/fuchsia/zircon/system/dev/i2c/imx-i2c/ |
H A D | imx-i2c-regs.h | 7 #include <hwreg/bitfields.h> 12 class SlaveAddressReg : public hwreg::RegisterBase<SlaveAddressReg, uint16_t> { 15 static auto Get() { return hwreg::RegisterAddr<SlaveAddressReg>(0x0); } 18 class FreqReg : public hwreg::RegisterBase<FreqReg, uint16_t> { 21 static auto Get() { return hwreg::RegisterAddr<FreqReg>(0x4); } 24 class ControlReg : public hwreg::RegisterBase<ControlReg, uint16_t, hwreg::EnablePrinter> { 32 static auto Get() { return hwreg::RegisterAddr<ControlReg>(0x8); } 35 class StatusReg : public hwreg::RegisterBase<StatusReg, uint16_t, hwreg [all...] |
/fuchsia/zircon/system/dev/display/intel-i915/ |
H A D | registers.h | 7 #include <hwreg/bitfields.h> 15 class GmchGfxControl : public hwreg::RegisterBase<GmchGfxControl, uint16_t> { 42 static auto Get() { return hwreg::RegisterAddr<GmchGfxControl>(0); } 46 class BaseDsm : public hwreg::RegisterBase<BaseDsm, uint32_t> { 55 static auto Get() { return hwreg::RegisterAddr<BaseDsm>(0); } 59 class MasterInterruptControl : public hwreg::RegisterBase<MasterInterruptControl, uint32_t> { 67 static auto Get() { return hwreg::RegisterAddr<MasterInterruptControl>(0x44200); } 71 class GMBus0 : public hwreg::RegisterBase<GMBus0, uint32_t> { 78 static auto Get() { return hwreg::RegisterAddr<GMBus0>(0xc5100); } 82 class GMBus1 : public hwreg [all...] |
H A D | registers-ddi.h | 7 #include <hwreg/bitfields.h> 23 class SdeInterruptBase : public hwreg::RegisterBase<SdeInterruptBase, uint32_t> { 29 hwreg::BitfieldRef<uint32_t> ddi_bit(Ddi ddi) { 46 return hwreg::BitfieldRef<uint32_t>(reg_value_ptr(), bit, bit); 49 static auto Get(uint32_t offset) { return hwreg::RegisterAddr<SdeInterruptBase>(offset); } 53 class HotplugCtrl : public hwreg::RegisterBase<HotplugCtrl, uint32_t> { 55 hwreg::BitfieldRef<uint32_t> hpd_enable(Ddi ddi) { 57 return hwreg::BitfieldRef<uint32_t>(reg_value_ptr(), bit, bit); 60 hwreg::BitfieldRef<uint32_t> hpd_long_pulse(Ddi ddi) { 62 return hwreg [all...] |
H A D | registers-dpll.h | 8 #include <hwreg/bitfields.h> 28 class DpllControl1 : public hwreg::RegisterBase<DpllControl1, uint32_t> { 30 hwreg::BitfieldRef<uint32_t> dpll_hdmi_mode(Dpll dpll) { 32 return hwreg::BitfieldRef<uint32_t>(reg_value_ptr(), bit, bit); 35 hwreg::BitfieldRef<uint32_t> dpll_ssc_enable(Dpll dpll) { 37 return hwreg::BitfieldRef<uint32_t>(reg_value_ptr(), bit, bit); 40 hwreg::BitfieldRef<uint32_t> dpll_link_rate(Dpll dpll) { 42 return hwreg::BitfieldRef<uint32_t>(reg_value_ptr(), bit + 2, bit); 51 hwreg::BitfieldRef<uint32_t> dpll_override(Dpll dpll) { 53 return hwreg [all...] |
H A D | dpcd.h | 7 #include <hwreg/bitfields.h> 47 class LinkBw : public hwreg::RegisterBase<LinkBw, uint8_t> { 57 class LaneCount : public hwreg::RegisterBase<LaneCount, uint8_t> { 64 class TrainingPatternSet : public hwreg::RegisterBase<TrainingPatternSet, uint8_t> { 77 class TrainingLaneSet : public hwreg::RegisterBase<TrainingLaneSet, uint8_t> { 86 class LaneStatus : public hwreg::RegisterBase<LaneStatus, uint8_t> { 88 hwreg::BitfieldRef<uint8_t> lane_cr_done(int lane) { 90 return hwreg::BitfieldRef<uint8_t>(reg_value_ptr(), bit, bit); 93 hwreg::BitfieldRef<uint8_t> lane_channel_eq_done(int lane) { 95 return hwreg [all...] |
H A D | registers-transcoder.h | 7 #include <hwreg/bitfields.h> 22 class TransHVTotal : public hwreg::RegisterBase<TransHVTotal, uint32_t> { 29 class TransHVSync : public hwreg::RegisterBase<TransHVSync, uint32_t> { 36 class TransDdiFuncControl : public hwreg::RegisterBase<TransDdiFuncControl, uint32_t> { 64 class TransConf : public hwreg::RegisterBase<TransConf, uint32_t> { 72 class TransClockSelect : public hwreg::RegisterBase<TransClockSelect, uint32_t> { 79 class TransDataM : public hwreg::RegisterBase<TransDataM, uint32_t> { 86 class TransDataN : public hwreg::RegisterBase<TransDataN, uint32_t> { 92 class TransLinkM : public hwreg::RegisterBase<TransLinkM, uint32_t> { 98 class TransLinkN : public hwreg [all...] |
H A D | registers-pipe.h | 10 #include <hwreg/bitfields.h> 28 class PipeSourceSize : public hwreg::RegisterBase<PipeSourceSize, uint32_t> { 37 class PipeBottomColor : public hwreg::RegisterBase<PipeBottomColor, uint32_t> { 50 class PlaneSurface : public hwreg::RegisterBase<PlaneSurface, uint32_t> { 67 class PlaneSurfaceLive : public hwreg::RegisterBase<PlaneSurfaceLive, uint32_t> { 78 class PlaneSurfaceStride : public hwreg::RegisterBase<PlaneSurfaceStride, uint32_t> { 86 class PlaneSurfaceSize : public hwreg::RegisterBase<PlaneSurfaceSize, uint32_t> { 95 class PlaneControl : public hwreg::RegisterBase<PlaneControl, uint32_t> { 140 class PlaneBufCfg : public hwreg::RegisterBase<PlaneBufCfg, uint32_t> { 150 class PlaneWm : public hwreg [all...] |
/fuchsia/zircon/system/dev/serial/aml-uart/ |
H A D | registers.h | 5 #include <hwreg/bitfields.h> 13 class Control : public hwreg::RegisterBase<Control, uint32_t, hwreg::EnablePrinter> { 50 static auto Get() { return hwreg::RegisterAddr<Control>(0x8); } 53 class Status : public hwreg::RegisterBase<Status, uint32_t> { 69 static auto Get() { return hwreg::RegisterAddr<Status>(0xC); } 72 class Misc : public hwreg::RegisterBase<Misc, uint32_t> { 77 static auto Get() { return hwreg::RegisterAddr<Misc>(0x10); } 80 class Reg5 : public hwreg::RegisterBase<Reg5, uint32_t, hwreg [all...] |
/fuchsia/zircon/system/dev/display/astro-display/ |
H A D | vpu.h | 10 #include <hwreg/mmio.h> 44 fbl::unique_ptr<hwreg::RegisterIo> vpu_regs_; 45 fbl::unique_ptr<hwreg::RegisterIo> hhi_regs_; 46 fbl::unique_ptr<hwreg::RegisterIo> aobus_regs_; 47 fbl::unique_ptr<hwreg::RegisterIo> cbus_regs_;
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H A D | astro-clock.h | 12 #include <hwreg/mmio.h> 52 fbl::unique_ptr<hwreg::RegisterIo> vpu_regs_; 53 fbl::unique_ptr<hwreg::RegisterIo> hhi_regs_;
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H A D | osd.h | 10 #include <hwreg/mmio.h> 37 fbl::unique_ptr<hwreg::RegisterIo> vpu_regs_;
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H A D | aml-dsi-host.h | 11 #include <hwreg/mmio.h> 53 fbl::unique_ptr<hwreg::RegisterIo> mipi_dsi_regs_; 54 fbl::unique_ptr<hwreg::RegisterIo> hhi_regs_;
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H A D | aml-mipi-phy.h | 11 #include <hwreg/mmio.h> 66 fbl::unique_ptr<hwreg::RegisterIo> mipi_dsi_regs_; 67 fbl::unique_ptr<hwreg::RegisterIo> dsi_phy_regs_;
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/fuchsia/zircon/system/dev/thermal/aml-thermal-s905d2g/ |
H A D | hiu-registers.h | 5 #include <hwreg/bitfields.h> 10 class SysCpuClkControl0 : public hwreg::RegisterBase<SysCpuClkControl0, uint32_t> { 29 static auto Get() { return hwreg::RegisterAddr<SysCpuClkControl0>(0x19C); }
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H A D | aml-tsensor-regs.h | 5 #include <hwreg/bitfields.h> 43 class TsCfgReg1 : public hwreg::RegisterBase<TsCfgReg1, uint32_t> { 75 static auto Get() { return hwreg::RegisterAddr<TsCfgReg1>(AML_TS_CFG_REG1); } 78 class TsCfgReg2 : public hwreg::RegisterBase<TsCfgReg2, uint32_t> { 85 static auto Get() { return hwreg::RegisterAddr<TsCfgReg2>(AML_TS_CFG_REG2); } 88 class TsCfgReg4 : public hwreg::RegisterBase<TsCfgReg4, uint32_t> { 93 static auto Get() { return hwreg::RegisterAddr<TsCfgReg4>(0); } 96 class TsCfgReg6 : public hwreg::RegisterBase<TsCfgReg6, uint32_t> { 101 static auto Get() { return hwreg::RegisterAddr<TsCfgReg6>(0); } 104 class TsStat0 : public hwreg [all...] |
H A D | aml-tsensor.h | 12 #include <hwreg/mmio.h> 47 fbl::unique_ptr<hwreg::RegisterIo> pll_regs_; 48 fbl::unique_ptr<hwreg::RegisterIo> ao_regs_; 49 fbl::unique_ptr<hwreg::RegisterIo> hiu_regs_;
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H A D | aml-pwm.h | 12 #include <hwreg/mmio.h> 39 fbl::unique_ptr<hwreg::RegisterIo> pwm_regs_;
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/fuchsia/zircon/system/dev/display/vim-display/ |
H A D | registers.h | 8 #include <hwreg/bitfields.h> 9 #include <hwreg/mmio.h> 12 class VdIfGenReg : public hwreg::RegisterBase<VdIfGenReg, uint32_t> { 42 class VdIfCanvas0 : public hwreg::RegisterBase<VdIfCanvas0, uint32_t> { 47 class VdIfLumaX0 : public hwreg::RegisterBase<VdIfLumaX0, uint32_t> { 54 class VdIfLumaY0 : public hwreg::RegisterBase<VdIfLumaY0, uint32_t> { 61 class VdIfChromaX0 : public hwreg::RegisterBase<VdIfChromaX0, uint32_t> { 68 class VdIfChromaY0 : public hwreg::RegisterBase<VdIfChromaY0, uint32_t> { 75 class VdIfGenReg2 : public hwreg::RegisterBase<VdIfGenReg2, uint32_t> { 82 class VdFmtCtrl : public hwreg [all...] |
/fuchsia/zircon/system/dev/pci/amlogic-pcie/ |
H A D | aml-pcie-clk.cpp | 9 #include <hwreg/bitfields.h> 10 #include <hwreg/mmio.h> 37 class MesonPLLControl0 : public hwreg::RegisterBase<MesonPLLControl0, uint32_t> { 46 static auto Get() {return hwreg::RegisterAddr<MesonPLLControl0>(0); } 49 class MesonPLLControl1 : public hwreg::RegisterBase<MesonPLLControl1, uint32_t> { 65 static auto Get() {return hwreg::RegisterAddr<MesonPLLControl1>(0); } 68 class MesonPLLControl6 : public hwreg::RegisterBase<MesonPLLControl6, uint32_t> { 75 static auto Get() { return hwreg::RegisterAddr<MesonPLLControl6>(0); } 95 hwreg::RegisterIo cntl0_mmio(regs + PCIE_PLL_CNTL0); 96 hwreg [all...] |
/fuchsia/zircon/system/utest/libhwreg/ |
H A D | bitfields-test.cpp | 11 #include <hwreg/bitfields.h> 12 #include <hwreg/mmio.h> 17 class TestReg32 : public hwreg::RegisterBase<TestReg32, uint32_t> { 27 static auto Get() { return hwreg::RegisterAddr<TestReg32>(0); } 31 hwreg::RegisterIo mmio(&fake_reg); 150 class TestReg8 : public hwreg::RegisterBase<TestReg8, uint8_t> { 154 static auto Get() { return hwreg::RegisterAddr<TestReg8>(0); } 156 class TestReg16 : public hwreg::RegisterBase<TestReg16, uint16_t> { 160 static auto Get() { return hwreg::RegisterAddr<TestReg16>(0); } 162 class TestReg32 : public hwreg [all...] |
/fuchsia/zircon/system/dev/pci/designware/ |
H A D | dw-pcie-hw.h | 7 #include <hwreg/bitfields.h> 8 #include <hwreg/mmio.h> 17 class DebugR1 : public hwreg::RegisterBase<DebugR1, uint32_t> { 21 static auto Get() {return hwreg::RegisterAddr<DebugR1>(0); }
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/fuchsia/zircon/kernel/dev/iommu/intel/ |
H A D | hw.h | 10 #include <hwreg/bitfields.h> 19 class Version : public hwreg::RegisterBase<Version, uint32_t> { 22 static auto Get() { return hwreg::RegisterAddr<Version>(kAddr); } 29 class Capability : public hwreg::RegisterBase<Capability, uint64_t> { 32 static auto Get() { return hwreg::RegisterAddr<Capability>(kAddr); } 65 class ExtendedCapability : public hwreg::RegisterBase<ExtendedCapability, uint64_t> { 68 static auto Get() { return hwreg::RegisterAddr<ExtendedCapability>(kAddr); } 96 class GlobalControl : public hwreg::RegisterBase<GlobalControl, uint32_t> { 100 static auto Get() { return hwreg::RegisterAddr<GlobalControl>(kReadAddr); } 115 GlobalControl& ReadFrom(hwreg [all...] |
/fuchsia/zircon/system/ulib/hwreg/include/hwreg/ |
H A D | bitfields.h | 7 #include <hwreg/internal.h> 8 #include <hwreg/mmio.h> 20 // class AuxControl : public hwreg::RegisterBase<AuxControl, uint32_t> { 30 // static auto Get() { return hwreg::RegisterAddr<AuxControl>(0x64010); } 33 // void Example1(hwreg::RegisterIo* reg_io) { 49 // void Example2(hwreg::RegisterIo* reg_io) { 57 // void Example3(hwreg::RegisterIo* reg_io) { 77 namespace hwreg { namespace 137 static_assert(PrinterEnabled::value, "Pass hwreg::EnablePrinter to RegisterBase to enable"); 144 static_assert(PrinterEnabled::value, "Pass hwreg [all...] |
H A D | mmio.h | 7 #include <hwreg/internal.h> 11 namespace hwreg { namespace 44 } // namespace hwreg
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/fuchsia/zircon/system/ulib/hwreg/ |
H A D | printers.cpp | 5 #include <hwreg/internal.h> 8 namespace hwreg { namespace 38 } // namespace hwreg
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