Searched refs:rd32 (Results 1 - 25 of 31) sorted by relevance

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/freebsd-current/sys/dev/ixl/
H A Dixl_pf_i2c.c77 u32 i2cctl = rd32(hw, IXL_I2C_REG(hw));
114 u32 i2cctl = rd32(hw, IXL_I2C_REG(hw));
165 u32 i2cctl = rd32(hw, IXL_I2C_REG(hw));
174 i2cctl = rd32(hw, IXL_I2C_REG(hw));
179 i2cctl = rd32(hw, IXL_I2C_REG(hw));
202 u32 i2cctl = rd32(hw, IXL_I2C_REG(hw));
211 i2cctl = rd32(hw, IXL_I2C_REG(hw));
219 i2cctl = rd32(hw, IXL_I2C_REG(hw));
252 u32 i2cctl = rd32(hw, IXL_I2C_REG(hw));
302 i2cctl = rd32(h
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H A Di40e_adminq.c318 reg = rd32(hw, hw->aq.asq.bal);
354 reg = rd32(hw, hw->aq.arq.bal);
789 while (rd32(hw, hw->aq.asq.head) != ntc) {
791 "ntc %d head %d.\n", ntc, rd32(hw, hw->aq.asq.head));
826 return rd32(hw, hw->aq.asq.head) == hw->aq.asq.next_to_use;
866 val = rd32(hw, hw->aq.asq.head);
1023 if (rd32(hw, hw->aq.asq.len) & I40E_GL_ATQLEN_ATQCRIT_MASK) {
1094 ntu = rd32(hw, hw->aq.arq.head) & I40E_PF_ARQH_ARQH_MASK;
1096 ntu = rd32(hw, hw->aq.arq.head) & I40E_VF_ARQH1_ARQH_MASK;
H A Dixl_pf_iflib.c91 icr0 = rd32(hw, I40E_PFINT_ICR0);
145 reg = rd32(hw, I40E_PFINT_ICR0);
150 mask = rd32(hw, I40E_PFINT_ICR0_ENA);
167 rstat_reg = rd32(hw, I40E_GLGEN_RSTAT);
210 reg = rd32(hw, I40E_PFHMC_ERRORINFO);
214 reg = rd32(hw, I40E_PFHMC_ERRORDATA);
778 val = rd32(tx_que->vsi->hw, tx_que->txr.tail);
800 val = rd32(rx_que->vsi->hw, rx_que->rxr.tail);
H A Dixl_pf_main.c243 fwsts = rd32(hw, I40E_GL_FWSTS) & I40E_GL_FWSTS_FWS1B_MASK;
785 rd32(hw, I40E_PFINT_ICR0); /* read to clear */
1693 reg = rd32(hw, I40E_QTX_ENA(pf_qidx));
1699 reg = rd32(hw, I40E_QTX_ENA(pf_qidx));
1727 reg = rd32(hw, I40E_QRX_ENA(pf_qidx));
1733 reg = rd32(hw, I40E_QRX_ENA(pf_qidx));
1780 reg = rd32(hw, I40E_QTX_ENA(pf_qidx));
1785 reg = rd32(hw, I40E_QTX_ENA(pf_qidx));
1816 reg = rd32(hw, I40E_QRX_ENA(pf_qidx));
1821 reg = rd32(h
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H A Di40e_lan_hmc.c135 obj->max_cnt = rd32(hw, I40E_GLHMC_LANQMAX);
138 size_exp = rd32(hw, I40E_GLHMC_LANTXOBJSZ);
155 obj->max_cnt = rd32(hw, I40E_GLHMC_LANQMAX);
161 size_exp = rd32(hw, I40E_GLHMC_LANRXOBJSZ);
178 obj->max_cnt = rd32(hw, I40E_GLHMC_FCOEMAX);
184 size_exp = rd32(hw, I40E_GLHMC_FCOEDDPOBJSZ);
201 obj->max_cnt = rd32(hw, I40E_GLHMC_FCOEFMAX);
207 size_exp = rd32(hw, I40E_GLHMC_FCOEFOBJSZ);
H A Di40e_nvm.c58 gens = rd32(hw, I40E_GLNVM_GENS);
65 fla = rd32(hw, I40E_GLNVM_FLA);
102 gtime = rd32(hw, I40E_GLVFGEN_TIMER);
118 gtime = rd32(hw, I40E_GLVFGEN_TIMER);
187 srctl = rd32(hw, I40E_GLNVM_SRCTL);
234 sr_reg = rd32(hw, I40E_GLNVM_SRDATA);
1331 gtime = rd32(hw, I40E_GLVFGEN_TIMER);
H A Di40e_common.c399 return !!(rd32(hw, hw->aq.asq.len) &
402 return !!(rd32(hw, hw->aq.asq.len) &
1014 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
1017 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
1019 func_rid = rd32(hw, I40E_PF_FUNC_RID);
1166 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1307 reg = rd32(hw, I40E_GLGEN_RSTAT);
1338 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1345 reg = rd32(hw, I40E_GLGEN_RSTAT);
1357 reg = rd32(h
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H A Di40e_osdep.h223 #define rd32(a, reg) rd32_osdep((a)->back, (reg)) macro
H A Dixl_pf_iov.c363 ciad = rd32(hw, I40E_PF_PCI_CIAD);
382 vfrtrig = rd32(hw, I40E_VPGEN_VFRTRIG(vf->vf_num));
410 vfrstat = rd32(hw, I40E_VPGEN_VFRSTAT(vf->vf_num));
420 vfrtrig = rd32(hw, I40E_VPGEN_VFRTRIG(vf->vf_num));
1535 icr0 = rd32(hw, I40E_PFINT_ICR0_ENA);
1549 vflrstat = rd32(hw, I40E_GLGEN_VFLRSTAT(vflrstat_index));
H A Di40e_dcb.c52 reg = rd32(hw, I40E_PRTDCB_GENS);
/freebsd-current/sys/dev/irdma/
H A Dicrdma_hw.c262 lfc &= (rd32(vsi->dev->hw,
264 lfc &= (rd32(vsi->dev->hw,
266 lfc &= rd32(vsi->dev->hw,
280 value = rd32(vsi->dev->hw, reg_offset);
295 pause = (rd32(vsi->dev->hw,
298 pause &= (rd32(vsi->dev->hw,
393 wqm_data = rd32(hw, GLPE_WQMTXIDXDATA);
406 wqm_data = rd32(hw, GLPE_WQMTXIDXDATA);
417 val = rd32(hw, GL_RDPU_CNTRL);
H A Dosdep.h183 #define rd32(a, reg) irdma_rd32((a)->dev_context, (reg)) macro
/freebsd-current/sys/dev/ice/
H A Dice_controlq.c95 return (rd32(hw, cq->sq.len) & (cq->sq.len_mask |
265 if (rd32(hw, ring->bal) != ICE_LO_DWORD(ring->desc_buf.pa))
832 while (rd32(hw, cq->sq.head) != ntc) {
833 ice_debug(hw, ICE_DBG_AQ_MSG, "ntc %d head %d.\n", ntc, rd32(hw, cq->sq.head));
931 return rd32(hw, cq->sq.head) == cq->sq.next_to_use;
990 val = rd32(hw, cq->sq.head);
1097 if (rd32(hw, cq->rq.len) & cq->rq.len_crit_mask ||
1098 rd32(hw, cq->sq.len) & cq->sq.len_crit_mask) {
1195 ntu = (u16)(rd32(hw, cq->rq.head) & cq->rq.head_mask);
1250 ntu = (u16)(rd32(h
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H A Dice_osdep.h85 uint32_t rd32(struct ice_hw *hw, uint32_t reg);
90 #define ice_flush(_hw) rd32((_hw), GLGEN_STAT)
H A Dice_osdep.c184 * rd32 - Read a 32bit hardware register value
191 rd32(struct ice_hw *hw, uint32_t reg) function
H A Dice_common.c727 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(IDX_OF_LFC));
733 val = rd32(hw, PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(IDX_OF_LFC));
883 u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) &
951 hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) &
1146 grst_timeout = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >>
1151 reg = rd32(hw, GLGEN_RSTAT);
1176 reg = rd32(hw, GLNVM_ULD) & uld_mask;
1209 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) ||
1210 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) {
1219 reg = rd32(h
[all...]
H A Dice_nvm.c1418 gens_stat = rd32(hw, GLNVM_GENS);
1425 fla = rd32(hw, GLNVM_FLA);
2053 data->regval = rd32(hw, cmd->offset);
H A Dice_lib.c1444 val = rd32(hw, QINT_RQCTL(reg));
1481 val = rd32(hw, QINT_TQCTL(reg));
1713 regval = rd32(hw, QRXFLXP_CNTXT(pf_q));
1783 qrx_ctrl = rd32(hw, QRX_CTRL(pf_q));
2099 val = rd32(hw, cq->rq.len);
2118 val = rd32(hw, cq->sq.len);
4636 info = rd32(hw, PFHMC_ERRORINFO);
4637 data = rd32(hw, PFHMC_ERRORDATA);
5164 rd32(hw, PFINT_OICR);
6330 if (rd32(h
[all...]
H A Dice_rdma.c381 up2tc = rd32(hw, PRTDCB_TUP2TC);
H A Dice_lib.h801 return (u8)((rd32(hw, PF_FUNC_RID) & PF_FUNC_RID_FUNCTION_NUMBER_M) >>
/freebsd-current/sys/dev/iavf/
H A Diavf_adminq.c299 reg = rd32(hw, hw->aq.asq.bal);
331 reg = rd32(hw, hw->aq.arq.bal);
618 while (rd32(hw, hw->aq.asq.head) != ntc) {
620 "ntc %d head %d.\n", ntc, rd32(hw, hw->aq.asq.head));
655 return rd32(hw, hw->aq.asq.head) == hw->aq.asq.next_to_use;
695 val = rd32(hw, hw->aq.asq.head);
852 if (rd32(hw, hw->aq.asq.len) & IAVF_VF_ATQLEN1_ATQCRIT_MASK) {
922 ntu = rd32(hw, hw->aq.arq.head) & IAVF_VF_ARQH1_ARQH_MASK;
H A Diavf_lib.c205 reg = rd32(hw, IAVF_VFGEN_RSTAT) &
376 rd32(hw, IAVF_VFGEN_RSTAT);
1125 hena = (u64)rd32(hw, IAVF_VFQF_HENA(0)) |
1126 ((u64)rd32(hw, IAVF_VFQF_HENA(1)) << 32);
H A Diavf_osdep.c376 rd32(hw, osdep->flush_reg);
H A Diavf_osdep.h246 #define rd32(hw, reg) iavf_rd32(hw, reg) macro
H A Dif_iavf_iflib.c1136 oldreg = reg = rd32(hw, hw->aq.arq.len);
1163 oldreg = reg = rd32(hw, hw->aq.asq.len);
1239 reg = rd32(hw, IAVF_VFINT_ICR0_ENA1);
1385 val = rd32(hw, IAVF_VFGEN_RSTAT) &
1599 reg = rd32(hw, IAVF_VFINT_ICR01);
1604 mask = rd32(hw, IAVF_VFINT_ICR0_ENA1);
1685 rd32(hw, IAVF_VFGEN_RSTAT);

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