Searched refs:pci_read_config (Results 1 - 25 of 206) sorted by relevance

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/freebsd-current/sys/dev/qat/qat_hw/qat_c4xxx/
H A Dadf_c4xxx_reset.c12 uncorr_err = pci_read_config(pdev, PCI_EXP_AERUCS, 4);
32 device_id1 = pci_read_config(pdev, PCIR_DEVICE, 2);
38 device_id2 = pci_read_config(pdev, PCIR_DEVICE, 2);
69 pmisclbar1 = pci_read_config(pdev, ADF_PMISC_L_OFFSET, 4);
70 pmiscubar1 = pci_read_config(pdev, ADF_PMISC_U_OFFSET, 4);
76 pmisclbar2 = pci_read_config(pdev, ADF_PMISC_L_OFFSET, 4);
77 pmiscubar2 = pci_read_config(pdev, ADF_PMISC_U_OFFSET, 4);
/freebsd-current/sys/dev/agp/
H A Dagp_intel.c154 value = pci_read_config(dev, AGP_INTEL_AGPCTRL, 4);
163 (pci_read_config(dev, AGP_INTEL_I820_RDCR, 1)
173 (pci_read_config(dev, AGP_INTEL_I845_AGPM, 1)
182 (pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
187 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
229 value = pci_read_config(dev, AGP_INTEL_APSIZE, 1);
231 sc->aperture_mask = pci_read_config(dev, AGP_INTEL_APSIZE, 1) &
271 reg = pci_read_config(dev, AGP_INTEL_I820_RDCR, 1) & ~(1 << 1);
281 reg = pci_read_config(dev, AGP_INTEL_I845_AGPM, 1) & ~(1 << 1);
290 reg = pci_read_config(de
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H A Dagp_via.c170 capid = pci_read_config(dev, agp_find_caps(dev) + AGP_CAPID, 4);
172 agpsel = pci_read_config(dev, AGP_VIA_AGPSEL, 1);
212 gartctrl = pci_read_config(dev, sc->regs[REG_GARTCTRL], 4);
245 apsize = pci_read_config(dev, sc->regs[REG_APSIZE], 1);
256 apsize = pci_read_config(dev, sc->regs[REG_APSIZE], 2) & 0xfff;
280 pci_read_config(dev, sc->regs[REG_APSIZE], 2));
342 val = pci_read_config(dev, sc->regs[REG_APSIZE], 2);
383 gartctrl = pci_read_config(dev, sc->regs[REG_GARTCTRL], 4);
H A Dagp_ati.c151 apbase_offset = pci_read_config(dev, AGP_APBASE, 4) >> 22;
223 temp = pci_read_config(dev, apsize_reg, 4);
230 temp = pci_read_config(dev, 4, 4); /* XXX: Magic reg# */
259 temp = pci_read_config(dev, apsize_reg, 4);
278 size_value = pci_read_config(dev, ATI_RS300_APSIZE, 4);
280 size_value = pci_read_config(dev, ATI_RS100_APSIZE, 4);
300 size_value = pci_read_config(dev, apsize_reg, 4);
H A Dagp_nvidia.c224 temp = pci_read_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, 4);
228 temp = pci_read_config(sc->dev, AGP_NVIDIA_0_APSIZE, 4);
246 temp = pci_read_config(sc->dev, AGP_NVIDIA_0_APSIZE, 4);
250 temp = pci_read_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, 4);
269 switch (pci_read_config(dev, AGP_NVIDIA_0_APSIZE, 1) & 0x0f) {
277 pci_read_config(dev, AGP_NVIDIA_0_APSIZE, 1));
299 val = pci_read_config(dev, AGP_NVIDIA_0_APSIZE, 1);
346 wbc_reg = pci_read_config(sc->mc1_dev, AGP_NVIDIA_1_WBC, 4);
352 wbc_reg = pci_read_config(sc->mc1_dev,
H A Dagp_ali.c127 attbase = pci_read_config(dev, AGP_ALI_ATTBASE, 4);
150 attbase = pci_read_config(dev, AGP_ALI_ATTBASE, 4);
182 int i = pci_read_config(dev, AGP_ALI_ATTBASE, 4) & 0xf;
200 attbase = pci_read_config(dev, AGP_ALI_ATTBASE, 4);
H A Dagp_sis.c158 pci_read_config(dev, AGP_SIS_WINCTRL, 1) | 3, 1);
178 pci_read_config(dev, AGP_SIS_WINCTRL, 1) & ~3, 1);
199 gws = (pci_read_config(dev, AGP_SIS_WINCTRL, 1) & 0x70) >> 4;
220 ((pci_read_config(dev, AGP_SIS_WINCTRL, 1) & ~0x70)
/freebsd-current/sys/dev/ata/chipsets/
H A Data-ati.c152 satacfg = pci_read_config(smbdev, 0xad, 1);
220 (pci_read_config(parent, 0x56, 2) &
224 pci_read_config(parent, 0x54, 1) |
227 (pci_read_config(parent, 0x44, 4) &
234 pci_read_config(parent, 0x54, 1) &
237 (pci_read_config(parent, 0x44, 4) &
245 pci_read_config(parent, 0x54, 1) &
251 (pci_read_config(parent, 0x4a, 2) &
255 (pci_read_config(parent, 0x40, 4) &
H A Data-ite.c98 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) & ~0x83, 1);
141 (pci_read_config(parent, 0x40, 2) &
149 pci_read_config(parent, 0x50, 1) &
159 pci_read_config(parent, 0x50, 1) |
176 u_int16_t reg40 = pci_read_config(parent, 0x40, 2);
177 u_int8_t reg44 = pci_read_config(parent, 0x44, 1);
178 u_int8_t reg48 = pci_read_config(parent, 0x48, 1);
179 u_int16_t reg4a = pci_read_config(parent, 0x4a, 2);
180 u_int16_t reg54 = pci_read_config(parent, 0x54, 2);
H A Data-sis.c117 u_int8_t reg57 = pci_read_config(dev, 0x57, 1);
120 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5518) {
131 u_int8_t reg4a = pci_read_config(dev, 0x4a, 1);
134 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5517) {
172 pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 1) & ~0x04, 1);
176 pci_write_config(dev, 0x49, pci_read_config(dev, 0x49, 1) & ~0x01, 1);
179 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 2) | 0x0008, 2);
180 pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 2) | 0x0008, 2);
249 pci_read_config(parent, ch->unit ? 0x52 : 0x50,2) & 0x8000) {
255 pci_read_config(paren
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H A Data-highpoint.c117 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x80), 1);
121 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x03), 1);
122 pci_write_config(dev, 0x55, (pci_read_config(dev, 0x55, 1) & ~0x03), 1);
125 pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
132 (pci_read_config(dev, 0x5b, 1) & 0x01) | 0x20, 1);
205 val = pci_read_config(parent, reg, 1);
210 val = pci_read_config(parent, reg, 1);
213 res = pci_read_config(parent, 0x5a, 1) & (ch->unit ? 0x1:0x2);
H A Data-siliconimage.c117 (pci_read_config(dev, 0x8a, 1) & 1))
122 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
124 (pci_read_config(dev, 0x8a, 1) & 0xcf)|0x10,1);
125 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
138 (pci_read_config(dev, 0x48, 4) & ~0x03c00000), 4);
141 pci_write_config(dev, 0x8a, (pci_read_config(dev, 0x8a, 1) & 0x3f), 1);
158 if ((pci_read_config(dev, 0x51, 1) & 0x08) != 0x08) {
198 if (((reg71 = pci_read_config(device_get_parent(dev), 0x71, 1)) &
225 u_int8_t umode = pci_read_config(parent, ureg, 1);
233 pci_read_config(paren
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H A Data-serverworks.c154 (pci_read_config(children[i], 0x64, 4) &
163 pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x40) |
327 (pci_read_config(parent, 0x56, 2) &
331 pci_read_config(parent, 0x54, 1) |
334 (pci_read_config(parent, 0x44, 4) &
341 pci_read_config(parent, 0x54, 1) &
344 (pci_read_config(parent, 0x44, 4) &
352 pci_read_config(parent, 0x54, 1) &
359 (pci_read_config(parent, 0x4a, 2) &
364 (pci_read_config(paren
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H A Data-amd.c97 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) & 0x0f, 1);
99 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) | 0xf0, 1);
123 !(pci_read_config(parent, 0x42, 1) & (1 << devno))) {
H A Data-acerlabs.c139 pci_write_config(dev, 0x4a, pci_read_config(dev, 0x4a, 1) | 0x20, 1);
143 pci_write_config(dev, 0x4b, pci_read_config(dev, 0x4b, 1) |
147 pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) |
163 pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x03, 1);
277 pci_read_config(children[i], 0x58, 1) &
280 pci_read_config(children[i], 0x58, 1) |
309 pci_read_config(parent, 0x4a, 1) & (1 << ch->unit)) {
326 word54 = pci_read_config(parent, 0x54, 4);
/freebsd-current/sys/dev/e1000/
H A De1000_osdep.c52 *value = pci_read_config(((struct e1000_osdep *)hw->back)->dev, reg, 2);
79 *value = pci_read_config(dev, offset + reg, 2);
/freebsd-current/sys/dev/pci/
H A Dfixup_pci.c89 pmccfg = pci_read_config(dev, 0x50, 2);
130 val = pci_read_config(dev, 0x6c, 4);
H A Dpci.c185 DEVMETHOD(pci_read_config, pci_read_config_method),
1442 val = pci_read_config(child, ptr + PCIR_HT_COMMAND, 2);
1474 KASSERT(pci_read_config(child, start + PCICAP_ID, 1) == PCIY_HT,
1487 val = pci_read_config(child, ptr + PCIR_HT_COMMAND, 2);
1520 status = pci_read_config(child, PCIR_STATUS, 2);
1539 ptr = pci_read_config(child, ptr, 1);
1545 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) {
1550 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1);
1567 KASSERT(pci_read_config(child, start + PCICAP_ID, 1) == capability,
1570 ptr = pci_read_config(chil
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H A Dpci_pci.c229 val = pci_read_config(dev, PCIR_IOBASEL_1, 1);
246 val = pci_read_config(dev, PCIR_PMBASEL_1, 2);
498 val = pci_read_config(dev, PCIR_IOBASEL_1, 1);
505 if (pci_read_config(dev, PCIR_IOBASEL_1, 1) != 0) {
520 pci_read_config(dev, PCIR_IOBASEH_1, 2), val);
522 pci_read_config(dev, PCIR_IOLIMITH_1, 2),
523 pci_read_config(dev, PCIR_IOLIMITL_1, 1));
528 pci_read_config(dev, PCIR_IOLIMITL_1, 1));
541 pci_read_config(dev, PCIR_MEMBASE_1, 2));
543 pci_read_config(de
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/freebsd-current/sys/dev/mlx5/mlx5_core/
H A Dmlx5_vsc.c50 if (pci_read_config(dev, vsc_addr + MLX5_VSC_SEMA_OFFSET, 4)) {
60 counter = pci_read_config(dev, vsc_addr + MLX5_VSC_COUNTER_OFFSET, 4);
62 lock_val = pci_read_config(dev, vsc_addr + MLX5_VSC_SEMA_OFFSET, 4);
98 flag = pci_read_config(dev, vsc_addr + MLX5_VSC_ADDR_OFFSET, 4);
122 vsc_space = pci_read_config(dev, vsc_addr + MLX5_VSC_SPACE_OFFSET, 4);
177 *data = pci_read_config(dev, vsc_addr + MLX5_VSC_DATA_OFFSET, 4);
195 id = pci_read_config(dev, vsc_addr + MLX5_VSC_COUNTER_OFFSET, 4);
/freebsd-current/sys/dev/qat_c2xxx/
H A Dqat_c2xxx.c85 fusectl = pci_read_config(sc->sc_dev, FUSECTL_REG, 4);
95 fusectl = pci_read_config(sc->sc_dev, FUSECTL_REG, 4);
120 fusectl = pci_read_config(sc->sc_dev, FUSECTL_REG, 4);
/freebsd-current/sys/i386/i386/
H A Dmp_clock.c116 d = pci_read_config(dev, PCIR_COMMAND, 2);
129 d = pci_read_config(dev, 0x40, 4);
/freebsd-current/sys/dev/mpt/
H A Dmpt_pci.c382 val = pci_read_config(dev, PCIR_COMMAND, 2);
390 val = pci_read_config(dev, PCIR_BIOS, 4);
416 val = pci_read_config(dev, PCIR_BAR(0), 4);
731 mpt->pci_cfg.Command = pci_read_config(mpt->dev, PCIR_COMMAND, 2);
733 pci_read_config(mpt->dev, PCIR_CACHELNSZ, 2);
734 mpt->pci_cfg.IO_BAR = pci_read_config(mpt->dev, PCIR_BAR(0), 4);
735 mpt->pci_cfg.Mem0_BAR[0] = pci_read_config(mpt->dev, PCIR_BAR(1), 4);
736 mpt->pci_cfg.Mem0_BAR[1] = pci_read_config(mpt->dev, PCIR_BAR(2), 4);
737 mpt->pci_cfg.Mem1_BAR[0] = pci_read_config(mpt->dev, PCIR_BAR(3), 4);
738 mpt->pci_cfg.Mem1_BAR[1] = pci_read_config(mp
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/freebsd-current/sys/dev/proto/
H A Dproto_bus_pci.c67 if ((pci_read_config(dev, PCIR_HDRTYPE, 1) & PCIM_HDRTYPE) != 0)
94 val = pci_read_config(dev, rid, 4);
/freebsd-current/sys/dev/hptrr/
H A Dhptrr_os_bsd.c57 return pci_read_config(((PHBA)osext)->pcidev, offset, 1);
62 return pci_read_config(((PHBA)osext)->pcidev, offset, 2);
67 return pci_read_config(((PHBA)osext)->pcidev, offset, 4);
96 if (pci_read_config(hba->pcidev, hba->pcibar[index].rid, 4) & 1)

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