1/*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 1998 - 2008 S��ren Schmidt <sos@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification, immediately at the beginning of the file. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include <sys/param.h> 30#include <sys/module.h> 31#include <sys/systm.h> 32#include <sys/kernel.h> 33#include <sys/ata.h> 34#include <sys/bus.h> 35#include <sys/endian.h> 36#include <sys/malloc.h> 37#include <sys/lock.h> 38#include <sys/mutex.h> 39#include <sys/sema.h> 40#include <sys/taskqueue.h> 41#include <vm/uma.h> 42#include <machine/stdarg.h> 43#include <machine/resource.h> 44#include <machine/bus.h> 45#include <sys/rman.h> 46#include <dev/pci/pcivar.h> 47#include <dev/pci/pcireg.h> 48#include <dev/ata/ata-all.h> 49#include <dev/ata/ata-pci.h> 50#include <ata_if.h> 51 52/* local prototypes */ 53static int ata_cmd_ch_attach(device_t dev); 54static int ata_cmd_status(device_t dev); 55static int ata_cmd_setmode(device_t dev, int target, int mode); 56static int ata_sii_ch_attach(device_t dev); 57static int ata_sii_ch_detach(device_t dev); 58static int ata_sii_status(device_t dev); 59static void ata_sii_reset(device_t dev); 60static int ata_sii_setmode(device_t dev, int target, int mode); 61 62/* misc defines */ 63#define SII_MEMIO 1 64#define SII_INTR 0x01 65#define SII_SETCLK 0x02 66#define SII_BUG 0x04 67#define SII_4CH 0x08 68 69/* 70 * Silicon Image Inc. (SiI) (former CMD) chipset support functions 71 */ 72static int 73ata_sii_probe(device_t dev) 74{ 75 struct ata_pci_controller *ctlr = device_get_softc(dev); 76 static const struct ata_chip_id ids[] = 77 {{ ATA_SII3114, 0x00, SII_MEMIO, SII_4CH, ATA_SA150, "3114" }, 78 { ATA_SII3512, 0x02, SII_MEMIO, 0, ATA_SA150, "3512" }, 79 { ATA_SII3112, 0x02, SII_MEMIO, 0, ATA_SA150, "3112" }, 80 { ATA_SII3112_1, 0x02, SII_MEMIO, 0, ATA_SA150, "3112" }, 81 { ATA_SII3512, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3512" }, 82 { ATA_SII3112, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3112" }, 83 { ATA_SII3112_1, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3112" }, 84 { ATA_SII0680, 0x00, SII_MEMIO, SII_SETCLK, ATA_UDMA6, "680" }, 85 { ATA_CMD649, 0x00, 0, SII_INTR, ATA_UDMA5, "(CMD) 649" }, 86 { ATA_CMD648, 0x00, 0, SII_INTR, ATA_UDMA4, "(CMD) 648" }, 87 { ATA_CMD646, 0x07, 0, 0, ATA_UDMA2, "(CMD) 646U2" }, 88 { ATA_CMD646, 0x00, 0, 0, ATA_WDMA2, "(CMD) 646" }, 89 { 0, 0, 0, 0, 0, 0}}; 90 91 if (pci_get_vendor(dev) != ATA_SILICON_IMAGE_ID) 92 return ENXIO; 93 94 if (!(ctlr->chip = ata_match_chip(dev, ids))) 95 return ENXIO; 96 97 ata_set_desc(dev); 98 ctlr->chipinit = ata_sii_chipinit; 99 return (BUS_PROBE_LOW_PRIORITY); 100} 101 102int 103ata_sii_chipinit(device_t dev) 104{ 105 struct ata_pci_controller *ctlr = device_get_softc(dev); 106 107 if (ata_setup_interrupt(dev, ata_generic_intr)) 108 return ENXIO; 109 110 switch (ctlr->chip->cfg1) { 111 case SII_MEMIO: 112 ctlr->r_type2 = SYS_RES_MEMORY; 113 ctlr->r_rid2 = PCIR_BAR(5); 114 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 115 &ctlr->r_rid2, RF_ACTIVE))){ 116 if (ctlr->chip->chipid != ATA_SII0680 || 117 (pci_read_config(dev, 0x8a, 1) & 1)) 118 return ENXIO; 119 } 120 121 if (ctlr->chip->cfg2 & SII_SETCLK) { 122 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10) 123 pci_write_config(dev, 0x8a, 124 (pci_read_config(dev, 0x8a, 1) & 0xcf)|0x10,1); 125 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10) 126 device_printf(dev, "%s could not set ATA133 clock\n", 127 ctlr->chip->text); 128 } 129 130 /* if we have 4 channels enable the second set */ 131 if (ctlr->chip->cfg2 & SII_4CH) { 132 ATA_OUTL(ctlr->r_res2, 0x0200, 0x00000002); 133 ctlr->channels = 4; 134 } 135 136 /* dont block interrupts from any channel */ 137 pci_write_config(dev, 0x48, 138 (pci_read_config(dev, 0x48, 4) & ~0x03c00000), 4); 139 140 /* enable PCI interrupt as BIOS might not */ 141 pci_write_config(dev, 0x8a, (pci_read_config(dev, 0x8a, 1) & 0x3f), 1); 142 143 if (ctlr->r_res2) { 144 ctlr->ch_attach = ata_sii_ch_attach; 145 ctlr->ch_detach = ata_sii_ch_detach; 146 } 147 148 if (ctlr->chip->max_dma >= ATA_SA150) { 149 ctlr->reset = ata_sii_reset; 150 ctlr->setmode = ata_sata_setmode; 151 ctlr->getrev = ata_sata_getrev; 152 } 153 else 154 ctlr->setmode = ata_sii_setmode; 155 break; 156 157 default: 158 if ((pci_read_config(dev, 0x51, 1) & 0x08) != 0x08) { 159 device_printf(dev, "HW has secondary channel disabled\n"); 160 ctlr->channels = 1; 161 } 162 163 /* enable interrupt as BIOS might not */ 164 pci_write_config(dev, 0x71, 0x01, 1); 165 166 ctlr->ch_attach = ata_cmd_ch_attach; 167 ctlr->ch_detach = ata_pci_ch_detach; 168 ctlr->setmode = ata_cmd_setmode; 169 break; 170 } 171 return 0; 172} 173 174static int 175ata_cmd_ch_attach(device_t dev) 176{ 177 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 178 struct ata_channel *ch = device_get_softc(dev); 179 180 /* setup the usual register normal pci style */ 181 if (ata_pci_ch_attach(dev)) 182 return ENXIO; 183 184 if (ctlr->chip->cfg2 & SII_INTR) 185 ch->hw.status = ata_cmd_status; 186 187 ch->flags |= ATA_NO_ATAPI_DMA; 188 189 return 0; 190} 191 192static int 193ata_cmd_status(device_t dev) 194{ 195 struct ata_channel *ch = device_get_softc(dev); 196 u_int8_t reg71; 197 198 if (((reg71 = pci_read_config(device_get_parent(dev), 0x71, 1)) & 199 (ch->unit ? 0x08 : 0x04))) { 200 pci_write_config(device_get_parent(dev), 0x71, 201 reg71 & ~(ch->unit ? 0x04 : 0x08), 1); 202 return ata_pci_status(dev); 203 } 204 return 0; 205} 206 207static int 208ata_cmd_setmode(device_t dev, int target, int mode) 209{ 210 device_t parent = device_get_parent(dev); 211 struct ata_pci_controller *ctlr = device_get_softc(parent); 212 struct ata_channel *ch = device_get_softc(dev); 213 int devno = (ch->unit << 1) + target; 214 int treg = 0x54 + ((devno < 3) ? (devno << 1) : 7); 215 int ureg = ch->unit ? 0x7b : 0x73; 216 int piomode; 217 static const uint8_t piotimings[] = 218 { 0xa9, 0x57, 0x44, 0x32, 0x3f, 0x87, 0x32, 0x3f }; 219 static const uint8_t udmatimings[][2] = 220 { { 0x31, 0xc2 }, { 0x21, 0x82 }, { 0x11, 0x42 }, 221 { 0x25, 0x8a }, { 0x15, 0x4a }, { 0x05, 0x0a } }; 222 223 mode = min(mode, ctlr->chip->max_dma); 224 if (mode >= ATA_UDMA0) { 225 u_int8_t umode = pci_read_config(parent, ureg, 1); 226 227 umode &= ~(target == 0 ? 0x35 : 0xca); 228 umode |= udmatimings[mode & ATA_MODE_MASK][target]; 229 pci_write_config(parent, ureg, umode, 1); 230 piomode = ATA_PIO4; 231 } else { 232 pci_write_config(parent, ureg, 233 pci_read_config(parent, ureg, 1) & 234 ~(target == 0 ? 0x35 : 0xca), 1); 235 piomode = mode; 236 } 237 pci_write_config(parent, treg, piotimings[ata_mode2idx(piomode)], 1); 238 return (mode); 239} 240 241static int 242ata_sii_ch_attach(device_t dev) 243{ 244 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 245 struct ata_channel *ch = device_get_softc(dev); 246 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2); 247 int i; 248 249 for (i = ATA_DATA; i <= ATA_COMMAND; i++) { 250 ch->r_io[i].res = ctlr->r_res2; 251 ch->r_io[i].offset = 0x80 + i + (unit01 << 6) + (unit10 << 8); 252 } 253 ch->r_io[ATA_CONTROL].res = ctlr->r_res2; 254 ch->r_io[ATA_CONTROL].offset = 0x8a + (unit01 << 6) + (unit10 << 8); 255 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2; 256 ata_default_registers(dev); 257 258 ch->r_io[ATA_BMCMD_PORT].res = ctlr->r_res2; 259 ch->r_io[ATA_BMCMD_PORT].offset = 0x00 + (unit01 << 3) + (unit10 << 8); 260 ch->r_io[ATA_BMSTAT_PORT].res = ctlr->r_res2; 261 ch->r_io[ATA_BMSTAT_PORT].offset = 0x02 + (unit01 << 3) + (unit10 << 8); 262 ch->r_io[ATA_BMDTP_PORT].res = ctlr->r_res2; 263 ch->r_io[ATA_BMDTP_PORT].offset = 0x04 + (unit01 << 3) + (unit10 << 8); 264 265 if (ctlr->chip->max_dma >= ATA_SA150) { 266 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2; 267 ch->r_io[ATA_SSTATUS].offset = 0x104 + (unit01 << 7) + (unit10 << 8); 268 ch->r_io[ATA_SERROR].res = ctlr->r_res2; 269 ch->r_io[ATA_SERROR].offset = 0x108 + (unit01 << 7) + (unit10 << 8); 270 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2; 271 ch->r_io[ATA_SCONTROL].offset = 0x100 + (unit01 << 7) + (unit10 << 8); 272 ch->flags |= ATA_NO_SLAVE; 273 ch->flags |= ATA_SATA; 274 ch->flags |= ATA_KNOWN_PRESENCE; 275 276 /* enable PHY state change interrupt */ 277 ATA_OUTL(ctlr->r_res2, 0x148 + (unit01 << 7) + (unit10 << 8),(1 << 16)); 278 } 279 280 if (ctlr->chip->cfg2 & SII_BUG) { 281 /* work around errata in early chips */ 282 ch->dma.boundary = 8192; 283 ch->dma.segsize = 15 * DEV_BSIZE; 284 } 285 286 ata_pci_hw(dev); 287 ch->hw.status = ata_sii_status; 288 if (ctlr->chip->cfg2 & SII_SETCLK) 289 ch->flags |= ATA_CHECKS_CABLE; 290 291 ata_pci_dmainit(dev); 292 293 return 0; 294} 295 296static int 297ata_sii_ch_detach(device_t dev) 298{ 299 300 ata_pci_dmafini(dev); 301 return (0); 302} 303 304static int 305ata_sii_status(device_t dev) 306{ 307 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 308 struct ata_channel *ch = device_get_softc(dev); 309 int offset0 = ((ch->unit & 1) << 3) + ((ch->unit & 2) << 8); 310 int offset1 = ((ch->unit & 1) << 6) + ((ch->unit & 2) << 8); 311 312 /* do we have any PHY events ? */ 313 if (ctlr->chip->max_dma >= ATA_SA150 && 314 (ATA_INL(ctlr->r_res2, 0x10 + offset0) & 0x00000010)) 315 ata_sata_phy_check_events(dev, -1); 316 317 if (ATA_INL(ctlr->r_res2, 0xa0 + offset1) & 0x00000800) 318 return ata_pci_status(dev); 319 else 320 return 0; 321} 322 323static void 324ata_sii_reset(device_t dev) 325{ 326 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 327 struct ata_channel *ch = device_get_softc(dev); 328 int offset = ((ch->unit & 1) << 7) + ((ch->unit & 2) << 8); 329 uint32_t val; 330 331 /* Apply R_ERR on DMA activate FIS errata workaround. */ 332 val = ATA_INL(ctlr->r_res2, 0x14c + offset); 333 if ((val & 0x3) == 0x1) 334 ATA_OUTL(ctlr->r_res2, 0x14c + offset, val & ~0x3); 335 336 if (ata_sata_phy_reset(dev, -1, 1)) 337 ata_generic_reset(dev); 338 else 339 ch->devices = 0; 340} 341 342static int 343ata_sii_setmode(device_t dev, int target, int mode) 344{ 345 device_t parent = device_get_parent(dev); 346 struct ata_pci_controller *ctlr = device_get_softc(parent); 347 struct ata_channel *ch = device_get_softc(dev); 348 int rego = (ch->unit << 4) + (target << 1); 349 int mreg = ch->unit ? 0x84 : 0x80; 350 int mask = 0x03 << (target << 2); 351 int mval = pci_read_config(parent, mreg, 1) & ~mask; 352 int piomode; 353 u_int8_t preg = 0xa4 + rego; 354 u_int8_t dreg = 0xa8 + rego; 355 u_int8_t ureg = 0xac + rego; 356 static const uint16_t piotimings[] = 357 { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; 358 static const uint16_t dmatimings[] = { 0x2208, 0x10c2, 0x10c1 }; 359 static const uint8_t udmatimings[] = 360 { 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 }; 361 362 mode = min(mode, ctlr->chip->max_dma); 363 364 if (ctlr->chip->cfg2 & SII_SETCLK) { 365 if (ata_dma_check_80pin && mode > ATA_UDMA2 && 366 (pci_read_config(parent, 0x79, 1) & 367 (ch->unit ? 0x02 : 0x01))) { 368 ata_print_cable(dev, "controller"); 369 mode = ATA_UDMA2; 370 } 371 } 372 if (mode >= ATA_UDMA0) { 373 pci_write_config(parent, mreg, 374 mval | (0x03 << (target << 2)), 1); 375 pci_write_config(parent, ureg, 376 (pci_read_config(parent, ureg, 1) & ~0x3f) | 377 udmatimings[mode & ATA_MODE_MASK], 1); 378 piomode = ATA_PIO4; 379 } else if (mode >= ATA_WDMA0) { 380 pci_write_config(parent, mreg, 381 mval | (0x02 << (target << 2)), 1); 382 pci_write_config(parent, dreg, dmatimings[mode & ATA_MODE_MASK], 2); 383 piomode = (mode == ATA_WDMA0) ? ATA_PIO0 : 384 (mode == ATA_WDMA1) ? ATA_PIO3 : ATA_PIO4; 385 } else { 386 pci_write_config(parent, mreg, 387 mval | (0x01 << (target << 2)), 1); 388 piomode = mode; 389 } 390 pci_write_config(parent, preg, piotimings[ata_mode2idx(piomode)], 2); 391 return (mode); 392} 393 394ATA_DECLARE_DRIVER(ata_sii); 395