Searched refs:WRITE4 (Results 1 - 25 of 60) sorted by relevance

123

/freebsd-current/sys/arm/freescale/vybrid/
H A Dvf_dcu4.c229 WRITE4(sc, DCU_INT_STATUS, reg);
294 WRITE4(sc, DCU_DISP_SIZE, reg);
299 WRITE4(sc, DCU_HSYN_PARA, reg);
304 WRITE4(sc, DCU_VSYN_PARA, reg);
306 WRITE4(sc, DCU_BGND, 0);
307 WRITE4(sc, DCU_DIV_RATIO, panel->clk_div);
310 WRITE4(sc, DCU_SYNPOL, reg);
316 WRITE4(sc, DCU_THRESHOLD, reg);
319 WRITE4(sc, DCU_INT_MASK, 0xffffffff);
323 WRITE4(s
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H A Dvf_anadig.c140 WRITE4(sc, pll_ctrl, reg);
148 WRITE4(sc, pll_ctrl, reg);
168 WRITE4(sc, ANADIG_PLL4_CTRL, reg);
169 WRITE4(sc, ANADIG_PLL4_NUM, mfn);
170 WRITE4(sc, ANADIG_PLL4_DENOM, mfd);
208 WRITE4(sc, ANADIG_REG_3P0, reg);
213 WRITE4(sc, USB_MISC(0), reg);
217 WRITE4(sc, USB_MISC(1), reg);
H A Dvf_spi.c166 WRITE4(sc, SPI_MCR, reg);
170 WRITE4(sc, SPI_RSER, reg);
174 WRITE4(sc, SPI_MCR, reg);
192 WRITE4(sc, SPI_CTAR0, reg);
197 WRITE4(sc, SPI_CTAR0, reg);
222 WRITE4(sc, SPI_PUSHR, wreg);
233 WRITE4(sc, SPI_SR, reg);
H A Dvf_common.h31 #define WRITE4(_sc, _reg, _val) \ macro
H A Dvf_adc.c171 WRITE4(sc, ADC_HC0, reg);
208 WRITE4(sc, ADC_CFG, reg);
213 WRITE4(sc, ADC_GC, reg);
218 WRITE4(sc, ADC_HC0, reg);
/freebsd-current/sys/arm/freescale/imx/
H A Dimx_gpt.c50 #define WRITE4(_sc, _r, _v) \ macro
55 WRITE4((_sc), (_r), READ4((_sc), (_r)) | (_m))
57 WRITE4((_sc), (_r), READ4((_sc), (_r)) & ~(_m))
191 WRITE4(sc, IMX_GPT_CR, 0);
192 WRITE4(sc, IMX_GPT_IR, 0);
202 WRITE4(sc, IMX_GPT_CR, ctlreg);
212 WRITE4(sc, IMX_GPT_CR, ctlreg | GPT_CR_SWR);
225 WRITE4(sc, IMX_GPT_PR, prescale);
228 WRITE4(sc, IMX_GPT_SR, GPT_IR_ALL);
231 WRITE4(s
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H A Dimx6_sdma.c64 #define WRITE4(_sc, _reg, _val) \ macro
97 WRITE4(sc, SDMAARM_INTR, pending);
115 WRITE4(sc, SDMAARM_HSTART, (1 << i));
140 WRITE4(sc, SDMAARM_HSTART, (1 << chn));
152 WRITE4(sc, SDMAARM_STOP_STAT, (1 << chn));
219 WRITE4(sc, SDMAARM_EVTOVR, reg);
227 WRITE4(sc, SDMAARM_HOSTOVR, reg);
235 WRITE4(sc, SDMAARM_DSPOVR, reg);
263 WRITE4(sc, SDMAARM_SDMA_CHNPRI(chn), 1);
264 WRITE4(s
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H A Dimx6_audmux.c54 #define WRITE4(_sc, _reg, _val) \ macro
105 WRITE4(sc, AUDMUX_PTCR(audmux_port), reg);
109 WRITE4(sc, AUDMUX_PDCR(audmux_port), reg);
/freebsd-current/sys/dev/flash/
H A Dcqspi.c83 #define WRITE4(_sc, _reg, _val) bus_write_4((_sc)->res[0], _reg, _val) macro
159 WRITE4(sc, CQSPI_IRQSTAT, pending);
260 WRITE4(sc, CQSPI_FLASHCMDADDR, addr);
264 WRITE4(sc, CQSPI_FLASHCMD, reg);
267 WRITE4(sc, CQSPI_FLASHCMD, reg);
282 WRITE4(sc, CQSPI_FLASHCMD, reg);
284 WRITE4(sc, CQSPI_FLASHCMD, reg);
313 WRITE4(sc, CQSPI_FLASHCMD, reg);
316 WRITE4(sc, CQSPI_FLASHCMD, reg);
429 WRITE4(s
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/freebsd-current/sys/arm/altera/socfpga/
H A Dsocfpga_a10_manager.c117 WRITE4(sc, FPGAMGR_DCLKSTAT, 0x1);
120 WRITE4(sc, FPGAMGR_DCLKCNT, npulses);
126 WRITE4(sc, FPGAMGR_DCLKSTAT, 0x1);
175 WRITE4(sc, IMGCFG_CTRL_02, reg);
179 WRITE4(sc, IMGCFG_CTRL_02, reg);
184 WRITE4(sc, IMGCFG_CTRL_01, reg);
188 WRITE4(sc, IMGCFG_CTRL_00, reg);
193 WRITE4(sc, IMGCFG_CTRL_01, reg);
198 WRITE4(sc, IMGCFG_CTRL_02, reg);
208 WRITE4(s
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H A Dsocfpga_common.h34 #define WRITE4(_sc, _reg, _val) bus_write_4((_sc)->res[0], _reg, _val) macro
H A Dsocfpga_manager.c224 WRITE4(sc, FPGAMGR_CTRL, reg);
229 WRITE4(sc, FPGAMGR_CTRL, reg);
234 WRITE4(sc, FPGAMGR_CTRL, reg);
245 WRITE4(sc, FPGAMGR_CTRL, reg);
253 WRITE4(sc, GPIO_PORTA_EOI, PORTA_EOI_NS);
258 WRITE4(sc, FPGAMGR_CTRL, reg);
270 WRITE4(sc, FPGAMGR_DCLKSTAT, 0x1);
273 WRITE4(sc, FPGAMGR_DCLKCNT, npulses);
279 WRITE4(sc, FPGAMGR_DCLKSTAT, 0x1);
310 WRITE4(s
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/freebsd-current/sys/dev/dwc/
H A Ddwc1000_core.c103 WRITE4(sc, GMII_ADDRESS, mii);
130 WRITE4(sc, GMII_DATA, val);
131 WRITE4(sc, GMII_ADDRESS, mii);
192 WRITE4(sc, MAC_CONFIGURATION, reg);
201 WRITE4(sc, FLOW_CONTROL, reg);
217 WRITE4(sc, MAC_CONFIGURATION, reg);
231 WRITE4(sc, MAC_CONFIGURATION, reg);
245 WRITE4(sc, MAC_CONFIGURATION, reg);
342 WRITE4(sc, MAC_ADDRESS_LOW(0), lo);
343 WRITE4(s
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/freebsd-current/sys/dev/mmc/host/
H A Ddwmmc_samsung.c45 #define WRITE4(_sc, _reg, _val) \ macro
101 WRITE4(sc, EMMCP_MPSBEGIN0, 0);
102 WRITE4(sc, EMMCP_SEND0, 0);
103 WRITE4(sc, EMMCP_CTRL0, (MPSCTRL_SECURE_READ_BIT |
H A Ddwmmc.c90 #define WRITE4(_sc, _reg, _val) \ macro
216 WRITE4(sc, SDMMC_CTRL, reg);
426 WRITE4(sc, SDMMC_RINTSTS, reg);
441 WRITE4(sc, SDMMC_IDSTS, (SDMMC_IDINTEN_TI |
443 WRITE4(sc, SDMMC_IDSTS, SDMMC_IDINTEN_NI);
726 WRITE4(sc, SDMMC_DBADDR, sc->desc_ring_paddr);
729 WRITE4(sc, SDMMC_IDSTS, SDMMC_IDINTEN_MASK);
730 WRITE4(sc, SDMMC_IDINTEN, (SDMMC_IDINTEN_NI |
736 WRITE4(sc, SDMMC_RINTSTS, 0xffffffff);
737 WRITE4(s
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/freebsd-current/sys/dev/clk/rockchip/
H A Drk_clk_pll.c53 #define WRITE4(_clk, off, val) \ macro
89 WRITE4(clk, sc->gate_offset, val);
150 WRITE4(clk, sc->mode_reg, reg);
231 WRITE4(clk, sc->mode_reg, reg);
234 WRITE4(clk, sc->base_offset + 12, RK3066_CLK_PLL_RESET |
246 WRITE4(clk, sc->base_offset, reg);
256 WRITE4(clk, sc->base_offset + 0x4, reg);
261 WRITE4(clk, sc->base_offset + 0x8, reg);
264 WRITE4(clk, sc->base_offset + 12,
290 WRITE4(cl
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/freebsd-current/sys/dev/xilinx/
H A Daxi_quad_spi.c66 #define WRITE4(_sc, _reg, _val) \ macro
140 WRITE4(sc, SPI_SRR, SRR_RESET);
145 WRITE4(sc, SPI_CR, reg);
146 WRITE4(sc, SPI_DGIER, 0); /* Disable interrupts */
149 WRITE4(sc, SPI_CR, reg);
163 WRITE4(sc, SPI_DTR, out_buf[i]);
198 WRITE4(sc, SPI_SSR, reg);
209 WRITE4(sc, SPI_SSR, reg);
H A Dif_xae.c70 #define WRITE4(_sc, _reg, _val) \ macro
349 WRITE4(sc, XAE_TC, reg);
354 WRITE4(sc, XAE_RCW1, reg);
450 WRITE4(sc, XAE_TC, TC_TX);
453 WRITE4(sc, XAE_RCW1, RCW1_RX);
527 WRITE4(sc, XAE_FFC, reg);
533 WRITE4(sc, XAE_FFV(0), reg);
537 WRITE4(sc, XAE_FFV(1), reg);
558 WRITE4(sc, XAE_FFC, reg);
562 WRITE4(s
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/freebsd-current/sys/dev/altera/pio/
H A Dpio.c60 #define WRITE4(_sc, _reg, _val) bus_write_4((_sc)->res[0], _reg, _val) macro
125 WRITE4(sc, PIO_OUTSET, bit);
127 WRITE4(sc, PIO_OUTCLR, bit);
139 WRITE4(sc, PIO_INT_MASK, mask);
140 WRITE4(sc, PIO_DIR, dir);
/freebsd-current/sys/arm/ti/clk/
H A Dti_clk_clkctrl.c70 #define WRITE4(_clk, off, val) \ macro
114 WRITE4(clk, sc->register_offset, val);
153 WRITE4(clk, sc->register_offset, MODULEMODE_ENABLE);
155 WRITE4(clk, sc->register_offset, MODULEMODE_DISABLE);
/freebsd-current/sys/dev/clk/allwinner/
H A Daw_clk_nkmp.c62 #define WRITE4(_clk, off, val) \ macro
111 WRITE4(clk, sc->offset, val);
132 WRITE4(clk, sc->offset, val);
205 WRITE4(clk, sc->offset, val);
212 WRITE4(clk, sc->offset, val);
220 WRITE4(clk, sc->offset, val);
226 WRITE4(clk, sc->offset, val);
233 WRITE4(clk, sc->offset, val);
293 WRITE4(clk, sc->offset, val);
301 WRITE4(cl
[all...]
H A Daw_clk_m.c59 #define WRITE4(_clk, off, val) \ macro
106 WRITE4(clk, sc->offset, val);
127 WRITE4(clk, sc->offset, val);
213 WRITE4(clk, sc->offset, val);
/freebsd-current/sys/dev/clk/starfive/
H A Djh7110_clk.c47 #define WRITE4(_sc, _off, _val) \ macro
74 WRITE4(sc, offset, regvalue);
147 WRITE4(sc, sc_clk->offset, reg);
175 WRITE4(sc, sc_clk->offset, reg);
232 WRITE4(sc, sc_clk->offset, divisor);
/freebsd-current/sys/dev/beri/virtio/
H A Dvirtio.h37 #define WRITE4(_sc, _reg, _val) \ macro
/freebsd-current/sys/dev/agp/
H A Dagp_ati.c58 #define WRITE4(off,v) bus_space_write_4(sc->bst, sc->bsh, off, v) macro
228 WRITE4(ATI_GART_FEATURE_ID, 0x00060000);
233 WRITE4(ATI_GART_BASE, sc->ag_pdir);
254 WRITE4(ATI_GART_BASE, 0);
341 WRITE4(ATI_GART_CACHE_CNTRL, 1);

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