Lines Matching refs:WRITE4
64 #define WRITE4(_sc, _reg, _val) \
97 WRITE4(sc, SDMAARM_INTR, pending);
115 WRITE4(sc, SDMAARM_HSTART, (1 << i));
140 WRITE4(sc, SDMAARM_HSTART, (1 << chn));
152 WRITE4(sc, SDMAARM_STOP_STAT, (1 << chn));
219 WRITE4(sc, SDMAARM_EVTOVR, reg);
227 WRITE4(sc, SDMAARM_HOSTOVR, reg);
235 WRITE4(sc, SDMAARM_DSPOVR, reg);
263 WRITE4(sc, SDMAARM_SDMA_CHNPRI(chn), 1);
264 WRITE4(sc, SDMAARM_CHNENBL(conf->event), (1 << chn));
327 WRITE4(sc, SDMAARM_HSTART, 1);
344 WRITE4(sc, SDMAARM_INTR, ret);
392 WRITE4(sc, SDMAARM_MC0PTR, 0);
406 WRITE4(sc, SDMAARM_CHNENBL(i), 0);
410 WRITE4(sc, SDMAARM_SDMA_CHNPRI(i), 0);
421 WRITE4(sc, SDMAARM_SDMA_CHNPRI(chn), 1);
426 WRITE4(sc, SDMAARM_CHN0ADDR, 0x4050);
428 WRITE4(sc, SDMAARM_CONFIG, 0);
429 WRITE4(sc, SDMAARM_MC0PTR, sc->ccb_phys);
430 WRITE4(sc, SDMAARM_CONFIG, CONFIG_CSM);
431 WRITE4(sc, SDMAARM_SDMA_CHNPRI(chn), 1);
439 WRITE4(sc, SDMAARM_HSTART, 1);
453 WRITE4(sc, SDMAARM_INTR, ret);
460 WRITE4(sc, SDMAARM_ONCE_ENB, 0);