Searched refs:Rd (Results 1 - 22 of 22) sorted by relevance

/freebsd-current/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64PBQPRegAlloc.h30 // parity(Rd) == parity(Ra).
32 bool addIntraChainConstraint(PBQPRAGraph &G, unsigned Rd, unsigned Ra);
35 void addInterChainConstraint(PBQPRAGraph &G, unsigned Rd, unsigned Ra);
H A DAArch64PBQPRegAlloc.cpp158 bool A57ChainingConstraint::addIntraChainConstraint(PBQPRAGraph &G, unsigned Rd, argument
160 if (Rd == Ra)
165 if (Register::isPhysicalRegister(Rd) || Register::isPhysicalRegister(Ra)) {
166 LLVM_DEBUG(dbgs() << "Rd is a physical reg:"
167 << Register::isPhysicalRegister(Rd) << '\n');
173 PBQPRAGraph::NodeId node1 = G.getMetadata().getNodeIdForVReg(Rd);
186 const LiveInterval &ld = LIs.getInterval(Rd);
242 void A57ChainingConstraint::addInterChainConstraint(PBQPRAGraph &G, unsigned Rd, argument
248 if (Rd != Ra) {
250 << " to " << printReg(Rd, TR
362 Register Rd = MI.getOperand(0).getReg(); local
372 Register Rd = MI.getOperand(0).getReg(); local
[all...]
/freebsd-current/contrib/llvm-project/compiler-rt/lib/xray/
H A Dxray_loongarch64.cpp31 encodeInstruction2RIx(uint32_t Opcode, uint32_t Rd, uint32_t Rj,
33 return Opcode | (Imm << 10) | (Rj << 5) | Rd;
38 encodeInstruction1RI20(uint32_t Opcode, uint32_t Rd,
40 return Opcode | (Imm << 5) | Rd;
H A Dxray_mips64.cpp48 encodeSpecialInstruction(uint32_t Opcode, uint32_t Rs, uint32_t Rt, uint32_t Rd,
50 return (Rs << 21 | Rt << 16 | Rd << 11 | Imm << 6 | Opcode);
H A Dxray_mips.cpp47 encodeSpecialInstruction(uint32_t Opcode, uint32_t Rs, uint32_t Rt, uint32_t Rd,
49 return (Rs << 21 | Rt << 16 | Rd << 11 | Imm << 6 | Opcode);
/freebsd-current/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp954 unsigned Rd = fieldFromInstruction(Insn, 0, 5); local
959 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder);
962 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
1053 unsigned Rd = fieldFromInstruction(insn, 0, 5); local
1081 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1102 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1115 unsigned Rd = fieldFromInstruction(insn, 0, 5); local
1127 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1132 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1655 unsigned Rd local
1712 unsigned Rd = fieldFromInstruction(insn, 0, 5); local
1743 unsigned Rd = fieldFromInstruction(insn, 0, 5); local
1782 unsigned Rd = fieldFromInstruction(insn, 0, 5); local
1800 unsigned Rd = fieldFromInstruction(insn, 0, 5); local
1818 unsigned Rd = fieldFromInstruction(insn, 0, 5); local
2049 unsigned Rd = fieldFromInstruction(insn, 0, 5); local
2074 unsigned Rd = fieldFromInstruction(insn, 0, 5); local
[all...]
/freebsd-current/contrib/llvm-project/lldb/source/Plugins/Instruction/RISCV/
H A DRISCVInstructions.h22 struct Rd { struct in namespace:lldb_private
45 Rd rd; \
59 Rd rd; \
67 Rd rd; \
74 Rd rd; \
81 Rd rd; \
87 Rd rd; \
H A DRISCVCInstructions.h25 operator Rd() { return Rd{rd + (shift ? 8 : 0)}; }
120 return JAL{Rd{0}, uint32_t(offset)};
121 return JAL{Rd{0}, uint32_t(int32_t(int16_t(offset | 0xf000)))};
128 return JALR{Rd{0}, rs1, 0};
135 return JALR{Rd{1}, rs1, 0};
183 return ADDI{Rd{gpr_sp_riscv}, Rs{gpr_sp_riscv}, uint32_t(nzimm)};
184 return ADDI{Rd{gpr_sp_riscv}, Rs{gpr_sp_riscv},
H A DEmulateInstructionRISCV.cpp111 bool Rd::Write(EmulateInstructionRISCV &emulator, uint64_t value) {
122 bool Rd::WriteAPFloat(EmulateInstructionRISCV &emulator, APFloat value) {
385 return T{Rd{DecodeRD(inst)}, DecodeUImm(inst)};
389 return T{Rd{DecodeRD(inst)}, DecodeJImm(inst)};
393 return T{Rd{DecodeRD(inst)}, Rs{DecodeRS1(inst)}, DecodeIImm(inst)};
406 return T{Rd{DecodeRD(inst)}, Rs{DecodeRS1(inst)}, Rs{DecodeRS2(inst)}};
410 return T{Rd{DecodeRD(inst)}, Rs{DecodeRS1(inst)}, DecodeRS2(inst)};
414 return T{Rd{DecodeRD(inst)}, Rs{DecodeRS1(inst)}};
418 return T{Rd{DecodeRD(inst)}, Rs{DecodeRS1(inst)}, Rs{DecodeRS2(inst)},
/freebsd-current/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM/
H A DEmulateInstructionARM.cpp1168 uint32_t Rd; // the destination register
1172 Rd = 7;
1176 Rd = Bits32(opcode, 15, 12);
1186 if (Rd == GetFramePointerRegisterNumber())
1194 if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + Rd,
1229 uint32_t Rd; // the destination register
1232 Rd = 7;
1235 Rd = 12;
1242 if (Rd == GetFramePointerRegisterNumber())
1250 if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + Rd, s
1289 uint32_t Rd; // the destination register local
1377 uint32_t Rd; // the destination register local
1619 uint32_t Rd; // the destination register local
1681 uint32_t Rd; // the destination register local
3152 uint32_t Rd, Rn; local
3218 uint32_t Rd, Rn, Rm; local
3753 uint32_t Rd; // the destination register local
3838 uint32_t Rd; // the destination register local
5801 uint32_t Rd, Rn; local
5871 uint32_t Rd, Rn, Rm; local
5950 uint32_t Rd; local
6018 uint32_t Rd, Rn; local
6094 uint32_t Rd, Rn, Rm; local
6183 uint32_t Rd, Rn; local
6259 uint32_t Rd, Rn, Rm; local
8822 uint32_t Rd, Rn; local
8901 uint32_t Rd, Rn, Rm; local
8991 uint32_t Rd, Rn; local
9068 uint32_t Rd, Rn, Rm; local
9155 uint32_t Rd; // the destination register local
9228 uint32_t Rd; // the destination register local
9306 uint32_t Rd; // the destination register local
9366 uint32_t Rd; // the destination register local
9435 uint32_t Rd; // the destination register local
9504 uint32_t Rd; // the destination register local
9584 uint32_t Rd; // the destination register local
9678 uint32_t Rd; // the destination register local
14215 WriteCoreRegOptionalFlags( Context &context, const uint32_t result, const uint32_t Rd, bool setflags, const uint32_t carry, const uint32_t overflow) argument
[all...]
H A DEmulateInstructionARM.h197 const uint32_t Rd, bool setflags,
202 const uint32_t Rd) {
204 return WriteCoreRegOptionalFlags(context, result, Rd, false);
325 // A8.6.97 MOV (register) -- Rd == r7|ip and Rm == sp
353 // A8.6.212 SUB (immediate, ARM) -- Rd == r7 and Rm == ip
356 // A8.6.215 SUB (SP minus immediate) -- Rd == ip
201 WriteCoreReg(Context &context, const uint32_t result, const uint32_t Rd) argument
/freebsd-current/sys/arm64/arm64/
H A Dundefined.c206 int attempts, error, Rn, Rd, Rm; local
224 Rd = (insn & 0xf000) >> 12;
260 regs[Rd] = val;
/freebsd-current/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp2429 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
2437 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2685 unsigned Rd = fieldFromInstruction(Insn, 8, 4); local
2694 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2696 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2710 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
2718 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2721 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2738 unsigned Rd = fieldFromInstruction(Insn, 16, 4); local
2747 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Addres
2962 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
3294 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
3565 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
3613 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
3662 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
3698 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
3751 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
3852 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
3900 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
5117 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
5250 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
5317 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
5382 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
5449 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
5512 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
5582 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
5645 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
5726 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local
5950 const unsigned Rd = fieldFromInstruction(Insn, 8, 4); local
7002 const unsigned Rd = fieldFromInstruction(Insn, 8, 4); local
[all...]
/freebsd-current/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonConstExtenders.cpp325 Register Rd; member in struct:__anon2330::HexagonConstExtenders::ExtDesc
396 OffsetRange getOffsetRange(Register Rd) const;
499 if (ED.Rd.Reg != 0)
500 OS << printReg(ED.Rd.Reg, &HRI, ED.Rd.Sub);
1127 // Get the allowable deviation from the current value of Rd by checking
1128 // all uses of Rd.
1129 OffsetRange HCE::getOffsetRange(Register Rd) const {
1131 for (const MachineOperand &Op : MRI->use_operands(Rd.Reg)) {
1135 if (Rd !
[all...]
H A DHexagonFrameLowering.cpp142 // Rd = PS_alloca Rs, A
144 // Rd - address of the allocated space
2495 // Rd = alloca Rs, #A
2497 // If Rs and Rd are different registers, use this sequence:
2498 // Rd = sub(r29, Rs)
2500 // Rd = and(Rd, #-A) ; if necessary
2502 // Rd = add(Rd, #CF) ; CF size aligned to at most A
2504 // Rd
2511 Register Rd = RdOp.getReg(), Rs = RsOp.getReg(); local
[all...]
H A DHexagonInstrInfo.cpp1344 Register Rd = Op0.getReg(); local
1352 if (Rd != Rs)
1353 BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpt), Rd)
1354 .addReg(Pu, (Rd == Rt) ? K1 : 0)
1356 if (Rd != Rt)
1357 BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpf), Rd)
3434 // Rd = Rs
3441 // Rd = #u6
3471 // Rd=#U6 ; jump #r9:2
3472 // Rd
[all...]
/freebsd-current/contrib/llvm-project/llvm/lib/Target/RISCV/Disassembler/
H A DRISCVDisassembler.cpp382 uint32_t Rd = fieldFromInstruction(Insn, 7, 5); local
383 DecodeStatus Result = DecodeGPRNoX0RegisterClass(Inst, Rd, Address, Decoder);
429 uint32_t Rd = fieldFromInstruction(Insn, 7, 5); local
431 DecodeGPRRegisterClass(Inst, Rd, Address, Decoder);
439 uint32_t Rd = fieldFromInstruction(Insn, 7, 5); local
441 DecodeGPRRegisterClass(Inst, Rd, Address, Decoder);
/freebsd-current/contrib/llvm-project/llvm/lib/Target/MSP430/Disassembler/
H A DMSP430Disassembler.cpp194 unsigned Rd = fieldFromInstruction(Insn, 0, 4); local
196 switch (Rd) {
/freebsd-current/contrib/llvm-project/llvm/lib/Target/LoongArch/AsmParser/
H A DLoongArchAsmParser.cpp1226 unsigned Rd = Inst.getOperand(0).getReg();
1229 if ((Rd == Rk || Rd == Rj) && Rd != LoongArch::R0)
1238 unsigned Rd = Inst.getOperand(0).getReg();
1240 if (Rd == Rj)
/freebsd-current/contrib/llvm-project/llvm/lib/Target/Hexagon/AsmParser/
H A DHexagonAsmParser.cpp1689 MCOperand &Rd = Inst.getOperand(0); local
1706 TmpInst.addOperand(Rd);
1720 if (Value == 0) { // convert to $Rd = $Rs
1722 MCOperand &Rd = Inst.getOperand(0); local
1724 TmpInst.addOperand(Rd);
1732 MCOperand &Rd = Inst.getOperand(0); local
1734 TmpInst.addOperand(Rd);
1920 MCOperand &Rd = Inst.getOperand(0); local
1923 TmpInst.addOperand(Rd);
/freebsd-current/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM64/
H A DEmulateInstructionARM64.cpp579 // integer d = UInt(Rd);
620 const uint32_t Rd = Bits32(opcode, 4, 0); local
624 const uint32_t d = UInt(Rd);
/freebsd-current/crypto/openssl/crypto/ec/asm/
H A Decp_nistz256-x86_64.pl2558 my ($ONE,$INDEX,$Ra,$Rb,$Rc,$Rd,$Re,$Rf)=map("%xmm$_",(0..7));
2624 pxor $Rd, $Rd
2654 por $T0d, $Rd
2665 movdqu $Rd, 16*3($val)
2744 pxor $Rd, $Rd
2768 por $T0d, $Rd
2776 movdqu $Rd, 16*3($val)

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