1//===- AArch64Disassembler.cpp - Disassembler for AArch64 -----------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9//
10//===----------------------------------------------------------------------===//
11
12#include "AArch64Disassembler.h"
13#include "AArch64ExternalSymbolizer.h"
14#include "MCTargetDesc/AArch64AddressingModes.h"
15#include "MCTargetDesc/AArch64MCTargetDesc.h"
16#include "TargetInfo/AArch64TargetInfo.h"
17#include "Utils/AArch64BaseInfo.h"
18#include "llvm-c/Disassembler.h"
19#include "llvm/MC/MCDecoderOps.h"
20#include "llvm/MC/MCDisassembler/MCRelocationInfo.h"
21#include "llvm/MC/MCInst.h"
22#include "llvm/MC/MCInstrDesc.h"
23#include "llvm/MC/MCRegisterInfo.h"
24#include "llvm/MC/MCSubtargetInfo.h"
25#include "llvm/MC/TargetRegistry.h"
26#include "llvm/Support/Compiler.h"
27#include "llvm/Support/Debug.h"
28#include "llvm/Support/ErrorHandling.h"
29#include <algorithm>
30#include <memory>
31
32using namespace llvm;
33
34#define DEBUG_TYPE "aarch64-disassembler"
35
36// Pull DecodeStatus and its enum values into the global namespace.
37using DecodeStatus = MCDisassembler::DecodeStatus;
38
39// Forward declare these because the autogenerated code will reference them.
40// Definitions are further down.
41static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo,
42                                              uint64_t Address,
43                                              const MCDisassembler *Decoder);
44static DecodeStatus DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo,
45                                                 uint64_t Address,
46                                                 const MCDisassembler *Decoder);
47static DecodeStatus
48DecodeFPR128_0to7RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
49                               const MCDisassembler *Decoder);
50static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo,
51                                             uint64_t Address,
52                                             const MCDisassembler *Decoder);
53static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo,
54                                             uint64_t Address,
55                                             const MCDisassembler *Decoder);
56static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo,
57                                             uint64_t Address,
58                                             const MCDisassembler *Decoder);
59static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo,
60                                            uint64_t Address,
61                                            const MCDisassembler *Decoder);
62static DecodeStatus
63DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
64                               const MCDisassembler *Decoder);
65static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
66                                             uint64_t Address,
67                                             const MCDisassembler *Decoder);
68static DecodeStatus
69DecodeGPR64x8ClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
70                                const MCDisassembler *Decoder);
71static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo,
72                                               uint64_t Address,
73                                               const MCDisassembler *Decoder);
74static DecodeStatus
75DecodeMatrixIndexGPR32_8_11RegisterClass(MCInst &Inst, unsigned RegNo,
76                                         uint64_t Address, const void *Decoder);
77static DecodeStatus
78DecodeMatrixIndexGPR32_12_15RegisterClass(MCInst &Inst, unsigned RegNo,
79                                          uint64_t Address,
80                                          const MCDisassembler *Decoder);
81static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
82                                             uint64_t Address,
83                                             const MCDisassembler *Decoder);
84static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo,
85                                               uint64_t Address,
86                                               const MCDisassembler *Decoder);
87static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo,
88                                          uint64_t Address,
89                                          const MCDisassembler *Decoder);
90static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo,
91                                           uint64_t Address,
92                                           const MCDisassembler *Decoder);
93static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo,
94                                            uint64_t Address,
95                                            const MCDisassembler *Decoder);
96static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo,
97                                          uint64_t Address,
98                                          const MCDisassembler *Decoder);
99static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo,
100                                           uint64_t Address,
101                                           const MCDisassembler *Decoder);
102static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo,
103                                            uint64_t Address,
104                                            const MCDisassembler *Decoder);
105static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo,
106                                           uint64_t Address,
107                                           const MCDisassembler *Decoder);
108static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo,
109                                              uint64_t Address,
110                                              const MCDisassembler *Decoder);
111static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
112                                              uint64_t Address,
113                                              const MCDisassembler *Decoder);
114static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo,
115                                            uint64_t Address,
116                                            const MCDisassembler *Decoder);
117static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo,
118                                            uint64_t Address,
119                                            const MCDisassembler *Decoder);
120static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo,
121                                            uint64_t Address,
122                                            const MCDisassembler *Decoder);
123static DecodeStatus DecodeZPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo,
124                                                uint64_t Address,
125                                                const void *Decoder);
126static DecodeStatus DecodeZPR4Mul4RegisterClass(MCInst &Inst, unsigned RegNo,
127                                                uint64_t Address,
128                                                const void *Decoder);
129static DecodeStatus DecodeZPR2StridedRegisterClass(MCInst &Inst, unsigned RegNo,
130                                                   uint64_t Address,
131                                                   const void *Decoder);
132static DecodeStatus DecodeZPR4StridedRegisterClass(MCInst &Inst, unsigned RegNo,
133                                                   uint64_t Address,
134                                                   const void *Decoder);
135template <unsigned NumBitsForTile>
136static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo,
137                                     uint64_t Address,
138                                     const MCDisassembler *Decoder);
139static DecodeStatus
140DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask,
141                                  uint64_t Address,
142                                  const MCDisassembler *Decoder);
143static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo,
144                                           uint64_t Address,
145                                           const MCDisassembler *Decoder);
146static DecodeStatus DecodePNRRegisterClass(MCInst &Inst, unsigned RegNo,
147                                           uint64_t Address,
148                                           const MCDisassembler *Decoder);
149static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
150                                              uint64_t Address,
151                                              const MCDisassembler *Decoder);
152static DecodeStatus
153DecodePNR_p8to15RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
154                              const MCDisassembler *Decoder);
155static DecodeStatus DecodePPR2RegisterClass(MCInst &Inst, unsigned RegNo,
156                                            uint64_t Address,
157                                            const void *Decoder);
158static DecodeStatus DecodePPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo,
159                                                uint64_t Address,
160                                                const void *Decoder);
161
162static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
163                                               uint64_t Address,
164                                               const MCDisassembler *Decoder);
165static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm,
166                                               uint64_t Address,
167                                               const MCDisassembler *Decoder);
168static DecodeStatus DecodePCRelLabel16(MCInst &Inst, unsigned Imm,
169                                       uint64_t Address,
170                                       const MCDisassembler *Decoder);
171static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm,
172                                       uint64_t Address,
173                                       const MCDisassembler *Decoder);
174static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm,
175                                    uint64_t Address,
176                                    const MCDisassembler *Decoder);
177static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm,
178                                            uint64_t Address,
179                                            const MCDisassembler *Decoder);
180static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm,
181                                            uint64_t Address,
182                                            const MCDisassembler *Decoder);
183static DecodeStatus
184DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Address,
185                               const MCDisassembler *Decoder);
186static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn,
187                                             uint64_t Address,
188                                             const MCDisassembler *Decoder);
189static DecodeStatus
190DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address,
191                              const MCDisassembler *Decoder);
192static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn,
193                                                uint64_t Address,
194                                                const MCDisassembler *Decoder);
195static DecodeStatus
196DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address,
197                               const MCDisassembler *Decoder);
198static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn,
199                                              uint64_t Address,
200                                              const MCDisassembler *Decoder);
201static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn,
202                                              uint64_t Address,
203                                              const MCDisassembler *Decoder);
204static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn,
205                                                uint64_t Address,
206                                                const MCDisassembler *Decoder);
207static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn,
208                                                uint64_t Address,
209                                                const MCDisassembler *Decoder);
210static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn,
211                                            uint64_t Address,
212                                            const MCDisassembler *Decoder);
213static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn,
214                                                uint64_t Address,
215                                                const MCDisassembler *Decoder);
216static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn,
217                                         uint64_t Address,
218                                         const MCDisassembler *Decoder);
219static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn,
220                                         uint64_t Address,
221                                         const MCDisassembler *Decoder);
222static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn,
223                                              uint64_t Address,
224                                              const MCDisassembler *Decoder);
225static DecodeStatus
226DecodeSystemPStateImm0_15Instruction(MCInst &Inst, uint32_t insn,
227                                     uint64_t Address,
228                                     const MCDisassembler *Decoder);
229static DecodeStatus
230DecodeSystemPStateImm0_1Instruction(MCInst &Inst, uint32_t insn,
231                                    uint64_t Address,
232                                    const MCDisassembler *Decoder);
233static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn,
234                                        uint64_t Address,
235                                        const MCDisassembler *Decoder);
236
237static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn,
238                                              uint64_t Address,
239                                              const MCDisassembler *Decoder);
240static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm,
241                                         uint64_t Addr,
242                                         const MCDisassembler *Decoder);
243static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm,
244                                               uint64_t Addr,
245                                               const MCDisassembler *Decoder);
246static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm,
247                                         uint64_t Addr,
248                                         const MCDisassembler *Decoder);
249static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm,
250                                               uint64_t Addr,
251                                               const MCDisassembler *Decoder);
252static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm,
253                                         uint64_t Addr,
254                                         const MCDisassembler *Decoder);
255static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm,
256                                               uint64_t Addr,
257                                               const MCDisassembler *Decoder);
258static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm,
259                                        uint64_t Addr,
260                                        const MCDisassembler *Decoder);
261static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm,
262                                         uint64_t Addr,
263                                         const MCDisassembler *Decoder);
264static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm,
265                                         uint64_t Addr,
266                                         const MCDisassembler *Decoder);
267static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm,
268                                         uint64_t Addr,
269                                         const MCDisassembler *Decoder);
270static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm,
271                                        uint64_t Addr,
272                                        const MCDisassembler *Decoder);
273static DecodeStatus
274DecodeWSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
275                                  const MCDisassembler *Decoder);
276static DecodeStatus
277DecodeXSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
278                                  const MCDisassembler *Decoder);
279static DecodeStatus DecodeSyspXzrInstruction(MCInst &Inst, uint32_t insn,
280                                             uint64_t Addr,
281                                             const MCDisassembler *Decoder);
282static DecodeStatus
283DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address,
284                               const MCDisassembler *Decoder);
285template <int Bits>
286static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address,
287                               const MCDisassembler *Decoder);
288template <int ElementWidth>
289static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, uint64_t Addr,
290                                     const MCDisassembler *Decoder);
291static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm,
292                                       uint64_t Addr,
293                                       const MCDisassembler *Decoder);
294static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address,
295                                 const MCDisassembler *Decoder);
296static DecodeStatus DecodeCPYMemOpInstruction(MCInst &Inst, uint32_t insn,
297                                              uint64_t Addr,
298                                              const MCDisassembler *Decoder);
299static DecodeStatus DecodeSETMemOpInstruction(MCInst &Inst, uint32_t insn,
300                                              uint64_t Addr,
301                                              const MCDisassembler *Decoder);
302static DecodeStatus DecodePRFMRegInstruction(MCInst &Inst, uint32_t insn,
303                                             uint64_t Address,
304                                             const MCDisassembler *Decoder);
305
306#include "AArch64GenDisassemblerTables.inc"
307#include "AArch64GenInstrInfo.inc"
308
309#define Success MCDisassembler::Success
310#define Fail MCDisassembler::Fail
311#define SoftFail MCDisassembler::SoftFail
312
313static MCDisassembler *createAArch64Disassembler(const Target &T,
314                                               const MCSubtargetInfo &STI,
315                                               MCContext &Ctx) {
316
317  return new AArch64Disassembler(STI, Ctx, T.createMCInstrInfo());
318}
319
320DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size,
321                                                 ArrayRef<uint8_t> Bytes,
322                                                 uint64_t Address,
323                                                 raw_ostream &CS) const {
324  CommentStream = &CS;
325
326  Size = 0;
327  // We want to read exactly 4 bytes of data.
328  if (Bytes.size() < 4)
329    return Fail;
330  Size = 4;
331
332  // Encoded as a small-endian 32-bit word in the stream.
333  uint32_t Insn =
334      (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
335
336  const uint8_t *Tables[] = {DecoderTable32, DecoderTableFallback32};
337
338  for (const auto *Table : Tables) {
339    DecodeStatus Result =
340        decodeInstruction(Table, MI, Insn, Address, this, STI);
341
342    const MCInstrDesc &Desc = MCII->get(MI.getOpcode());
343
344    // For Scalable Matrix Extension (SME) instructions that have an implicit
345    // operand for the accumulator (ZA) or implicit immediate zero which isn't
346    // encoded, manually insert operand.
347    for (unsigned i = 0; i < Desc.getNumOperands(); i++) {
348      if (Desc.operands()[i].OperandType == MCOI::OPERAND_REGISTER) {
349        switch (Desc.operands()[i].RegClass) {
350        default:
351          break;
352        case AArch64::MPRRegClassID:
353          MI.insert(MI.begin() + i, MCOperand::createReg(AArch64::ZA));
354          break;
355        case AArch64::MPR8RegClassID:
356          MI.insert(MI.begin() + i, MCOperand::createReg(AArch64::ZAB0));
357          break;
358        case AArch64::ZTRRegClassID:
359          MI.insert(MI.begin() + i, MCOperand::createReg(AArch64::ZT0));
360          break;
361        }
362      } else if (Desc.operands()[i].OperandType ==
363                 AArch64::OPERAND_IMPLICIT_IMM_0) {
364        MI.insert(MI.begin() + i, MCOperand::createImm(0));
365      }
366    }
367
368    if (MI.getOpcode() == AArch64::LDR_ZA ||
369        MI.getOpcode() == AArch64::STR_ZA) {
370      // Spill and fill instructions have a single immediate used for both
371      // the vector select offset and optional memory offset. Replicate
372      // the decoded immediate.
373      const MCOperand &Imm4Op = MI.getOperand(2);
374      assert(Imm4Op.isImm() && "Unexpected operand type!");
375      MI.addOperand(Imm4Op);
376    }
377
378    if (Result != MCDisassembler::Fail)
379      return Result;
380  }
381
382  return MCDisassembler::Fail;
383}
384
385uint64_t AArch64Disassembler::suggestBytesToSkip(ArrayRef<uint8_t> Bytes,
386                                                 uint64_t Address) const {
387  // AArch64 instructions are always 4 bytes wide, so there's no point
388  // in skipping any smaller number of bytes if an instruction can't
389  // be decoded.
390  return 4;
391}
392
393static MCSymbolizer *
394createAArch64ExternalSymbolizer(const Triple &TT, LLVMOpInfoCallback GetOpInfo,
395                                LLVMSymbolLookupCallback SymbolLookUp,
396                                void *DisInfo, MCContext *Ctx,
397                                std::unique_ptr<MCRelocationInfo> &&RelInfo) {
398  return new AArch64ExternalSymbolizer(*Ctx, std::move(RelInfo), GetOpInfo,
399                                       SymbolLookUp, DisInfo);
400}
401
402extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Disassembler() {
403  TargetRegistry::RegisterMCDisassembler(getTheAArch64leTarget(),
404                                         createAArch64Disassembler);
405  TargetRegistry::RegisterMCDisassembler(getTheAArch64beTarget(),
406                                         createAArch64Disassembler);
407  TargetRegistry::RegisterMCSymbolizer(getTheAArch64leTarget(),
408                                       createAArch64ExternalSymbolizer);
409  TargetRegistry::RegisterMCSymbolizer(getTheAArch64beTarget(),
410                                       createAArch64ExternalSymbolizer);
411  TargetRegistry::RegisterMCDisassembler(getTheAArch64_32Target(),
412                                         createAArch64Disassembler);
413  TargetRegistry::RegisterMCSymbolizer(getTheAArch64_32Target(),
414                                       createAArch64ExternalSymbolizer);
415
416  TargetRegistry::RegisterMCDisassembler(getTheARM64Target(),
417                                         createAArch64Disassembler);
418  TargetRegistry::RegisterMCSymbolizer(getTheARM64Target(),
419                                       createAArch64ExternalSymbolizer);
420  TargetRegistry::RegisterMCDisassembler(getTheARM64_32Target(),
421                                         createAArch64Disassembler);
422  TargetRegistry::RegisterMCSymbolizer(getTheARM64_32Target(),
423                                       createAArch64ExternalSymbolizer);
424}
425
426static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, unsigned RegNo,
427                                              uint64_t Addr,
428                                              const MCDisassembler *Decoder) {
429  if (RegNo > 31)
430    return Fail;
431
432  unsigned Register =
433      AArch64MCRegisterClasses[AArch64::FPR128RegClassID].getRegister(RegNo);
434  Inst.addOperand(MCOperand::createReg(Register));
435  return Success;
436}
437
438static DecodeStatus
439DecodeFPR128_loRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
440                             const MCDisassembler *Decoder) {
441  if (RegNo > 15)
442    return Fail;
443  return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder);
444}
445
446static DecodeStatus
447DecodeFPR128_0to7RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
448                               const MCDisassembler *Decoder) {
449  if (RegNo > 7)
450    return Fail;
451  return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder);
452}
453
454static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, unsigned RegNo,
455                                             uint64_t Addr,
456                                             const MCDisassembler *Decoder) {
457  if (RegNo > 31)
458    return Fail;
459
460  unsigned Register =
461      AArch64MCRegisterClasses[AArch64::FPR64RegClassID].getRegister(RegNo);
462  Inst.addOperand(MCOperand::createReg(Register));
463  return Success;
464}
465
466static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, unsigned RegNo,
467                                             uint64_t Addr,
468                                             const MCDisassembler *Decoder) {
469  if (RegNo > 31)
470    return Fail;
471
472  unsigned Register =
473      AArch64MCRegisterClasses[AArch64::FPR32RegClassID].getRegister(RegNo);
474  Inst.addOperand(MCOperand::createReg(Register));
475  return Success;
476}
477
478static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, unsigned RegNo,
479                                             uint64_t Addr,
480                                             const MCDisassembler *Decoder) {
481  if (RegNo > 31)
482    return Fail;
483
484  unsigned Register =
485      AArch64MCRegisterClasses[AArch64::FPR16RegClassID].getRegister(RegNo);
486  Inst.addOperand(MCOperand::createReg(Register));
487  return Success;
488}
489
490static DecodeStatus DecodeFPR8RegisterClass(MCInst &Inst, unsigned RegNo,
491                                            uint64_t Addr,
492                                            const MCDisassembler *Decoder) {
493  if (RegNo > 31)
494    return Fail;
495
496  unsigned Register =
497      AArch64MCRegisterClasses[AArch64::FPR8RegClassID].getRegister(RegNo);
498  Inst.addOperand(MCOperand::createReg(Register));
499  return Success;
500}
501
502static DecodeStatus
503DecodeGPR64commonRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
504                               const MCDisassembler *Decoder) {
505  if (RegNo > 30)
506    return Fail;
507
508  unsigned Register =
509      AArch64MCRegisterClasses[AArch64::GPR64commonRegClassID].getRegister(
510          RegNo);
511  Inst.addOperand(MCOperand::createReg(Register));
512  return Success;
513}
514
515static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
516                                             uint64_t Addr,
517                                             const MCDisassembler *Decoder) {
518  if (RegNo > 31)
519    return Fail;
520
521  unsigned Register =
522      AArch64MCRegisterClasses[AArch64::GPR64RegClassID].getRegister(RegNo);
523  Inst.addOperand(MCOperand::createReg(Register));
524  return Success;
525}
526
527static DecodeStatus
528DecodeGPR64x8ClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
529                                const MCDisassembler *Decoder) {
530  if (RegNo > 22)
531    return Fail;
532  if (RegNo & 1)
533    return Fail;
534
535  unsigned Register =
536      AArch64MCRegisterClasses[AArch64::GPR64x8ClassRegClassID].getRegister(
537          RegNo >> 1);
538  Inst.addOperand(MCOperand::createReg(Register));
539  return Success;
540}
541
542static DecodeStatus DecodeGPR64spRegisterClass(MCInst &Inst, unsigned RegNo,
543                                               uint64_t Addr,
544                                               const MCDisassembler *Decoder) {
545  if (RegNo > 31)
546    return Fail;
547  unsigned Register =
548      AArch64MCRegisterClasses[AArch64::GPR64spRegClassID].getRegister(RegNo);
549  Inst.addOperand(MCOperand::createReg(Register));
550  return Success;
551}
552
553static DecodeStatus
554DecodeMatrixIndexGPR32_8_11RegisterClass(MCInst &Inst, unsigned RegNo,
555                                         uint64_t Addr, const void *Decoder) {
556  if (RegNo > 3)
557    return Fail;
558
559  unsigned Register =
560      AArch64MCRegisterClasses[AArch64::MatrixIndexGPR32_8_11RegClassID]
561          .getRegister(RegNo);
562  Inst.addOperand(MCOperand::createReg(Register));
563  return Success;
564}
565
566static DecodeStatus
567DecodeMatrixIndexGPR32_12_15RegisterClass(MCInst &Inst, unsigned RegNo,
568                                          uint64_t Addr,
569                                          const MCDisassembler *Decoder) {
570  if (RegNo > 3)
571    return Fail;
572
573  unsigned Register =
574      AArch64MCRegisterClasses[AArch64::MatrixIndexGPR32_12_15RegClassID]
575          .getRegister(RegNo);
576  Inst.addOperand(MCOperand::createReg(Register));
577  return Success;
578}
579
580static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
581                                             uint64_t Addr,
582                                             const MCDisassembler *Decoder) {
583  if (RegNo > 31)
584    return Fail;
585
586  unsigned Register =
587      AArch64MCRegisterClasses[AArch64::GPR32RegClassID].getRegister(RegNo);
588  Inst.addOperand(MCOperand::createReg(Register));
589  return Success;
590}
591
592static DecodeStatus DecodeGPR32spRegisterClass(MCInst &Inst, unsigned RegNo,
593                                               uint64_t Addr,
594                                               const MCDisassembler *Decoder) {
595  if (RegNo > 31)
596    return Fail;
597
598  unsigned Register =
599      AArch64MCRegisterClasses[AArch64::GPR32spRegClassID].getRegister(RegNo);
600  Inst.addOperand(MCOperand::createReg(Register));
601  return Success;
602}
603
604static DecodeStatus DecodeZPRRegisterClass(MCInst &Inst, unsigned RegNo,
605                                           uint64_t Address,
606                                           const MCDisassembler *Decoder) {
607  if (RegNo > 31)
608    return Fail;
609
610  unsigned Register =
611      AArch64MCRegisterClasses[AArch64::ZPRRegClassID].getRegister(RegNo);
612  Inst.addOperand(MCOperand::createReg(Register));
613  return Success;
614}
615
616static DecodeStatus DecodeZPR_4bRegisterClass(MCInst &Inst, unsigned RegNo,
617                                              uint64_t Address,
618                                              const MCDisassembler *Decoder) {
619  if (RegNo > 15)
620    return Fail;
621  return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder);
622}
623
624static DecodeStatus DecodeZPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
625                                              uint64_t Address,
626                                              const MCDisassembler *Decoder) {
627  if (RegNo > 7)
628    return Fail;
629  return DecodeZPRRegisterClass(Inst, RegNo, Address, Decoder);
630}
631
632static DecodeStatus DecodeZPR2RegisterClass(MCInst &Inst, unsigned RegNo,
633                                            uint64_t Address,
634                                            const MCDisassembler *Decoder) {
635  if (RegNo > 31)
636    return Fail;
637  unsigned Register =
638      AArch64MCRegisterClasses[AArch64::ZPR2RegClassID].getRegister(RegNo);
639  Inst.addOperand(MCOperand::createReg(Register));
640  return Success;
641}
642
643static DecodeStatus DecodeZPR3RegisterClass(MCInst &Inst, unsigned RegNo,
644                                            uint64_t Address,
645                                            const MCDisassembler *Decoder) {
646  if (RegNo > 31)
647    return Fail;
648  unsigned Register =
649      AArch64MCRegisterClasses[AArch64::ZPR3RegClassID].getRegister(RegNo);
650  Inst.addOperand(MCOperand::createReg(Register));
651  return Success;
652}
653
654static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo,
655                                            uint64_t Address,
656                                            const MCDisassembler *Decoder) {
657  if (RegNo > 31)
658    return Fail;
659  unsigned Register =
660      AArch64MCRegisterClasses[AArch64::ZPR4RegClassID].getRegister(RegNo);
661  Inst.addOperand(MCOperand::createReg(Register));
662  return Success;
663}
664
665static DecodeStatus DecodeZPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo,
666                                                uint64_t Address,
667                                                const void *Decoder) {
668  if (RegNo * 2 > 30)
669    return Fail;
670  unsigned Register =
671      AArch64MCRegisterClasses[AArch64::ZPR2RegClassID].getRegister(RegNo * 2);
672  Inst.addOperand(MCOperand::createReg(Register));
673  return Success;
674}
675
676static DecodeStatus DecodeZPR4Mul4RegisterClass(MCInst &Inst, unsigned RegNo,
677                                                uint64_t Address,
678                                                const void *Decoder) {
679  if (RegNo * 4 > 28)
680    return Fail;
681  unsigned Register =
682      AArch64MCRegisterClasses[AArch64::ZPR4RegClassID].getRegister(RegNo * 4);
683  Inst.addOperand(MCOperand::createReg(Register));
684  return Success;
685}
686
687static DecodeStatus DecodeZPR2StridedRegisterClass(MCInst &Inst, unsigned RegNo,
688                                                   uint64_t Address,
689                                                   const void *Decoder) {
690  if (RegNo > 15)
691    return Fail;
692  unsigned Register =
693      AArch64MCRegisterClasses[AArch64::ZPR2StridedRegClassID].getRegister(
694          RegNo);
695  Inst.addOperand(MCOperand::createReg(Register));
696  return Success;
697}
698
699static DecodeStatus DecodeZPR4StridedRegisterClass(MCInst &Inst, unsigned RegNo,
700                                                   uint64_t Address,
701                                                   const void *Decoder) {
702  if (RegNo > 7)
703    return Fail;
704  unsigned Register =
705      AArch64MCRegisterClasses[AArch64::ZPR4StridedRegClassID].getRegister(
706          RegNo);
707  Inst.addOperand(MCOperand::createReg(Register));
708  return Success;
709}
710
711static DecodeStatus
712DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask,
713                                  uint64_t Address,
714                                  const MCDisassembler *Decoder) {
715  if (RegMask > 0xFF)
716    return Fail;
717  Inst.addOperand(MCOperand::createImm(RegMask));
718  return Success;
719}
720
721static const MCPhysReg MatrixZATileDecoderTable[5][16] = {
722    {AArch64::ZAB0},
723    {AArch64::ZAH0, AArch64::ZAH1},
724    {AArch64::ZAS0, AArch64::ZAS1, AArch64::ZAS2, AArch64::ZAS3},
725    {AArch64::ZAD0, AArch64::ZAD1, AArch64::ZAD2, AArch64::ZAD3, AArch64::ZAD4,
726     AArch64::ZAD5, AArch64::ZAD6, AArch64::ZAD7},
727    {AArch64::ZAQ0, AArch64::ZAQ1, AArch64::ZAQ2, AArch64::ZAQ3, AArch64::ZAQ4,
728     AArch64::ZAQ5, AArch64::ZAQ6, AArch64::ZAQ7, AArch64::ZAQ8, AArch64::ZAQ9,
729     AArch64::ZAQ10, AArch64::ZAQ11, AArch64::ZAQ12, AArch64::ZAQ13,
730     AArch64::ZAQ14, AArch64::ZAQ15}};
731
732template <unsigned NumBitsForTile>
733static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo,
734                                     uint64_t Address,
735                                     const MCDisassembler *Decoder) {
736  unsigned LastReg = (1 << NumBitsForTile) - 1;
737  if (RegNo > LastReg)
738    return Fail;
739  Inst.addOperand(
740      MCOperand::createReg(MatrixZATileDecoderTable[NumBitsForTile][RegNo]));
741  return Success;
742}
743
744static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo,
745                                           uint64_t Addr,
746                                           const MCDisassembler *Decoder) {
747  if (RegNo > 15)
748    return Fail;
749
750  unsigned Register =
751      AArch64MCRegisterClasses[AArch64::PPRRegClassID].getRegister(RegNo);
752  Inst.addOperand(MCOperand::createReg(Register));
753  return Success;
754}
755
756static DecodeStatus DecodePNRRegisterClass(MCInst &Inst, unsigned RegNo,
757                                           uint64_t Addr,
758                                           const MCDisassembler *Decoder) {
759  if (RegNo > 15)
760    return Fail;
761
762  unsigned Register =
763      AArch64MCRegisterClasses[AArch64::PNRRegClassID].getRegister(RegNo);
764  Inst.addOperand(MCOperand::createReg(Register));
765  return Success;
766}
767
768static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
769                                              uint64_t Addr,
770                                              const MCDisassembler *Decoder) {
771  if (RegNo > 7)
772    return Fail;
773
774  // Just reuse the PPR decode table
775  return DecodePPRRegisterClass(Inst, RegNo, Addr, Decoder);
776}
777
778static DecodeStatus
779DecodePNR_p8to15RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
780                              const MCDisassembler *Decoder) {
781  if (RegNo > 7)
782    return Fail;
783
784  // Just reuse the PPR decode table
785  return DecodePNRRegisterClass(Inst, RegNo + 8, Addr, Decoder);
786}
787
788static DecodeStatus DecodePPR2RegisterClass(MCInst &Inst, unsigned RegNo,
789                                            uint64_t Address,
790                                            const void *Decoder) {
791  if (RegNo > 15)
792    return Fail;
793
794  unsigned Register =
795      AArch64MCRegisterClasses[AArch64::PPR2RegClassID].getRegister(RegNo);
796  Inst.addOperand(MCOperand::createReg(Register));
797  return Success;
798}
799
800static DecodeStatus DecodePPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo,
801                                                uint64_t Address,
802                                                const void *Decoder) {
803  if ((RegNo * 2) > 14)
804    return Fail;
805  unsigned Register =
806      AArch64MCRegisterClasses[AArch64::PPR2RegClassID].getRegister(RegNo * 2);
807  Inst.addOperand(MCOperand::createReg(Register));
808  return Success;
809}
810
811static DecodeStatus DecodeQQRegisterClass(MCInst &Inst, unsigned RegNo,
812                                          uint64_t Addr,
813                                          const MCDisassembler *Decoder) {
814  if (RegNo > 31)
815    return Fail;
816  unsigned Register =
817      AArch64MCRegisterClasses[AArch64::QQRegClassID].getRegister(RegNo);
818  Inst.addOperand(MCOperand::createReg(Register));
819  return Success;
820}
821
822static DecodeStatus DecodeQQQRegisterClass(MCInst &Inst, unsigned RegNo,
823                                           uint64_t Addr,
824                                           const MCDisassembler *Decoder) {
825  if (RegNo > 31)
826    return Fail;
827  unsigned Register =
828      AArch64MCRegisterClasses[AArch64::QQQRegClassID].getRegister(RegNo);
829  Inst.addOperand(MCOperand::createReg(Register));
830  return Success;
831}
832
833static DecodeStatus DecodeQQQQRegisterClass(MCInst &Inst, unsigned RegNo,
834                                            uint64_t Addr,
835                                            const MCDisassembler *Decoder) {
836  if (RegNo > 31)
837    return Fail;
838  unsigned Register =
839      AArch64MCRegisterClasses[AArch64::QQQQRegClassID].getRegister(RegNo);
840  Inst.addOperand(MCOperand::createReg(Register));
841  return Success;
842}
843
844static DecodeStatus DecodeDDRegisterClass(MCInst &Inst, unsigned RegNo,
845                                          uint64_t Addr,
846                                          const MCDisassembler *Decoder) {
847  if (RegNo > 31)
848    return Fail;
849  unsigned Register =
850      AArch64MCRegisterClasses[AArch64::DDRegClassID].getRegister(RegNo);
851  Inst.addOperand(MCOperand::createReg(Register));
852  return Success;
853}
854
855static DecodeStatus DecodeDDDRegisterClass(MCInst &Inst, unsigned RegNo,
856                                           uint64_t Addr,
857                                           const MCDisassembler *Decoder) {
858  if (RegNo > 31)
859    return Fail;
860  unsigned Register =
861      AArch64MCRegisterClasses[AArch64::DDDRegClassID].getRegister(RegNo);
862  Inst.addOperand(MCOperand::createReg(Register));
863  return Success;
864}
865
866static DecodeStatus DecodeDDDDRegisterClass(MCInst &Inst, unsigned RegNo,
867                                            uint64_t Addr,
868                                            const MCDisassembler *Decoder) {
869  if (RegNo > 31)
870    return Fail;
871  unsigned Register =
872      AArch64MCRegisterClasses[AArch64::DDDDRegClassID].getRegister(RegNo);
873  Inst.addOperand(MCOperand::createReg(Register));
874  return Success;
875}
876
877static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
878                                               uint64_t Addr,
879                                               const MCDisassembler *Decoder) {
880  // scale{5} is asserted as 1 in tblgen.
881  Imm |= 0x20;
882  Inst.addOperand(MCOperand::createImm(64 - Imm));
883  return Success;
884}
885
886static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm,
887                                               uint64_t Addr,
888                                               const MCDisassembler *Decoder) {
889  Inst.addOperand(MCOperand::createImm(64 - Imm));
890  return Success;
891}
892
893static DecodeStatus DecodePCRelLabel16(MCInst &Inst, unsigned Imm,
894                                       uint64_t Addr,
895                                       const MCDisassembler *Decoder) {
896  // Immediate is encoded as the top 16-bits of an unsigned 18-bit negative
897  // PC-relative offset.
898  uint64_t ImmVal = Imm;
899  if (ImmVal > (1 << 16))
900    return Fail;
901  ImmVal = -ImmVal;
902  if (!Decoder->tryAddingSymbolicOperand(Inst, (ImmVal << 2), Addr,
903                                         /*IsBranch=*/false, 0, 0, 4))
904    Inst.addOperand(MCOperand::createImm(ImmVal));
905  return Success;
906}
907
908static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm,
909                                       uint64_t Addr,
910                                       const MCDisassembler *Decoder) {
911  int64_t ImmVal = Imm;
912
913  // Sign-extend 19-bit immediate.
914  if (ImmVal & (1 << (19 - 1)))
915    ImmVal |= ~((1LL << 19) - 1);
916
917  if (!Decoder->tryAddingSymbolicOperand(
918          Inst, ImmVal * 4, Addr, Inst.getOpcode() != AArch64::LDRXl, 0, 0, 4))
919    Inst.addOperand(MCOperand::createImm(ImmVal));
920  return Success;
921}
922
923static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm,
924                                    uint64_t Address,
925                                    const MCDisassembler *Decoder) {
926  Inst.addOperand(MCOperand::createImm((Imm  >> 1) & 1));
927  Inst.addOperand(MCOperand::createImm(Imm & 1));
928  return Success;
929}
930
931static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm,
932                                            uint64_t Address,
933                                            const MCDisassembler *Decoder) {
934  Inst.addOperand(MCOperand::createImm(Imm));
935
936  // Every system register in the encoding space is valid with the syntax
937  // S<op0>_<op1>_<Cn>_<Cm>_<op2>, so decoding system registers always succeeds.
938  return Success;
939}
940
941static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm,
942                                            uint64_t Address,
943                                            const MCDisassembler *Decoder) {
944  Inst.addOperand(MCOperand::createImm(Imm));
945
946  return Success;
947}
948
949static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn,
950                                              uint64_t Address,
951                                              const MCDisassembler *Decoder) {
952  // This decoder exists to add the dummy Lane operand to the MCInst, which must
953  // be 1 in assembly but has no other real manifestation.
954  unsigned Rd = fieldFromInstruction(Insn, 0, 5);
955  unsigned Rn = fieldFromInstruction(Insn, 5, 5);
956  unsigned IsToVec = fieldFromInstruction(Insn, 16, 1);
957
958  if (IsToVec) {
959    DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder);
960    DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
961  } else {
962    DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
963    DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder);
964  }
965
966  // Add the lane
967  Inst.addOperand(MCOperand::createImm(1));
968
969  return Success;
970}
971
972static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm,
973                                       unsigned Add) {
974  Inst.addOperand(MCOperand::createImm(Add - Imm));
975  return Success;
976}
977
978static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm,
979                                       unsigned Add) {
980  Inst.addOperand(MCOperand::createImm((Imm + Add) & (Add - 1)));
981  return Success;
982}
983
984static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm,
985                                         uint64_t Addr,
986                                         const MCDisassembler *Decoder) {
987  return DecodeVecShiftRImm(Inst, Imm, 64);
988}
989
990static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm,
991                                               uint64_t Addr,
992                                               const MCDisassembler *Decoder) {
993  return DecodeVecShiftRImm(Inst, Imm | 0x20, 64);
994}
995
996static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm,
997                                         uint64_t Addr,
998                                         const MCDisassembler *Decoder) {
999  return DecodeVecShiftRImm(Inst, Imm, 32);
1000}
1001
1002static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm,
1003                                               uint64_t Addr,
1004                                               const MCDisassembler *Decoder) {
1005  return DecodeVecShiftRImm(Inst, Imm | 0x10, 32);
1006}
1007
1008static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm,
1009                                         uint64_t Addr,
1010                                         const MCDisassembler *Decoder) {
1011  return DecodeVecShiftRImm(Inst, Imm, 16);
1012}
1013
1014static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm,
1015                                               uint64_t Addr,
1016                                               const MCDisassembler *Decoder) {
1017  return DecodeVecShiftRImm(Inst, Imm | 0x8, 16);
1018}
1019
1020static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm,
1021                                        uint64_t Addr,
1022                                        const MCDisassembler *Decoder) {
1023  return DecodeVecShiftRImm(Inst, Imm, 8);
1024}
1025
1026static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm,
1027                                         uint64_t Addr,
1028                                         const MCDisassembler *Decoder) {
1029  return DecodeVecShiftLImm(Inst, Imm, 64);
1030}
1031
1032static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm,
1033                                         uint64_t Addr,
1034                                         const MCDisassembler *Decoder) {
1035  return DecodeVecShiftLImm(Inst, Imm, 32);
1036}
1037
1038static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm,
1039                                         uint64_t Addr,
1040                                         const MCDisassembler *Decoder) {
1041  return DecodeVecShiftLImm(Inst, Imm, 16);
1042}
1043
1044static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm,
1045                                        uint64_t Addr,
1046                                        const MCDisassembler *Decoder) {
1047  return DecodeVecShiftLImm(Inst, Imm, 8);
1048}
1049
1050static DecodeStatus
1051DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
1052                               const MCDisassembler *Decoder) {
1053  unsigned Rd = fieldFromInstruction(insn, 0, 5);
1054  unsigned Rn = fieldFromInstruction(insn, 5, 5);
1055  unsigned Rm = fieldFromInstruction(insn, 16, 5);
1056  unsigned shiftHi = fieldFromInstruction(insn, 22, 2);
1057  unsigned shiftLo = fieldFromInstruction(insn, 10, 6);
1058  unsigned shift = (shiftHi << 6) | shiftLo;
1059  switch (Inst.getOpcode()) {
1060  default:
1061    return Fail;
1062  case AArch64::ADDWrs:
1063  case AArch64::ADDSWrs:
1064  case AArch64::SUBWrs:
1065  case AArch64::SUBSWrs:
1066    // if shift == '11' then ReservedValue()
1067    if (shiftHi == 0x3)
1068      return Fail;
1069    [[fallthrough]];
1070  case AArch64::ANDWrs:
1071  case AArch64::ANDSWrs:
1072  case AArch64::BICWrs:
1073  case AArch64::BICSWrs:
1074  case AArch64::ORRWrs:
1075  case AArch64::ORNWrs:
1076  case AArch64::EORWrs:
1077  case AArch64::EONWrs: {
1078    // if sf == '0' and imm6<5> == '1' then ReservedValue()
1079    if (shiftLo >> 5 == 1)
1080      return Fail;
1081    DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1082    DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
1083    DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1084    break;
1085  }
1086  case AArch64::ADDXrs:
1087  case AArch64::ADDSXrs:
1088  case AArch64::SUBXrs:
1089  case AArch64::SUBSXrs:
1090    // if shift == '11' then ReservedValue()
1091    if (shiftHi == 0x3)
1092      return Fail;
1093    [[fallthrough]];
1094  case AArch64::ANDXrs:
1095  case AArch64::ANDSXrs:
1096  case AArch64::BICXrs:
1097  case AArch64::BICSXrs:
1098  case AArch64::ORRXrs:
1099  case AArch64::ORNXrs:
1100  case AArch64::EORXrs:
1101  case AArch64::EONXrs:
1102    DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1103    DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
1104    DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1105    break;
1106  }
1107
1108  Inst.addOperand(MCOperand::createImm(shift));
1109  return Success;
1110}
1111
1112static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn,
1113                                             uint64_t Addr,
1114                                             const MCDisassembler *Decoder) {
1115  unsigned Rd = fieldFromInstruction(insn, 0, 5);
1116  unsigned imm = fieldFromInstruction(insn, 5, 16);
1117  unsigned shift = fieldFromInstruction(insn, 21, 2);
1118  shift <<= 4;
1119  switch (Inst.getOpcode()) {
1120  default:
1121    return Fail;
1122  case AArch64::MOVZWi:
1123  case AArch64::MOVNWi:
1124  case AArch64::MOVKWi:
1125    if (shift & (1U << 5))
1126      return Fail;
1127    DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1128    break;
1129  case AArch64::MOVZXi:
1130  case AArch64::MOVNXi:
1131  case AArch64::MOVKXi:
1132    DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1133    break;
1134  }
1135
1136  if (Inst.getOpcode() == AArch64::MOVKWi ||
1137      Inst.getOpcode() == AArch64::MOVKXi)
1138    Inst.addOperand(Inst.getOperand(0));
1139
1140  Inst.addOperand(MCOperand::createImm(imm));
1141  Inst.addOperand(MCOperand::createImm(shift));
1142  return Success;
1143}
1144
1145static DecodeStatus
1146DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
1147                              const MCDisassembler *Decoder) {
1148  unsigned Rt = fieldFromInstruction(insn, 0, 5);
1149  unsigned Rn = fieldFromInstruction(insn, 5, 5);
1150  unsigned offset = fieldFromInstruction(insn, 10, 12);
1151
1152  switch (Inst.getOpcode()) {
1153  default:
1154    return Fail;
1155  case AArch64::PRFMui:
1156    // Rt is an immediate in prefetch.
1157    Inst.addOperand(MCOperand::createImm(Rt));
1158    break;
1159  case AArch64::STRBBui:
1160  case AArch64::LDRBBui:
1161  case AArch64::LDRSBWui:
1162  case AArch64::STRHHui:
1163  case AArch64::LDRHHui:
1164  case AArch64::LDRSHWui:
1165  case AArch64::STRWui:
1166  case AArch64::LDRWui:
1167    DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1168    break;
1169  case AArch64::LDRSBXui:
1170  case AArch64::LDRSHXui:
1171  case AArch64::LDRSWui:
1172  case AArch64::STRXui:
1173  case AArch64::LDRXui:
1174    DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1175    break;
1176  case AArch64::LDRQui:
1177  case AArch64::STRQui:
1178    DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1179    break;
1180  case AArch64::LDRDui:
1181  case AArch64::STRDui:
1182    DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1183    break;
1184  case AArch64::LDRSui:
1185  case AArch64::STRSui:
1186    DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1187    break;
1188  case AArch64::LDRHui:
1189  case AArch64::STRHui:
1190    DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
1191    break;
1192  case AArch64::LDRBui:
1193  case AArch64::STRBui:
1194    DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
1195    break;
1196  }
1197
1198  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1199  if (!Decoder->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 0, 4))
1200    Inst.addOperand(MCOperand::createImm(offset));
1201  return Success;
1202}
1203
1204static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn,
1205                                                uint64_t Addr,
1206                                                const MCDisassembler *Decoder) {
1207  unsigned Rt = fieldFromInstruction(insn, 0, 5);
1208  unsigned Rn = fieldFromInstruction(insn, 5, 5);
1209  int64_t offset = fieldFromInstruction(insn, 12, 9);
1210
1211  // offset is a 9-bit signed immediate, so sign extend it to
1212  // fill the unsigned.
1213  if (offset & (1 << (9 - 1)))
1214    offset |= ~((1LL << 9) - 1);
1215
1216  // First operand is always the writeback to the address register, if needed.
1217  switch (Inst.getOpcode()) {
1218  default:
1219    break;
1220  case AArch64::LDRSBWpre:
1221  case AArch64::LDRSHWpre:
1222  case AArch64::STRBBpre:
1223  case AArch64::LDRBBpre:
1224  case AArch64::STRHHpre:
1225  case AArch64::LDRHHpre:
1226  case AArch64::STRWpre:
1227  case AArch64::LDRWpre:
1228  case AArch64::LDRSBWpost:
1229  case AArch64::LDRSHWpost:
1230  case AArch64::STRBBpost:
1231  case AArch64::LDRBBpost:
1232  case AArch64::STRHHpost:
1233  case AArch64::LDRHHpost:
1234  case AArch64::STRWpost:
1235  case AArch64::LDRWpost:
1236  case AArch64::LDRSBXpre:
1237  case AArch64::LDRSHXpre:
1238  case AArch64::STRXpre:
1239  case AArch64::LDRSWpre:
1240  case AArch64::LDRXpre:
1241  case AArch64::LDRSBXpost:
1242  case AArch64::LDRSHXpost:
1243  case AArch64::STRXpost:
1244  case AArch64::LDRSWpost:
1245  case AArch64::LDRXpost:
1246  case AArch64::LDRQpre:
1247  case AArch64::STRQpre:
1248  case AArch64::LDRQpost:
1249  case AArch64::STRQpost:
1250  case AArch64::LDRDpre:
1251  case AArch64::STRDpre:
1252  case AArch64::LDRDpost:
1253  case AArch64::STRDpost:
1254  case AArch64::LDRSpre:
1255  case AArch64::STRSpre:
1256  case AArch64::LDRSpost:
1257  case AArch64::STRSpost:
1258  case AArch64::LDRHpre:
1259  case AArch64::STRHpre:
1260  case AArch64::LDRHpost:
1261  case AArch64::STRHpost:
1262  case AArch64::LDRBpre:
1263  case AArch64::STRBpre:
1264  case AArch64::LDRBpost:
1265  case AArch64::STRBpost:
1266    DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1267    break;
1268  }
1269
1270  switch (Inst.getOpcode()) {
1271  default:
1272    return Fail;
1273  case AArch64::PRFUMi:
1274    // Rt is an immediate in prefetch.
1275    Inst.addOperand(MCOperand::createImm(Rt));
1276    break;
1277  case AArch64::STURBBi:
1278  case AArch64::LDURBBi:
1279  case AArch64::LDURSBWi:
1280  case AArch64::STURHHi:
1281  case AArch64::LDURHHi:
1282  case AArch64::LDURSHWi:
1283  case AArch64::STURWi:
1284  case AArch64::LDURWi:
1285  case AArch64::LDTRSBWi:
1286  case AArch64::LDTRSHWi:
1287  case AArch64::STTRWi:
1288  case AArch64::LDTRWi:
1289  case AArch64::STTRHi:
1290  case AArch64::LDTRHi:
1291  case AArch64::LDTRBi:
1292  case AArch64::STTRBi:
1293  case AArch64::LDRSBWpre:
1294  case AArch64::LDRSHWpre:
1295  case AArch64::STRBBpre:
1296  case AArch64::LDRBBpre:
1297  case AArch64::STRHHpre:
1298  case AArch64::LDRHHpre:
1299  case AArch64::STRWpre:
1300  case AArch64::LDRWpre:
1301  case AArch64::LDRSBWpost:
1302  case AArch64::LDRSHWpost:
1303  case AArch64::STRBBpost:
1304  case AArch64::LDRBBpost:
1305  case AArch64::STRHHpost:
1306  case AArch64::LDRHHpost:
1307  case AArch64::STRWpost:
1308  case AArch64::LDRWpost:
1309  case AArch64::STLURBi:
1310  case AArch64::STLURHi:
1311  case AArch64::STLURWi:
1312  case AArch64::LDAPURBi:
1313  case AArch64::LDAPURSBWi:
1314  case AArch64::LDAPURHi:
1315  case AArch64::LDAPURSHWi:
1316  case AArch64::LDAPURi:
1317    DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1318    break;
1319  case AArch64::LDURSBXi:
1320  case AArch64::LDURSHXi:
1321  case AArch64::LDURSWi:
1322  case AArch64::STURXi:
1323  case AArch64::LDURXi:
1324  case AArch64::LDTRSBXi:
1325  case AArch64::LDTRSHXi:
1326  case AArch64::LDTRSWi:
1327  case AArch64::STTRXi:
1328  case AArch64::LDTRXi:
1329  case AArch64::LDRSBXpre:
1330  case AArch64::LDRSHXpre:
1331  case AArch64::STRXpre:
1332  case AArch64::LDRSWpre:
1333  case AArch64::LDRXpre:
1334  case AArch64::LDRSBXpost:
1335  case AArch64::LDRSHXpost:
1336  case AArch64::STRXpost:
1337  case AArch64::LDRSWpost:
1338  case AArch64::LDRXpost:
1339  case AArch64::LDAPURSWi:
1340  case AArch64::LDAPURSHXi:
1341  case AArch64::LDAPURSBXi:
1342  case AArch64::STLURXi:
1343  case AArch64::LDAPURXi:
1344    DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1345    break;
1346  case AArch64::LDURQi:
1347  case AArch64::STURQi:
1348  case AArch64::LDRQpre:
1349  case AArch64::STRQpre:
1350  case AArch64::LDRQpost:
1351  case AArch64::STRQpost:
1352    DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1353    break;
1354  case AArch64::LDURDi:
1355  case AArch64::STURDi:
1356  case AArch64::LDRDpre:
1357  case AArch64::STRDpre:
1358  case AArch64::LDRDpost:
1359  case AArch64::STRDpost:
1360    DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1361    break;
1362  case AArch64::LDURSi:
1363  case AArch64::STURSi:
1364  case AArch64::LDRSpre:
1365  case AArch64::STRSpre:
1366  case AArch64::LDRSpost:
1367  case AArch64::STRSpost:
1368    DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1369    break;
1370  case AArch64::LDURHi:
1371  case AArch64::STURHi:
1372  case AArch64::LDRHpre:
1373  case AArch64::STRHpre:
1374  case AArch64::LDRHpost:
1375  case AArch64::STRHpost:
1376    DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
1377    break;
1378  case AArch64::LDURBi:
1379  case AArch64::STURBi:
1380  case AArch64::LDRBpre:
1381  case AArch64::STRBpre:
1382  case AArch64::LDRBpost:
1383  case AArch64::STRBpost:
1384    DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
1385    break;
1386  }
1387
1388  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1389  Inst.addOperand(MCOperand::createImm(offset));
1390
1391  bool IsLoad = fieldFromInstruction(insn, 22, 1);
1392  bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0;
1393  bool IsFP = fieldFromInstruction(insn, 26, 1);
1394
1395  // Cannot write back to a transfer register (but xzr != sp).
1396  if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn)
1397    return SoftFail;
1398
1399  return Success;
1400}
1401
1402static DecodeStatus
1403DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
1404                               const MCDisassembler *Decoder) {
1405  unsigned Rt = fieldFromInstruction(insn, 0, 5);
1406  unsigned Rn = fieldFromInstruction(insn, 5, 5);
1407  unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1408  unsigned Rs = fieldFromInstruction(insn, 16, 5);
1409
1410  unsigned Opcode = Inst.getOpcode();
1411  switch (Opcode) {
1412  default:
1413    return Fail;
1414  case AArch64::STLXRW:
1415  case AArch64::STLXRB:
1416  case AArch64::STLXRH:
1417  case AArch64::STXRW:
1418  case AArch64::STXRB:
1419  case AArch64::STXRH:
1420    DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1421    [[fallthrough]];
1422  case AArch64::LDARW:
1423  case AArch64::LDARB:
1424  case AArch64::LDARH:
1425  case AArch64::LDAXRW:
1426  case AArch64::LDAXRB:
1427  case AArch64::LDAXRH:
1428  case AArch64::LDXRW:
1429  case AArch64::LDXRB:
1430  case AArch64::LDXRH:
1431  case AArch64::STLRW:
1432  case AArch64::STLRB:
1433  case AArch64::STLRH:
1434  case AArch64::STLLRW:
1435  case AArch64::STLLRB:
1436  case AArch64::STLLRH:
1437  case AArch64::LDLARW:
1438  case AArch64::LDLARB:
1439  case AArch64::LDLARH:
1440    DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1441    break;
1442  case AArch64::STLXRX:
1443  case AArch64::STXRX:
1444    DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1445    [[fallthrough]];
1446  case AArch64::LDARX:
1447  case AArch64::LDAXRX:
1448  case AArch64::LDXRX:
1449  case AArch64::STLRX:
1450  case AArch64::LDLARX:
1451  case AArch64::STLLRX:
1452    DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1453    break;
1454  case AArch64::STLXPW:
1455  case AArch64::STXPW:
1456    DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1457    [[fallthrough]];
1458  case AArch64::LDAXPW:
1459  case AArch64::LDXPW:
1460    DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1461    DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1462    break;
1463  case AArch64::STLXPX:
1464  case AArch64::STXPX:
1465    DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1466    [[fallthrough]];
1467  case AArch64::LDAXPX:
1468  case AArch64::LDXPX:
1469    DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1470    DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1471    break;
1472  }
1473
1474  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1475
1476  // You shouldn't load to the same register twice in an instruction...
1477  if ((Opcode == AArch64::LDAXPW || Opcode == AArch64::LDXPW ||
1478       Opcode == AArch64::LDAXPX || Opcode == AArch64::LDXPX) &&
1479      Rt == Rt2)
1480    return SoftFail;
1481
1482  return Success;
1483}
1484
1485static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn,
1486                                              uint64_t Addr,
1487                                              const MCDisassembler *Decoder) {
1488  unsigned Rt = fieldFromInstruction(insn, 0, 5);
1489  unsigned Rn = fieldFromInstruction(insn, 5, 5);
1490  unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1491  int64_t offset = fieldFromInstruction(insn, 15, 7);
1492  bool IsLoad = fieldFromInstruction(insn, 22, 1);
1493
1494  // offset is a 7-bit signed immediate, so sign extend it to
1495  // fill the unsigned.
1496  if (offset & (1 << (7 - 1)))
1497    offset |= ~((1LL << 7) - 1);
1498
1499  unsigned Opcode = Inst.getOpcode();
1500  bool NeedsDisjointWritebackTransfer = false;
1501
1502  // First operand is always writeback of base register.
1503  switch (Opcode) {
1504  default:
1505    break;
1506  case AArch64::LDPXpost:
1507  case AArch64::STPXpost:
1508  case AArch64::LDPSWpost:
1509  case AArch64::LDPXpre:
1510  case AArch64::STPXpre:
1511  case AArch64::LDPSWpre:
1512  case AArch64::LDPWpost:
1513  case AArch64::STPWpost:
1514  case AArch64::LDPWpre:
1515  case AArch64::STPWpre:
1516  case AArch64::LDPQpost:
1517  case AArch64::STPQpost:
1518  case AArch64::LDPQpre:
1519  case AArch64::STPQpre:
1520  case AArch64::LDPDpost:
1521  case AArch64::STPDpost:
1522  case AArch64::LDPDpre:
1523  case AArch64::STPDpre:
1524  case AArch64::LDPSpost:
1525  case AArch64::STPSpost:
1526  case AArch64::LDPSpre:
1527  case AArch64::STPSpre:
1528  case AArch64::STGPpre:
1529  case AArch64::STGPpost:
1530    DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1531    break;
1532  }
1533
1534  switch (Opcode) {
1535  default:
1536    return Fail;
1537  case AArch64::LDPXpost:
1538  case AArch64::STPXpost:
1539  case AArch64::LDPSWpost:
1540  case AArch64::LDPXpre:
1541  case AArch64::STPXpre:
1542  case AArch64::LDPSWpre:
1543  case AArch64::STGPpre:
1544  case AArch64::STGPpost:
1545    NeedsDisjointWritebackTransfer = true;
1546    [[fallthrough]];
1547  case AArch64::LDNPXi:
1548  case AArch64::STNPXi:
1549  case AArch64::LDPXi:
1550  case AArch64::STPXi:
1551  case AArch64::LDPSWi:
1552  case AArch64::STGPi:
1553    DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1554    DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1555    break;
1556  case AArch64::LDPWpost:
1557  case AArch64::STPWpost:
1558  case AArch64::LDPWpre:
1559  case AArch64::STPWpre:
1560    NeedsDisjointWritebackTransfer = true;
1561    [[fallthrough]];
1562  case AArch64::LDNPWi:
1563  case AArch64::STNPWi:
1564  case AArch64::LDPWi:
1565  case AArch64::STPWi:
1566    DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1567    DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1568    break;
1569  case AArch64::LDNPQi:
1570  case AArch64::STNPQi:
1571  case AArch64::LDPQpost:
1572  case AArch64::STPQpost:
1573  case AArch64::LDPQi:
1574  case AArch64::STPQi:
1575  case AArch64::LDPQpre:
1576  case AArch64::STPQpre:
1577    DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1578    DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder);
1579    break;
1580  case AArch64::LDNPDi:
1581  case AArch64::STNPDi:
1582  case AArch64::LDPDpost:
1583  case AArch64::STPDpost:
1584  case AArch64::LDPDi:
1585  case AArch64::STPDi:
1586  case AArch64::LDPDpre:
1587  case AArch64::STPDpre:
1588    DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1589    DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1590    break;
1591  case AArch64::LDNPSi:
1592  case AArch64::STNPSi:
1593  case AArch64::LDPSpost:
1594  case AArch64::STPSpost:
1595  case AArch64::LDPSi:
1596  case AArch64::STPSi:
1597  case AArch64::LDPSpre:
1598  case AArch64::STPSpre:
1599    DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1600    DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1601    break;
1602  }
1603
1604  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1605  Inst.addOperand(MCOperand::createImm(offset));
1606
1607  // You shouldn't load to the same register twice in an instruction...
1608  if (IsLoad && Rt == Rt2)
1609    return SoftFail;
1610
1611  // ... or do any operation that writes-back to a transfer register. But note
1612  // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different.
1613  if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn))
1614    return SoftFail;
1615
1616  return Success;
1617}
1618
1619static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn,
1620                                              uint64_t Addr,
1621                                              const MCDisassembler *Decoder) {
1622  unsigned Rt = fieldFromInstruction(insn, 0, 5);
1623  unsigned Rn = fieldFromInstruction(insn, 5, 5);
1624  uint64_t offset = fieldFromInstruction(insn, 22, 1) << 9 |
1625                    fieldFromInstruction(insn, 12, 9);
1626  unsigned writeback = fieldFromInstruction(insn, 11, 1);
1627
1628  switch (Inst.getOpcode()) {
1629  default:
1630    return Fail;
1631  case AArch64::LDRAAwriteback:
1632  case AArch64::LDRABwriteback:
1633    DecodeGPR64spRegisterClass(Inst, Rn /* writeback register */, Addr,
1634                               Decoder);
1635    break;
1636  case AArch64::LDRAAindexed:
1637  case AArch64::LDRABindexed:
1638    break;
1639  }
1640
1641  DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1642  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1643  DecodeSImm<10>(Inst, offset, Addr, Decoder);
1644
1645  if (writeback && Rt == Rn && Rn != 31) {
1646    return SoftFail;
1647  }
1648
1649  return Success;
1650}
1651
1652static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn,
1653                                                uint64_t Addr,
1654                                                const MCDisassembler *Decoder) {
1655  unsigned Rd = fieldFromInstruction(insn, 0, 5);
1656  unsigned Rn = fieldFromInstruction(insn, 5, 5);
1657  unsigned Rm = fieldFromInstruction(insn, 16, 5);
1658  unsigned extend = fieldFromInstruction(insn, 10, 6);
1659
1660  unsigned shift = extend & 0x7;
1661  if (shift > 4)
1662    return Fail;
1663
1664  switch (Inst.getOpcode()) {
1665  default:
1666    return Fail;
1667  case AArch64::ADDWrx:
1668  case AArch64::SUBWrx:
1669    DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1670    DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1671    DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1672    break;
1673  case AArch64::ADDSWrx:
1674  case AArch64::SUBSWrx:
1675    DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1676    DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1677    DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1678    break;
1679  case AArch64::ADDXrx:
1680  case AArch64::SUBXrx:
1681    DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1682    DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1683    DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1684    break;
1685  case AArch64::ADDSXrx:
1686  case AArch64::SUBSXrx:
1687    DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1688    DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1689    DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1690    break;
1691  case AArch64::ADDXrx64:
1692  case AArch64::SUBXrx64:
1693    DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1694    DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1695    DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1696    break;
1697  case AArch64::SUBSXrx64:
1698  case AArch64::ADDSXrx64:
1699    DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1700    DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1701    DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1702    break;
1703  }
1704
1705  Inst.addOperand(MCOperand::createImm(extend));
1706  return Success;
1707}
1708
1709static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn,
1710                                                uint64_t Addr,
1711                                                const MCDisassembler *Decoder) {
1712  unsigned Rd = fieldFromInstruction(insn, 0, 5);
1713  unsigned Rn = fieldFromInstruction(insn, 5, 5);
1714  unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1715  unsigned imm;
1716
1717  if (Datasize) {
1718    if (Inst.getOpcode() == AArch64::ANDSXri)
1719      DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1720    else
1721      DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1722    DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
1723    imm = fieldFromInstruction(insn, 10, 13);
1724    if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64))
1725      return Fail;
1726  } else {
1727    if (Inst.getOpcode() == AArch64::ANDSWri)
1728      DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1729    else
1730      DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1731    DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
1732    imm = fieldFromInstruction(insn, 10, 12);
1733    if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 32))
1734      return Fail;
1735  }
1736  Inst.addOperand(MCOperand::createImm(imm));
1737  return Success;
1738}
1739
1740static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn,
1741                                            uint64_t Addr,
1742                                            const MCDisassembler *Decoder) {
1743  unsigned Rd = fieldFromInstruction(insn, 0, 5);
1744  unsigned cmode = fieldFromInstruction(insn, 12, 4);
1745  unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1746  imm |= fieldFromInstruction(insn, 5, 5);
1747
1748  if (Inst.getOpcode() == AArch64::MOVID)
1749    DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder);
1750  else
1751    DecodeFPR128RegisterClass(Inst, Rd, Addr, Decoder);
1752
1753  Inst.addOperand(MCOperand::createImm(imm));
1754
1755  switch (Inst.getOpcode()) {
1756  default:
1757    break;
1758  case AArch64::MOVIv4i16:
1759  case AArch64::MOVIv8i16:
1760  case AArch64::MVNIv4i16:
1761  case AArch64::MVNIv8i16:
1762  case AArch64::MOVIv2i32:
1763  case AArch64::MOVIv4i32:
1764  case AArch64::MVNIv2i32:
1765  case AArch64::MVNIv4i32:
1766    Inst.addOperand(MCOperand::createImm((cmode & 6) << 2));
1767    break;
1768  case AArch64::MOVIv2s_msl:
1769  case AArch64::MOVIv4s_msl:
1770  case AArch64::MVNIv2s_msl:
1771  case AArch64::MVNIv4s_msl:
1772    Inst.addOperand(MCOperand::createImm((cmode & 1) ? 0x110 : 0x108));
1773    break;
1774  }
1775
1776  return Success;
1777}
1778
1779static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn,
1780                                                uint64_t Addr,
1781                                                const MCDisassembler *Decoder) {
1782  unsigned Rd = fieldFromInstruction(insn, 0, 5);
1783  unsigned cmode = fieldFromInstruction(insn, 12, 4);
1784  unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1785  imm |= fieldFromInstruction(insn, 5, 5);
1786
1787  // Tied operands added twice.
1788  DecodeFPR128RegisterClass(Inst, Rd, Addr, Decoder);
1789  DecodeFPR128RegisterClass(Inst, Rd, Addr, Decoder);
1790
1791  Inst.addOperand(MCOperand::createImm(imm));
1792  Inst.addOperand(MCOperand::createImm((cmode & 6) << 2));
1793
1794  return Success;
1795}
1796
1797static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn,
1798                                         uint64_t Addr,
1799                                         const MCDisassembler *Decoder) {
1800  unsigned Rd = fieldFromInstruction(insn, 0, 5);
1801  int64_t imm = fieldFromInstruction(insn, 5, 19) << 2;
1802  imm |= fieldFromInstruction(insn, 29, 2);
1803
1804  // Sign-extend the 21-bit immediate.
1805  if (imm & (1 << (21 - 1)))
1806    imm |= ~((1LL << 21) - 1);
1807
1808  DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1809  if (!Decoder->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 0, 4))
1810    Inst.addOperand(MCOperand::createImm(imm));
1811
1812  return Success;
1813}
1814
1815static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn,
1816                                         uint64_t Addr,
1817                                         const MCDisassembler *Decoder) {
1818  unsigned Rd = fieldFromInstruction(insn, 0, 5);
1819  unsigned Rn = fieldFromInstruction(insn, 5, 5);
1820  unsigned Imm = fieldFromInstruction(insn, 10, 14);
1821  unsigned S = fieldFromInstruction(insn, 29, 1);
1822  unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1823
1824  unsigned ShifterVal = (Imm >> 12) & 3;
1825  unsigned ImmVal = Imm & 0xFFF;
1826
1827  if (ShifterVal != 0 && ShifterVal != 1)
1828    return Fail;
1829
1830  if (Datasize) {
1831    if (Rd == 31 && !S)
1832      DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1833    else
1834      DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1835    DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1836  } else {
1837    if (Rd == 31 && !S)
1838      DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1839    else
1840      DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1841    DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1842  }
1843
1844  if (!Decoder->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 0, 4))
1845    Inst.addOperand(MCOperand::createImm(ImmVal));
1846  Inst.addOperand(MCOperand::createImm(12 * ShifterVal));
1847  return Success;
1848}
1849
1850static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn,
1851                                              uint64_t Addr,
1852                                              const MCDisassembler *Decoder) {
1853  int64_t imm = fieldFromInstruction(insn, 0, 26);
1854
1855  // Sign-extend the 26-bit immediate.
1856  if (imm & (1 << (26 - 1)))
1857    imm |= ~((1LL << 26) - 1);
1858
1859  if (!Decoder->tryAddingSymbolicOperand(Inst, imm * 4, Addr, true, 0, 0, 4))
1860    Inst.addOperand(MCOperand::createImm(imm));
1861
1862  return Success;
1863}
1864
1865static bool isInvalidPState(uint64_t Op1, uint64_t Op2) {
1866  return Op1 == 0b000 && (Op2 == 0b000 || // CFINV
1867                          Op2 == 0b001 || // XAFlag
1868                          Op2 == 0b010);  // AXFlag
1869}
1870
1871static DecodeStatus
1872DecodeSystemPStateImm0_15Instruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
1873                                     const MCDisassembler *Decoder) {
1874  uint64_t op1 = fieldFromInstruction(insn, 16, 3);
1875  uint64_t op2 = fieldFromInstruction(insn, 5, 3);
1876  uint64_t imm = fieldFromInstruction(insn, 8, 4);
1877  uint64_t pstate_field = (op1 << 3) | op2;
1878
1879  if (isInvalidPState(op1, op2))
1880    return Fail;
1881
1882  Inst.addOperand(MCOperand::createImm(pstate_field));
1883  Inst.addOperand(MCOperand::createImm(imm));
1884
1885  auto PState = AArch64PState::lookupPStateImm0_15ByEncoding(pstate_field);
1886  if (PState &&
1887      PState->haveFeatures(Decoder->getSubtargetInfo().getFeatureBits()))
1888    return Success;
1889  return Fail;
1890}
1891
1892static DecodeStatus
1893DecodeSystemPStateImm0_1Instruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
1894                                    const MCDisassembler *Decoder) {
1895  uint64_t op1 = fieldFromInstruction(insn, 16, 3);
1896  uint64_t op2 = fieldFromInstruction(insn, 5, 3);
1897  uint64_t crm_high = fieldFromInstruction(insn, 9, 3);
1898  uint64_t imm = fieldFromInstruction(insn, 8, 1);
1899  uint64_t pstate_field = (crm_high << 6) | (op1 << 3) | op2;
1900
1901  if (isInvalidPState(op1, op2))
1902    return Fail;
1903
1904  Inst.addOperand(MCOperand::createImm(pstate_field));
1905  Inst.addOperand(MCOperand::createImm(imm));
1906
1907  auto PState = AArch64PState::lookupPStateImm0_1ByEncoding(pstate_field);
1908  if (PState &&
1909      PState->haveFeatures(Decoder->getSubtargetInfo().getFeatureBits()))
1910    return Success;
1911  return Fail;
1912}
1913
1914static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn,
1915                                        uint64_t Addr,
1916                                        const MCDisassembler *Decoder) {
1917  uint64_t Rt = fieldFromInstruction(insn, 0, 5);
1918  uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5;
1919  bit |= fieldFromInstruction(insn, 19, 5);
1920  int64_t dst = fieldFromInstruction(insn, 5, 14);
1921
1922  // Sign-extend 14-bit immediate.
1923  if (dst & (1 << (14 - 1)))
1924    dst |= ~((1LL << 14) - 1);
1925
1926  if (fieldFromInstruction(insn, 31, 1) == 0)
1927    DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1928  else
1929    DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1930  Inst.addOperand(MCOperand::createImm(bit));
1931  if (!Decoder->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 0, 4))
1932    Inst.addOperand(MCOperand::createImm(dst));
1933
1934  return Success;
1935}
1936
1937static DecodeStatus
1938DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegClassID,
1939                                    unsigned RegNo, uint64_t Addr,
1940                                    const MCDisassembler *Decoder) {
1941  // Register number must be even (see CASP instruction)
1942  if (RegNo & 0x1)
1943    return Fail;
1944
1945  unsigned Reg = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo / 2);
1946  Inst.addOperand(MCOperand::createReg(Reg));
1947  return Success;
1948}
1949
1950static DecodeStatus
1951DecodeWSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
1952                                  const MCDisassembler *Decoder) {
1953  return DecodeGPRSeqPairsClassRegisterClass(Inst,
1954                                             AArch64::WSeqPairsClassRegClassID,
1955                                             RegNo, Addr, Decoder);
1956}
1957
1958static DecodeStatus
1959DecodeXSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
1960                                  const MCDisassembler *Decoder) {
1961  return DecodeGPRSeqPairsClassRegisterClass(Inst,
1962                                             AArch64::XSeqPairsClassRegClassID,
1963                                             RegNo, Addr, Decoder);
1964}
1965
1966static DecodeStatus DecodeSyspXzrInstruction(MCInst &Inst, uint32_t insn,
1967                                             uint64_t Addr,
1968                                             const MCDisassembler *Decoder) {
1969  unsigned op1 = fieldFromInstruction(insn, 16, 3);
1970  unsigned CRn = fieldFromInstruction(insn, 12, 4);
1971  unsigned CRm = fieldFromInstruction(insn, 8, 4);
1972  unsigned op2 = fieldFromInstruction(insn, 5, 3);
1973  unsigned Rt = fieldFromInstruction(insn, 0, 5);
1974  if (Rt != 0b11111)
1975    return Fail;
1976
1977  Inst.addOperand(MCOperand::createImm(op1));
1978  Inst.addOperand(MCOperand::createImm(CRn));
1979  Inst.addOperand(MCOperand::createImm(CRm));
1980  Inst.addOperand(MCOperand::createImm(op2));
1981  DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1982
1983  return Success;
1984}
1985
1986static DecodeStatus
1987DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
1988                               const MCDisassembler *Decoder) {
1989  unsigned Zdn = fieldFromInstruction(insn, 0, 5);
1990  unsigned imm = fieldFromInstruction(insn, 5, 13);
1991  if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64))
1992    return Fail;
1993
1994  // The same (tied) operand is added twice to the instruction.
1995  DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder);
1996  if (Inst.getOpcode() != AArch64::DUPM_ZI)
1997    DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder);
1998  Inst.addOperand(MCOperand::createImm(imm));
1999  return Success;
2000}
2001
2002template <int Bits>
2003static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address,
2004                               const MCDisassembler *Decoder) {
2005  if (Imm & ~((1LL << Bits) - 1))
2006      return Fail;
2007
2008  // Imm is a signed immediate, so sign extend it.
2009  if (Imm & (1 << (Bits - 1)))
2010    Imm |= ~((1LL << Bits) - 1);
2011
2012  Inst.addOperand(MCOperand::createImm(Imm));
2013  return Success;
2014}
2015
2016// Decode 8-bit signed/unsigned immediate for a given element width.
2017template <int ElementWidth>
2018static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, uint64_t Addr,
2019                                     const MCDisassembler *Decoder) {
2020  unsigned Val = (uint8_t)Imm;
2021  unsigned Shift = (Imm & 0x100) ? 8 : 0;
2022  if (ElementWidth == 8 && Shift)
2023    return Fail;
2024  Inst.addOperand(MCOperand::createImm(Val));
2025  Inst.addOperand(MCOperand::createImm(Shift));
2026  return Success;
2027}
2028
2029// Decode uimm4 ranged from 1-16.
2030static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm,
2031                                       uint64_t Addr,
2032                                       const MCDisassembler *Decoder) {
2033  Inst.addOperand(MCOperand::createImm(Imm + 1));
2034  return Success;
2035}
2036
2037static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address,
2038                                 const MCDisassembler *Decoder) {
2039  if (AArch64SVCR::lookupSVCRByEncoding(Imm)) {
2040    Inst.addOperand(MCOperand::createImm(Imm));
2041    return Success;
2042  }
2043  return Fail;
2044}
2045
2046static DecodeStatus DecodeCPYMemOpInstruction(MCInst &Inst, uint32_t insn,
2047                                              uint64_t Addr,
2048                                              const MCDisassembler *Decoder) {
2049  unsigned Rd = fieldFromInstruction(insn, 0, 5);
2050  unsigned Rs = fieldFromInstruction(insn, 16, 5);
2051  unsigned Rn = fieldFromInstruction(insn, 5, 5);
2052
2053  // None of the registers may alias: if they do, then the instruction is not
2054  // merely unpredictable but actually entirely unallocated.
2055  if (Rd == Rs || Rs == Rn || Rd == Rn)
2056    return MCDisassembler::Fail;
2057
2058  // All three register operands are written back, so they all appear
2059  // twice in the operand list, once as outputs and once as inputs.
2060  if (!DecodeGPR64commonRegisterClass(Inst, Rd, Addr, Decoder) ||
2061      !DecodeGPR64commonRegisterClass(Inst, Rs, Addr, Decoder) ||
2062      !DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder) ||
2063      !DecodeGPR64commonRegisterClass(Inst, Rd, Addr, Decoder) ||
2064      !DecodeGPR64commonRegisterClass(Inst, Rs, Addr, Decoder) ||
2065      !DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder))
2066    return MCDisassembler::Fail;
2067
2068  return MCDisassembler::Success;
2069}
2070
2071static DecodeStatus DecodeSETMemOpInstruction(MCInst &Inst, uint32_t insn,
2072                                              uint64_t Addr,
2073                                              const MCDisassembler *Decoder) {
2074  unsigned Rd = fieldFromInstruction(insn, 0, 5);
2075  unsigned Rm = fieldFromInstruction(insn, 16, 5);
2076  unsigned Rn = fieldFromInstruction(insn, 5, 5);
2077
2078  // None of the registers may alias: if they do, then the instruction is not
2079  // merely unpredictable but actually entirely unallocated.
2080  if (Rd == Rm || Rm == Rn || Rd == Rn)
2081    return MCDisassembler::Fail;
2082
2083  // Rd and Rn (not Rm) register operands are written back, so they appear
2084  // twice in the operand list, once as outputs and once as inputs.
2085  if (!DecodeGPR64commonRegisterClass(Inst, Rd, Addr, Decoder) ||
2086      !DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder) ||
2087      !DecodeGPR64commonRegisterClass(Inst, Rd, Addr, Decoder) ||
2088      !DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder) ||
2089      !DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder))
2090    return MCDisassembler::Fail;
2091
2092  return MCDisassembler::Success;
2093}
2094
2095static DecodeStatus DecodePRFMRegInstruction(MCInst &Inst, uint32_t insn,
2096                                             uint64_t Addr,
2097                                             const MCDisassembler *Decoder) {
2098  // PRFM with Rt = '11xxx' should be decoded as RPRFM.
2099  // Fail to decode and defer to fallback decoder table to decode RPRFM.
2100  unsigned Mask = 0x18;
2101  uint64_t Rt = fieldFromInstruction(insn, 0, 5);
2102  if ((Rt & Mask) == Mask)
2103    return Fail;
2104
2105  uint64_t Rn = fieldFromInstruction(insn, 5, 5);
2106  uint64_t Shift = fieldFromInstruction(insn, 12, 1);
2107  uint64_t Extend = fieldFromInstruction(insn, 15, 1);
2108  uint64_t Rm = fieldFromInstruction(insn, 16, 5);
2109
2110  Inst.addOperand(MCOperand::createImm(Rt));
2111  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
2112
2113  switch (Inst.getOpcode()) {
2114  default:
2115    return Fail;
2116  case AArch64::PRFMroW:
2117    DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
2118    break;
2119  case AArch64::PRFMroX:
2120    DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
2121    break;
2122  }
2123
2124  DecodeMemExtend(Inst, (Extend << 1) | Shift, Addr, Decoder);
2125
2126  return Success;
2127}
2128