1//===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9#include "ARMBaseInstrInfo.h" 10#include "MCTargetDesc/ARMAddressingModes.h" 11#include "MCTargetDesc/ARMBaseInfo.h" 12#include "MCTargetDesc/ARMMCTargetDesc.h" 13#include "TargetInfo/ARMTargetInfo.h" 14#include "Utils/ARMBaseInfo.h" 15#include "llvm/MC/MCContext.h" 16#include "llvm/MC/MCDecoderOps.h" 17#include "llvm/MC/MCDisassembler/MCDisassembler.h" 18#include "llvm/MC/MCInst.h" 19#include "llvm/MC/MCInstrDesc.h" 20#include "llvm/MC/MCInstrInfo.h" 21#include "llvm/MC/MCSubtargetInfo.h" 22#include "llvm/MC/TargetRegistry.h" 23#include "llvm/Support/Compiler.h" 24#include "llvm/Support/ErrorHandling.h" 25#include "llvm/Support/MathExtras.h" 26#include "llvm/Support/raw_ostream.h" 27#include "llvm/TargetParser/SubtargetFeature.h" 28#include <algorithm> 29#include <cassert> 30#include <cstdint> 31#include <vector> 32 33using namespace llvm; 34 35#define DEBUG_TYPE "arm-disassembler" 36 37using DecodeStatus = MCDisassembler::DecodeStatus; 38 39namespace { 40 41 // Handles the condition code status of instructions in IT blocks 42 class ITStatus 43 { 44 public: 45 // Returns the condition code for instruction in IT block 46 unsigned getITCC() { 47 unsigned CC = ARMCC::AL; 48 if (instrInITBlock()) 49 CC = ITStates.back(); 50 return CC; 51 } 52 53 // Advances the IT block state to the next T or E 54 void advanceITState() { 55 ITStates.pop_back(); 56 } 57 58 // Returns true if the current instruction is in an IT block 59 bool instrInITBlock() { 60 return !ITStates.empty(); 61 } 62 63 // Returns true if current instruction is the last instruction in an IT block 64 bool instrLastInITBlock() { 65 return ITStates.size() == 1; 66 } 67 68 // Called when decoding an IT instruction. Sets the IT state for 69 // the following instructions that for the IT block. Firstcond 70 // corresponds to the field in the IT instruction encoding; Mask 71 // is in the MCOperand format in which 1 means 'else' and 0 'then'. 72 void setITState(char Firstcond, char Mask) { 73 // (3 - the number of trailing zeros) is the number of then / else. 74 unsigned NumTZ = llvm::countr_zero<uint8_t>(Mask); 75 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf); 76 assert(NumTZ <= 3 && "Invalid IT mask!"); 77 // push condition codes onto the stack the correct order for the pops 78 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 79 unsigned Else = (Mask >> Pos) & 1; 80 ITStates.push_back(CCBits ^ Else); 81 } 82 ITStates.push_back(CCBits); 83 } 84 85 private: 86 std::vector<unsigned char> ITStates; 87 }; 88 89 class VPTStatus 90 { 91 public: 92 unsigned getVPTPred() { 93 unsigned Pred = ARMVCC::None; 94 if (instrInVPTBlock()) 95 Pred = VPTStates.back(); 96 return Pred; 97 } 98 99 void advanceVPTState() { 100 VPTStates.pop_back(); 101 } 102 103 bool instrInVPTBlock() { 104 return !VPTStates.empty(); 105 } 106 107 bool instrLastInVPTBlock() { 108 return VPTStates.size() == 1; 109 } 110 111 void setVPTState(char Mask) { 112 // (3 - the number of trailing zeros) is the number of then / else. 113 unsigned NumTZ = llvm::countr_zero<uint8_t>(Mask); 114 assert(NumTZ <= 3 && "Invalid VPT mask!"); 115 // push predicates onto the stack the correct order for the pops 116 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 117 bool T = ((Mask >> Pos) & 1) == 0; 118 if (T) 119 VPTStates.push_back(ARMVCC::Then); 120 else 121 VPTStates.push_back(ARMVCC::Else); 122 } 123 VPTStates.push_back(ARMVCC::Then); 124 } 125 126 private: 127 SmallVector<unsigned char, 4> VPTStates; 128 }; 129 130/// ARM disassembler for all ARM platforms. 131class ARMDisassembler : public MCDisassembler { 132public: 133 std::unique_ptr<const MCInstrInfo> MCII; 134 135 ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, 136 const MCInstrInfo *MCII) 137 : MCDisassembler(STI, Ctx), MCII(MCII) { 138 InstructionEndianness = STI.hasFeature(ARM::ModeBigEndianInstructions) 139 ? llvm::endianness::big 140 : llvm::endianness::little; 141 } 142 143 ~ARMDisassembler() override = default; 144 145 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 146 ArrayRef<uint8_t> Bytes, uint64_t Address, 147 raw_ostream &CStream) const override; 148 149 uint64_t suggestBytesToSkip(ArrayRef<uint8_t> Bytes, 150 uint64_t Address) const override; 151 152private: 153 DecodeStatus getARMInstruction(MCInst &Instr, uint64_t &Size, 154 ArrayRef<uint8_t> Bytes, uint64_t Address, 155 raw_ostream &CStream) const; 156 157 DecodeStatus getThumbInstruction(MCInst &Instr, uint64_t &Size, 158 ArrayRef<uint8_t> Bytes, uint64_t Address, 159 raw_ostream &CStream) const; 160 161 mutable ITStatus ITBlock; 162 mutable VPTStatus VPTBlock; 163 164 void AddThumb1SBit(MCInst &MI, bool InITBlock) const; 165 bool isVectorPredicable(const MCInst &MI) const; 166 DecodeStatus AddThumbPredicate(MCInst&) const; 167 void UpdateThumbVFPPredicate(DecodeStatus &, MCInst&) const; 168 169 llvm::endianness InstructionEndianness; 170}; 171 172} // end anonymous namespace 173 174// Forward declare these because the autogenerated code will reference them. 175// Definitions are further down. 176static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 177 uint64_t Address, 178 const MCDisassembler *Decoder); 179static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, 180 uint64_t Address, 181 const MCDisassembler *Decoder); 182static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, 183 uint64_t Address, 184 const MCDisassembler *Decoder); 185static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, 186 uint64_t Address, 187 const MCDisassembler *Decoder); 188static DecodeStatus 189DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo, 190 uint64_t Address, 191 const MCDisassembler *Decoder); 192static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 193 uint64_t Address, 194 const MCDisassembler *Decoder); 195static DecodeStatus DecodeGPRnospRegisterClass(MCInst &Inst, unsigned RegNo, 196 uint64_t Address, 197 const MCDisassembler *Decoder); 198static DecodeStatus 199DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 200 const MCDisassembler *Decoder); 201static DecodeStatus DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo, 202 uint64_t Address, 203 const MCDisassembler *Decoder); 204static DecodeStatus 205DecodeGPRwithZRnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 206 const MCDisassembler *Decoder); 207static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 208 uint64_t Address, 209 const MCDisassembler *Decoder); 210static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 211 uint64_t Address, 212 const MCDisassembler *Decoder); 213static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 214 uint64_t Address, 215 const MCDisassembler *Decoder); 216static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 217 uint64_t Address, 218 const MCDisassembler *Decoder); 219static DecodeStatus 220DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 221 const MCDisassembler *Decoder); 222static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo, 223 uint64_t Address, 224 const MCDisassembler *Decoder); 225static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, 226 uint64_t Address, 227 const MCDisassembler *Decoder); 228static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 229 uint64_t Address, 230 const MCDisassembler *Decoder); 231static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 232 uint64_t Address, 233 const MCDisassembler *Decoder); 234static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 235 uint64_t Address, 236 const MCDisassembler *Decoder); 237static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 238 uint64_t Address, 239 const MCDisassembler *Decoder); 240static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 241 uint64_t Address, 242 const MCDisassembler *Decoder); 243static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 244 uint64_t Address, 245 const MCDisassembler *Decoder); 246static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, 247 uint64_t Address, 248 const MCDisassembler *Decoder); 249static DecodeStatus DecodeMQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 250 uint64_t Address, 251 const MCDisassembler *Decoder); 252static DecodeStatus DecodeMQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 253 uint64_t Address, 254 const MCDisassembler *Decoder); 255static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 256 uint64_t Address, 257 const MCDisassembler *Decoder); 258static DecodeStatus 259DecodeDPairSpacedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 260 const MCDisassembler *Decoder); 261 262static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 263 uint64_t Address, 264 const MCDisassembler *Decoder); 265static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 266 uint64_t Address, 267 const MCDisassembler *Decoder); 268static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 269 uint64_t Address, 270 const MCDisassembler *Decoder); 271static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 272 uint64_t Address, 273 const MCDisassembler *Decoder); 274static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 275 uint64_t Address, 276 const MCDisassembler *Decoder); 277 278static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 279 uint64_t Address, 280 const MCDisassembler *Decoder); 281static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 282 uint64_t Address, 283 const MCDisassembler *Decoder); 284static DecodeStatus 285DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 286 const MCDisassembler *Decoder); 287static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 288 uint64_t Address, 289 const MCDisassembler *Decoder); 290static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 291 uint64_t Address, 292 const MCDisassembler *Decoder); 293static DecodeStatus DecodeTSBInstruction(MCInst &Inst, unsigned Insn, 294 uint64_t Address, 295 const MCDisassembler *Decoder); 296static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 297 uint64_t Address, 298 const MCDisassembler *Decoder); 299static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 300 uint64_t Address, 301 const MCDisassembler *Decoder); 302 303static DecodeStatus 304DecodeMemMultipleWritebackInstruction(MCInst &Inst, unsigned Insn, 305 uint64_t Adddress, 306 const MCDisassembler *Decoder); 307static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 308 uint64_t Address, 309 const MCDisassembler *Decoder); 310static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 311 uint64_t Address, 312 const MCDisassembler *Decoder); 313static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 314 uint64_t Address, 315 const MCDisassembler *Decoder); 316static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 317 uint64_t Address, 318 const MCDisassembler *Decoder); 319static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 320 uint64_t Address, 321 const MCDisassembler *Decoder); 322static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 323 uint64_t Address, 324 const MCDisassembler *Decoder); 325static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 326 uint64_t Address, 327 const MCDisassembler *Decoder); 328static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 329 uint64_t Address, 330 const MCDisassembler *Decoder); 331static DecodeStatus DecodeT2HintSpaceInstruction(MCInst &Inst, unsigned Insn, 332 uint64_t Address, 333 const MCDisassembler *Decoder); 334static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 335 uint64_t Address, 336 const MCDisassembler *Decoder); 337static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 338 uint64_t Address, 339 const MCDisassembler *Decoder); 340static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 341 uint64_t Address, 342 const MCDisassembler *Decoder); 343static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 344 uint64_t Address, 345 const MCDisassembler *Decoder); 346static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 347 uint64_t Address, 348 const MCDisassembler *Decoder); 349static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 350 uint64_t Address, 351 const MCDisassembler *Decoder); 352static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 353 uint64_t Address, 354 const MCDisassembler *Decoder); 355static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val, 356 uint64_t Address, 357 const MCDisassembler *Decoder); 358static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val, 359 uint64_t Address, 360 const MCDisassembler *Decoder); 361static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val, 362 uint64_t Address, 363 const MCDisassembler *Decoder); 364static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val, 365 uint64_t Address, 366 const MCDisassembler *Decoder); 367static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 368 uint64_t Address, 369 const MCDisassembler *Decoder); 370static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 371 uint64_t Address, 372 const MCDisassembler *Decoder); 373static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 374 uint64_t Address, 375 const MCDisassembler *Decoder); 376static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 377 uint64_t Address, 378 const MCDisassembler *Decoder); 379static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 380 uint64_t Address, 381 const MCDisassembler *Decoder); 382static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 383 uint64_t Address, 384 const MCDisassembler *Decoder); 385static DecodeStatus DecodeVMOVModImmInstruction(MCInst &Inst, unsigned Val, 386 uint64_t Address, 387 const MCDisassembler *Decoder); 388static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst, unsigned Val, 389 uint64_t Address, 390 const MCDisassembler *Decoder); 391static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn, 392 uint64_t Address, 393 const MCDisassembler *Decoder); 394static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 395 uint64_t Address, 396 const MCDisassembler *Decoder); 397static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 398 uint64_t Address, 399 const MCDisassembler *Decoder); 400static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 401 uint64_t Address, 402 const MCDisassembler *Decoder); 403static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 404 uint64_t Address, 405 const MCDisassembler *Decoder); 406static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 407 uint64_t Address, 408 const MCDisassembler *Decoder); 409static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 410 uint64_t Address, 411 const MCDisassembler *Decoder); 412static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 413 uint64_t Address, 414 const MCDisassembler *Decoder); 415static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn, 416 uint64_t Address, 417 const MCDisassembler *Decoder); 418template <int shift> 419static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn, 420 uint64_t Address, 421 const MCDisassembler *Decoder); 422static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 423 uint64_t Address, 424 const MCDisassembler *Decoder); 425static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 426 uint64_t Address, 427 const MCDisassembler *Decoder); 428static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn, 429 uint64_t Address, 430 const MCDisassembler *Decoder); 431static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, uint64_t Address, 432 const MCDisassembler *Decoder); 433static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn, 434 uint64_t Address, 435 const MCDisassembler *Decoder); 436static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 437 uint64_t Address, 438 const MCDisassembler *Decoder); 439static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 440 uint64_t Address, 441 const MCDisassembler *Decoder); 442static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 443 uint64_t Address, 444 const MCDisassembler *Decoder); 445static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 446 uint64_t Address, 447 const MCDisassembler *Decoder); 448static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 449 uint64_t Address, 450 const MCDisassembler *Decoder); 451static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 452 uint64_t Address, 453 const MCDisassembler *Decoder); 454static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, uint64_t Address, 455 const MCDisassembler *Decoder); 456static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, uint64_t Address, 457 const MCDisassembler *Decoder); 458static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, uint64_t Address, 459 const MCDisassembler *Decoder); 460static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, uint64_t Address, 461 const MCDisassembler *Decoder); 462static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, uint64_t Address, 463 const MCDisassembler *Decoder); 464static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, uint64_t Address, 465 const MCDisassembler *Decoder); 466static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, uint64_t Address, 467 const MCDisassembler *Decoder); 468static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, uint64_t Address, 469 const MCDisassembler *Decoder); 470static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, uint64_t Address, 471 const MCDisassembler *Decoder); 472static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, uint64_t Address, 473 const MCDisassembler *Decoder); 474static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, uint64_t Address, 475 const MCDisassembler *Decoder); 476static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, uint64_t Address, 477 const MCDisassembler *Decoder); 478static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, uint64_t Address, 479 const MCDisassembler *Decoder); 480static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Insn, 481 uint64_t Address, 482 const MCDisassembler *Decoder); 483static DecodeStatus 484DecodeNEONComplexLane64Instruction(MCInst &Inst, unsigned Val, uint64_t Address, 485 const MCDisassembler *Decoder); 486 487static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 488 uint64_t Address, 489 const MCDisassembler *Decoder); 490static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 491 uint64_t Address, 492 const MCDisassembler *Decoder); 493static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 494 uint64_t Address, 495 const MCDisassembler *Decoder); 496static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 497 uint64_t Address, 498 const MCDisassembler *Decoder); 499static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 500 uint64_t Address, 501 const MCDisassembler *Decoder); 502static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 503 uint64_t Address, 504 const MCDisassembler *Decoder); 505static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 506 uint64_t Address, 507 const MCDisassembler *Decoder); 508static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 509 uint64_t Address, 510 const MCDisassembler *Decoder); 511static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 512 uint64_t Address, 513 const MCDisassembler *Decoder); 514static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 515 uint64_t Address, 516 const MCDisassembler *Decoder); 517static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 518 uint64_t Address, 519 const MCDisassembler *Decoder); 520static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 521 uint64_t Address, 522 const MCDisassembler *Decoder); 523static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, uint64_t Address, 524 const MCDisassembler *Decoder); 525static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 526 uint64_t Address, 527 const MCDisassembler *Decoder); 528static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, uint64_t Address, 529 const MCDisassembler *Decoder); 530static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address, 531 const MCDisassembler *Decoder); 532static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 533 uint64_t Address, 534 const MCDisassembler *Decoder); 535static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val, 536 uint64_t Address, 537 const MCDisassembler *Decoder); 538static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst, unsigned Val, 539 uint64_t Address, 540 const MCDisassembler *Decoder); 541static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, uint64_t Address, 542 const MCDisassembler *Decoder); 543template <int shift> 544static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, uint64_t Address, 545 const MCDisassembler *Decoder); 546static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 547 uint64_t Address, 548 const MCDisassembler *Decoder); 549template <int shift> 550static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val, 551 uint64_t Address, 552 const MCDisassembler *Decoder); 553template <int shift, int WriteBack> 554static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val, 555 uint64_t Address, 556 const MCDisassembler *Decoder); 557static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 558 uint64_t Address, 559 const MCDisassembler *Decoder); 560static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 561 uint64_t Address, 562 const MCDisassembler *Decoder); 563static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 564 uint64_t Address, 565 const MCDisassembler *Decoder); 566static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 567 uint64_t Address, 568 const MCDisassembler *Decoder); 569static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 570 uint64_t Address, 571 const MCDisassembler *Decoder); 572static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 573 uint64_t Address, 574 const MCDisassembler *Decoder); 575static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 576 uint64_t Address, 577 const MCDisassembler *Decoder); 578static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 579 uint64_t Address, 580 const MCDisassembler *Decoder); 581static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, uint64_t Address, 582 const MCDisassembler *Decoder); 583static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 584 uint64_t Address, 585 const MCDisassembler *Decoder); 586static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 587 uint64_t Address, 588 const MCDisassembler *Decoder); 589static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, uint64_t Address, 590 const MCDisassembler *Decoder); 591static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 592 uint64_t Address, 593 const MCDisassembler *Decoder); 594static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 595 uint64_t Address, 596 const MCDisassembler *Decoder); 597static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, uint64_t Address, 598 const MCDisassembler *Decoder); 599static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 600 uint64_t Address, 601 const MCDisassembler *Decoder); 602static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 603 uint64_t Address, 604 const MCDisassembler *Decoder); 605 606static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, uint64_t Address, 607 const MCDisassembler *Decoder); 608static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 609 uint64_t Address, 610 const MCDisassembler *Decoder); 611static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, 612 uint64_t Address, 613 const MCDisassembler *Decoder); 614 615template <bool isSigned, bool isNeg, bool zeroPermitted, int size> 616static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned val, 617 uint64_t Address, 618 const MCDisassembler *Decoder); 619static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned val, 620 uint64_t Address, 621 const MCDisassembler *Decoder); 622static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val, 623 uint64_t Address, 624 const MCDisassembler *Decoder); 625static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, 626 const MCDisassembler *Decoder); 627static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val, 628 uint64_t Address, 629 const MCDisassembler *Decoder); 630static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address, 631 const MCDisassembler *Decoder); 632static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val, 633 uint64_t Address, 634 const MCDisassembler *Decoder); 635static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned Val, 636 uint64_t Address, 637 const MCDisassembler *Decoder); 638static DecodeStatus DecodeVpredNOperand(MCInst &Inst, unsigned Val, 639 uint64_t Address, 640 const MCDisassembler *Decoder); 641static DecodeStatus 642DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, 643 const MCDisassembler *Decoder); 644static DecodeStatus 645DecodeRestrictedSPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, 646 const MCDisassembler *Decoder); 647static DecodeStatus 648DecodeRestrictedUPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, 649 const MCDisassembler *Decoder); 650static DecodeStatus 651DecodeRestrictedFPPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, 652 const MCDisassembler *Decoder); 653template <bool Writeback> 654static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Insn, 655 uint64_t Address, 656 const MCDisassembler *Decoder); 657template <int shift> 658static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val, 659 uint64_t Address, 660 const MCDisassembler *Decoder); 661template <int shift> 662static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val, 663 uint64_t Address, 664 const MCDisassembler *Decoder); 665template <int shift> 666static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val, 667 uint64_t Address, 668 const MCDisassembler *Decoder); 669template <unsigned MinLog, unsigned MaxLog> 670static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val, 671 uint64_t Address, 672 const MCDisassembler *Decoder); 673template <unsigned start> 674static DecodeStatus 675DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, uint64_t Address, 676 const MCDisassembler *Decoder); 677static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn, 678 uint64_t Address, 679 const MCDisassembler *Decoder); 680static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn, 681 uint64_t Address, 682 const MCDisassembler *Decoder); 683static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, 684 uint64_t Address, 685 const MCDisassembler *Decoder); 686typedef DecodeStatus OperandDecoder(MCInst &Inst, unsigned Val, 687 uint64_t Address, 688 const MCDisassembler *Decoder); 689template <bool scalar, OperandDecoder predicate_decoder> 690static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, uint64_t Address, 691 const MCDisassembler *Decoder); 692static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address, 693 const MCDisassembler *Decoder); 694static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn, 695 uint64_t Address, 696 const MCDisassembler *Decoder); 697static DecodeStatus 698DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn, uint64_t Address, 699 const MCDisassembler *Decoder); 700static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn, 701 uint64_t Address, 702 const MCDisassembler *Decoder); 703 704#include "ARMGenDisassemblerTables.inc" 705 706static MCDisassembler *createARMDisassembler(const Target &T, 707 const MCSubtargetInfo &STI, 708 MCContext &Ctx) { 709 return new ARMDisassembler(STI, Ctx, T.createMCInstrInfo()); 710} 711 712// Post-decoding checks 713static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size, 714 uint64_t Address, raw_ostream &CS, 715 uint32_t Insn, 716 DecodeStatus Result) { 717 switch (MI.getOpcode()) { 718 case ARM::HVC: { 719 // HVC is undefined if condition = 0xf otherwise upredictable 720 // if condition != 0xe 721 uint32_t Cond = (Insn >> 28) & 0xF; 722 if (Cond == 0xF) 723 return MCDisassembler::Fail; 724 if (Cond != 0xE) 725 return MCDisassembler::SoftFail; 726 return Result; 727 } 728 case ARM::t2ADDri: 729 case ARM::t2ADDri12: 730 case ARM::t2ADDrr: 731 case ARM::t2ADDrs: 732 case ARM::t2SUBri: 733 case ARM::t2SUBri12: 734 case ARM::t2SUBrr: 735 case ARM::t2SUBrs: 736 if (MI.getOperand(0).getReg() == ARM::SP && 737 MI.getOperand(1).getReg() != ARM::SP) 738 return MCDisassembler::SoftFail; 739 return Result; 740 default: return Result; 741 } 742} 743 744uint64_t ARMDisassembler::suggestBytesToSkip(ArrayRef<uint8_t> Bytes, 745 uint64_t Address) const { 746 // In Arm state, instructions are always 4 bytes wide, so there's no 747 // point in skipping any smaller number of bytes if an instruction 748 // can't be decoded. 749 if (!STI.hasFeature(ARM::ModeThumb)) 750 return 4; 751 752 // In a Thumb instruction stream, a halfword is a standalone 2-byte 753 // instruction if and only if its value is less than 0xE800. 754 // Otherwise, it's the first halfword of a 4-byte instruction. 755 // 756 // So, if we can see the upcoming halfword, we can judge on that 757 // basis, and maybe skip a whole 4-byte instruction that we don't 758 // know how to decode, without accidentally trying to interpret its 759 // second half as something else. 760 // 761 // If we don't have the instruction data available, we just have to 762 // recommend skipping the minimum sensible distance, which is 2 763 // bytes. 764 if (Bytes.size() < 2) 765 return 2; 766 767 uint16_t Insn16 = llvm::support::endian::read<uint16_t>( 768 Bytes.data(), InstructionEndianness); 769 return Insn16 < 0xE800 ? 2 : 4; 770} 771 772DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 773 ArrayRef<uint8_t> Bytes, 774 uint64_t Address, 775 raw_ostream &CS) const { 776 if (STI.hasFeature(ARM::ModeThumb)) 777 return getThumbInstruction(MI, Size, Bytes, Address, CS); 778 return getARMInstruction(MI, Size, Bytes, Address, CS); 779} 780 781DecodeStatus ARMDisassembler::getARMInstruction(MCInst &MI, uint64_t &Size, 782 ArrayRef<uint8_t> Bytes, 783 uint64_t Address, 784 raw_ostream &CS) const { 785 CommentStream = &CS; 786 787 assert(!STI.hasFeature(ARM::ModeThumb) && 788 "Asked to disassemble an ARM instruction but Subtarget is in Thumb " 789 "mode!"); 790 791 // We want to read exactly 4 bytes of data. 792 if (Bytes.size() < 4) { 793 Size = 0; 794 return MCDisassembler::Fail; 795 } 796 797 // Encoded as a 32-bit word in the stream. 798 uint32_t Insn = llvm::support::endian::read<uint32_t>(Bytes.data(), 799 InstructionEndianness); 800 801 // Calling the auto-generated decoder function. 802 DecodeStatus Result = 803 decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI); 804 if (Result != MCDisassembler::Fail) { 805 Size = 4; 806 return checkDecodedInstruction(MI, Size, Address, CS, Insn, Result); 807 } 808 809 struct DecodeTable { 810 const uint8_t *P; 811 bool DecodePred; 812 }; 813 814 const DecodeTable Tables[] = { 815 {DecoderTableVFP32, false}, {DecoderTableVFPV832, false}, 816 {DecoderTableNEONData32, true}, {DecoderTableNEONLoadStore32, true}, 817 {DecoderTableNEONDup32, true}, {DecoderTablev8NEON32, false}, 818 {DecoderTablev8Crypto32, false}, 819 }; 820 821 for (auto Table : Tables) { 822 Result = decodeInstruction(Table.P, MI, Insn, Address, this, STI); 823 if (Result != MCDisassembler::Fail) { 824 Size = 4; 825 // Add a fake predicate operand, because we share these instruction 826 // definitions with Thumb2 where these instructions are predicable. 827 if (Table.DecodePred && !DecodePredicateOperand(MI, 0xE, Address, this)) 828 return MCDisassembler::Fail; 829 return Result; 830 } 831 } 832 833 Result = 834 decodeInstruction(DecoderTableCoProc32, MI, Insn, Address, this, STI); 835 if (Result != MCDisassembler::Fail) { 836 Size = 4; 837 return checkDecodedInstruction(MI, Size, Address, CS, Insn, Result); 838 } 839 840 Size = 4; 841 return MCDisassembler::Fail; 842} 843 844/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 845/// immediate Value in the MCInst. The immediate Value has had any PC 846/// adjustment made by the caller. If the instruction is a branch instruction 847/// then isBranch is true, else false. If the getOpInfo() function was set as 848/// part of the setupForSymbolicDisassembly() call then that function is called 849/// to get any symbolic information at the Address for this instruction. If 850/// that returns non-zero then the symbolic information it returns is used to 851/// create an MCExpr and that is added as an operand to the MCInst. If 852/// getOpInfo() returns zero and isBranch is true then a symbol look up for 853/// Value is done and if a symbol is found an MCExpr is created with that, else 854/// an MCExpr with Value is created. This function returns true if it adds an 855/// operand to the MCInst and false otherwise. 856static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 857 bool isBranch, uint64_t InstSize, 858 MCInst &MI, 859 const MCDisassembler *Decoder) { 860 // FIXME: Does it make sense for value to be negative? 861 return Decoder->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, 862 isBranch, /*Offset=*/0, /*OpSize=*/0, 863 InstSize); 864} 865 866/// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 867/// referenced by a load instruction with the base register that is the Pc. 868/// These can often be values in a literal pool near the Address of the 869/// instruction. The Address of the instruction and its immediate Value are 870/// used as a possible literal pool entry. The SymbolLookUp call back will 871/// return the name of a symbol referenced by the literal pool's entry if 872/// the referenced address is that of a symbol. Or it will return a pointer to 873/// a literal 'C' string if the referenced address of the literal pool's entry 874/// is an address into a section with 'C' string literals. 875static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 876 const MCDisassembler *Decoder) { 877 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 878 Dis->tryAddingPcLoadReferenceComment(Value, Address); 879} 880 881// Thumb1 instructions don't have explicit S bits. Rather, they 882// implicitly set CPSR. Since it's not represented in the encoding, the 883// auto-generated decoder won't inject the CPSR operand. We need to fix 884// that as a post-pass. 885void ARMDisassembler::AddThumb1SBit(MCInst &MI, bool InITBlock) const { 886 const MCInstrDesc &MCID = MCII->get(MI.getOpcode()); 887 MCInst::iterator I = MI.begin(); 888 for (unsigned i = 0; i < MCID.NumOperands; ++i, ++I) { 889 if (I == MI.end()) break; 890 if (MCID.operands()[i].isOptionalDef() && 891 MCID.operands()[i].RegClass == ARM::CCRRegClassID) { 892 if (i > 0 && MCID.operands()[i - 1].isPredicate()) 893 continue; 894 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 895 return; 896 } 897 } 898 899 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); 900} 901 902bool ARMDisassembler::isVectorPredicable(const MCInst &MI) const { 903 const MCInstrDesc &MCID = MCII->get(MI.getOpcode()); 904 for (unsigned i = 0; i < MCID.NumOperands; ++i) { 905 if (ARM::isVpred(MCID.operands()[i].OperandType)) 906 return true; 907 } 908 return false; 909} 910 911// Most Thumb instructions don't have explicit predicates in the 912// encoding, but rather get their predicates from IT context. We need 913// to fix up the predicate operands using this context information as a 914// post-pass. 915MCDisassembler::DecodeStatus 916ARMDisassembler::AddThumbPredicate(MCInst &MI) const { 917 MCDisassembler::DecodeStatus S = Success; 918 919 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits(); 920 921 // A few instructions actually have predicates encoded in them. Don't 922 // try to overwrite it if we're seeing one of those. 923 switch (MI.getOpcode()) { 924 case ARM::tBcc: 925 case ARM::t2Bcc: 926 case ARM::tCBZ: 927 case ARM::tCBNZ: 928 case ARM::tCPS: 929 case ARM::t2CPS3p: 930 case ARM::t2CPS2p: 931 case ARM::t2CPS1p: 932 case ARM::t2CSEL: 933 case ARM::t2CSINC: 934 case ARM::t2CSINV: 935 case ARM::t2CSNEG: 936 case ARM::tMOVSr: 937 case ARM::tSETEND: 938 // Some instructions (mostly conditional branches) are not 939 // allowed in IT blocks. 940 if (ITBlock.instrInITBlock()) 941 S = SoftFail; 942 else 943 return Success; 944 break; 945 case ARM::t2HINT: 946 if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0) 947 S = SoftFail; 948 break; 949 case ARM::tB: 950 case ARM::t2B: 951 case ARM::t2TBB: 952 case ARM::t2TBH: 953 // Some instructions (mostly unconditional branches) can 954 // only appears at the end of, or outside of, an IT. 955 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) 956 S = SoftFail; 957 break; 958 default: 959 break; 960 } 961 962 // Warn on non-VPT predicable instruction in a VPT block and a VPT 963 // predicable instruction in an IT block 964 if ((!isVectorPredicable(MI) && VPTBlock.instrInVPTBlock()) || 965 (isVectorPredicable(MI) && ITBlock.instrInITBlock())) 966 S = SoftFail; 967 968 // If we're in an IT/VPT block, base the predicate on that. Otherwise, 969 // assume a predicate of AL. 970 unsigned CC = ARMCC::AL; 971 unsigned VCC = ARMVCC::None; 972 if (ITBlock.instrInITBlock()) { 973 CC = ITBlock.getITCC(); 974 ITBlock.advanceITState(); 975 } else if (VPTBlock.instrInVPTBlock()) { 976 VCC = VPTBlock.getVPTPred(); 977 VPTBlock.advanceVPTState(); 978 } 979 980 const MCInstrDesc &MCID = MCII->get(MI.getOpcode()); 981 982 MCInst::iterator CCI = MI.begin(); 983 for (unsigned i = 0; i < MCID.NumOperands; ++i, ++CCI) { 984 if (MCID.operands()[i].isPredicate() || CCI == MI.end()) 985 break; 986 } 987 988 if (MCID.isPredicable()) { 989 CCI = MI.insert(CCI, MCOperand::createImm(CC)); 990 ++CCI; 991 if (CC == ARMCC::AL) 992 MI.insert(CCI, MCOperand::createReg(0)); 993 else 994 MI.insert(CCI, MCOperand::createReg(ARM::CPSR)); 995 } else if (CC != ARMCC::AL) { 996 Check(S, SoftFail); 997 } 998 999 MCInst::iterator VCCI = MI.begin(); 1000 unsigned VCCPos; 1001 for (VCCPos = 0; VCCPos < MCID.NumOperands; ++VCCPos, ++VCCI) { 1002 if (ARM::isVpred(MCID.operands()[VCCPos].OperandType) || VCCI == MI.end()) 1003 break; 1004 } 1005 1006 if (isVectorPredicable(MI)) { 1007 VCCI = MI.insert(VCCI, MCOperand::createImm(VCC)); 1008 ++VCCI; 1009 if (VCC == ARMVCC::None) 1010 VCCI = MI.insert(VCCI, MCOperand::createReg(0)); 1011 else 1012 VCCI = MI.insert(VCCI, MCOperand::createReg(ARM::P0)); 1013 ++VCCI; 1014 VCCI = MI.insert(VCCI, MCOperand::createReg(0)); 1015 ++VCCI; 1016 if (MCID.operands()[VCCPos].OperandType == ARM::OPERAND_VPRED_R) { 1017 int TiedOp = MCID.getOperandConstraint(VCCPos + 3, MCOI::TIED_TO); 1018 assert(TiedOp >= 0 && 1019 "Inactive register in vpred_r is not tied to an output!"); 1020 // Copy the operand to ensure it's not invalidated when MI grows. 1021 MI.insert(VCCI, MCOperand(MI.getOperand(TiedOp))); 1022 } 1023 } else if (VCC != ARMVCC::None) { 1024 Check(S, SoftFail); 1025 } 1026 1027 return S; 1028} 1029 1030// Thumb VFP instructions are a special case. Because we share their 1031// encodings between ARM and Thumb modes, and they are predicable in ARM 1032// mode, the auto-generated decoder will give them an (incorrect) 1033// predicate operand. We need to rewrite these operands based on the IT 1034// context as a post-pass. 1035void ARMDisassembler::UpdateThumbVFPPredicate( 1036 DecodeStatus &S, MCInst &MI) const { 1037 unsigned CC; 1038 CC = ITBlock.getITCC(); 1039 if (CC == 0xF) 1040 CC = ARMCC::AL; 1041 if (ITBlock.instrInITBlock()) 1042 ITBlock.advanceITState(); 1043 else if (VPTBlock.instrInVPTBlock()) { 1044 CC = VPTBlock.getVPTPred(); 1045 VPTBlock.advanceVPTState(); 1046 } 1047 1048 const MCInstrDesc &MCID = MCII->get(MI.getOpcode()); 1049 ArrayRef<MCOperandInfo> OpInfo = MCID.operands(); 1050 MCInst::iterator I = MI.begin(); 1051 unsigned short NumOps = MCID.NumOperands; 1052 for (unsigned i = 0; i < NumOps; ++i, ++I) { 1053 if (OpInfo[i].isPredicate() ) { 1054 if (CC != ARMCC::AL && !MCID.isPredicable()) 1055 Check(S, SoftFail); 1056 I->setImm(CC); 1057 ++I; 1058 if (CC == ARMCC::AL) 1059 I->setReg(0); 1060 else 1061 I->setReg(ARM::CPSR); 1062 return; 1063 } 1064 } 1065} 1066 1067DecodeStatus ARMDisassembler::getThumbInstruction(MCInst &MI, uint64_t &Size, 1068 ArrayRef<uint8_t> Bytes, 1069 uint64_t Address, 1070 raw_ostream &CS) const { 1071 CommentStream = &CS; 1072 1073 assert(STI.hasFeature(ARM::ModeThumb) && 1074 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 1075 1076 // We want to read exactly 2 bytes of data. 1077 if (Bytes.size() < 2) { 1078 Size = 0; 1079 return MCDisassembler::Fail; 1080 } 1081 1082 uint16_t Insn16 = llvm::support::endian::read<uint16_t>( 1083 Bytes.data(), InstructionEndianness); 1084 DecodeStatus Result = 1085 decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI); 1086 if (Result != MCDisassembler::Fail) { 1087 Size = 2; 1088 Check(Result, AddThumbPredicate(MI)); 1089 return Result; 1090 } 1091 1092 Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this, 1093 STI); 1094 if (Result) { 1095 Size = 2; 1096 bool InITBlock = ITBlock.instrInITBlock(); 1097 Check(Result, AddThumbPredicate(MI)); 1098 AddThumb1SBit(MI, InITBlock); 1099 return Result; 1100 } 1101 1102 Result = 1103 decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI); 1104 if (Result != MCDisassembler::Fail) { 1105 Size = 2; 1106 1107 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 1108 // the Thumb predicate. 1109 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) 1110 Result = MCDisassembler::SoftFail; 1111 1112 Check(Result, AddThumbPredicate(MI)); 1113 1114 // If we find an IT instruction, we need to parse its condition 1115 // code and mask operands so that we can apply them correctly 1116 // to the subsequent instructions. 1117 if (MI.getOpcode() == ARM::t2IT) { 1118 unsigned Firstcond = MI.getOperand(0).getImm(); 1119 unsigned Mask = MI.getOperand(1).getImm(); 1120 ITBlock.setITState(Firstcond, Mask); 1121 1122 // An IT instruction that would give a 'NV' predicate is unpredictable. 1123 if (Firstcond == ARMCC::AL && !isPowerOf2_32(Mask)) 1124 CS << "unpredictable IT predicate sequence"; 1125 } 1126 1127 return Result; 1128 } 1129 1130 // We want to read exactly 4 bytes of data. 1131 if (Bytes.size() < 4) { 1132 Size = 0; 1133 return MCDisassembler::Fail; 1134 } 1135 1136 uint32_t Insn32 = 1137 (uint32_t(Insn16) << 16) | llvm::support::endian::read<uint16_t>( 1138 Bytes.data() + 2, InstructionEndianness); 1139 1140 Result = 1141 decodeInstruction(DecoderTableMVE32, MI, Insn32, Address, this, STI); 1142 if (Result != MCDisassembler::Fail) { 1143 Size = 4; 1144 1145 // Nested VPT blocks are UNPREDICTABLE. Must be checked before we add 1146 // the VPT predicate. 1147 if (isVPTOpcode(MI.getOpcode()) && VPTBlock.instrInVPTBlock()) 1148 Result = MCDisassembler::SoftFail; 1149 1150 Check(Result, AddThumbPredicate(MI)); 1151 1152 if (isVPTOpcode(MI.getOpcode())) { 1153 unsigned Mask = MI.getOperand(0).getImm(); 1154 VPTBlock.setVPTState(Mask); 1155 } 1156 1157 return Result; 1158 } 1159 1160 Result = 1161 decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI); 1162 if (Result != MCDisassembler::Fail) { 1163 Size = 4; 1164 bool InITBlock = ITBlock.instrInITBlock(); 1165 Check(Result, AddThumbPredicate(MI)); 1166 AddThumb1SBit(MI, InITBlock); 1167 return Result; 1168 } 1169 1170 Result = 1171 decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI); 1172 if (Result != MCDisassembler::Fail) { 1173 Size = 4; 1174 Check(Result, AddThumbPredicate(MI)); 1175 return checkDecodedInstruction(MI, Size, Address, CS, Insn32, Result); 1176 } 1177 1178 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 1179 Result = 1180 decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI); 1181 if (Result != MCDisassembler::Fail) { 1182 Size = 4; 1183 UpdateThumbVFPPredicate(Result, MI); 1184 return Result; 1185 } 1186 } 1187 1188 Result = 1189 decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI); 1190 if (Result != MCDisassembler::Fail) { 1191 Size = 4; 1192 return Result; 1193 } 1194 1195 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 1196 Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this, 1197 STI); 1198 if (Result != MCDisassembler::Fail) { 1199 Size = 4; 1200 Check(Result, AddThumbPredicate(MI)); 1201 return Result; 1202 } 1203 } 1204 1205 if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) { 1206 uint32_t NEONLdStInsn = Insn32; 1207 NEONLdStInsn &= 0xF0FFFFFF; 1208 NEONLdStInsn |= 0x04000000; 1209 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, 1210 Address, this, STI); 1211 if (Result != MCDisassembler::Fail) { 1212 Size = 4; 1213 Check(Result, AddThumbPredicate(MI)); 1214 return Result; 1215 } 1216 } 1217 1218 if (fieldFromInstruction(Insn32, 24, 4) == 0xF) { 1219 uint32_t NEONDataInsn = Insn32; 1220 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 1221 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 1222 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 1223 Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn, 1224 Address, this, STI); 1225 if (Result != MCDisassembler::Fail) { 1226 Size = 4; 1227 Check(Result, AddThumbPredicate(MI)); 1228 return Result; 1229 } 1230 1231 uint32_t NEONCryptoInsn = Insn32; 1232 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24 1233 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 1234 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25 1235 Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn, 1236 Address, this, STI); 1237 if (Result != MCDisassembler::Fail) { 1238 Size = 4; 1239 return Result; 1240 } 1241 1242 uint32_t NEONv8Insn = Insn32; 1243 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26 1244 Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address, 1245 this, STI); 1246 if (Result != MCDisassembler::Fail) { 1247 Size = 4; 1248 return Result; 1249 } 1250 } 1251 1252 uint32_t Coproc = fieldFromInstruction(Insn32, 8, 4); 1253 const uint8_t *DecoderTable = ARM::isCDECoproc(Coproc, STI) 1254 ? DecoderTableThumb2CDE32 1255 : DecoderTableThumb2CoProc32; 1256 Result = 1257 decodeInstruction(DecoderTable, MI, Insn32, Address, this, STI); 1258 if (Result != MCDisassembler::Fail) { 1259 Size = 4; 1260 Check(Result, AddThumbPredicate(MI)); 1261 return Result; 1262 } 1263 1264 Size = 0; 1265 return MCDisassembler::Fail; 1266} 1267 1268extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMDisassembler() { 1269 TargetRegistry::RegisterMCDisassembler(getTheARMLETarget(), 1270 createARMDisassembler); 1271 TargetRegistry::RegisterMCDisassembler(getTheARMBETarget(), 1272 createARMDisassembler); 1273 TargetRegistry::RegisterMCDisassembler(getTheThumbLETarget(), 1274 createARMDisassembler); 1275 TargetRegistry::RegisterMCDisassembler(getTheThumbBETarget(), 1276 createARMDisassembler); 1277} 1278 1279static const uint16_t GPRDecoderTable[] = { 1280 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 1281 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 1282 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 1283 ARM::R12, ARM::SP, ARM::LR, ARM::PC 1284}; 1285 1286static const uint16_t CLRMGPRDecoderTable[] = { 1287 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 1288 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 1289 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 1290 ARM::R12, 0, ARM::LR, ARM::APSR 1291}; 1292 1293static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1294 uint64_t Address, 1295 const MCDisassembler *Decoder) { 1296 if (RegNo > 15) 1297 return MCDisassembler::Fail; 1298 1299 unsigned Register = GPRDecoderTable[RegNo]; 1300 Inst.addOperand(MCOperand::createReg(Register)); 1301 return MCDisassembler::Success; 1302} 1303 1304static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1305 uint64_t Address, 1306 const MCDisassembler *Decoder) { 1307 if (RegNo > 15) 1308 return MCDisassembler::Fail; 1309 1310 unsigned Register = CLRMGPRDecoderTable[RegNo]; 1311 if (Register == 0) 1312 return MCDisassembler::Fail; 1313 1314 Inst.addOperand(MCOperand::createReg(Register)); 1315 return MCDisassembler::Success; 1316} 1317 1318static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 1319 uint64_t Address, 1320 const MCDisassembler *Decoder) { 1321 DecodeStatus S = MCDisassembler::Success; 1322 1323 if (RegNo == 15) 1324 S = MCDisassembler::SoftFail; 1325 1326 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1327 1328 return S; 1329} 1330 1331static DecodeStatus DecodeGPRnospRegisterClass(MCInst &Inst, unsigned RegNo, 1332 uint64_t Address, 1333 const MCDisassembler *Decoder) { 1334 DecodeStatus S = MCDisassembler::Success; 1335 1336 if (RegNo == 13) 1337 S = MCDisassembler::SoftFail; 1338 1339 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1340 1341 return S; 1342} 1343 1344static DecodeStatus 1345DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 1346 const MCDisassembler *Decoder) { 1347 DecodeStatus S = MCDisassembler::Success; 1348 1349 if (RegNo == 15) 1350 { 1351 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); 1352 return MCDisassembler::Success; 1353 } 1354 1355 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1356 return S; 1357} 1358 1359static DecodeStatus 1360DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 1361 const MCDisassembler *Decoder) { 1362 DecodeStatus S = MCDisassembler::Success; 1363 1364 if (RegNo == 15) 1365 { 1366 Inst.addOperand(MCOperand::createReg(ARM::ZR)); 1367 return MCDisassembler::Success; 1368 } 1369 1370 if (RegNo == 13) 1371 Check(S, MCDisassembler::SoftFail); 1372 1373 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1374 return S; 1375} 1376 1377static DecodeStatus 1378DecodeGPRwithZRnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 1379 const MCDisassembler *Decoder) { 1380 DecodeStatus S = MCDisassembler::Success; 1381 if (RegNo == 13) 1382 return MCDisassembler::Fail; 1383 Check(S, DecodeGPRwithZRRegisterClass(Inst, RegNo, Address, Decoder)); 1384 return S; 1385} 1386 1387static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1388 uint64_t Address, 1389 const MCDisassembler *Decoder) { 1390 if (RegNo > 7) 1391 return MCDisassembler::Fail; 1392 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 1393} 1394 1395static const uint16_t GPRPairDecoderTable[] = { 1396 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, 1397 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP 1398}; 1399 1400static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 1401 uint64_t Address, 1402 const MCDisassembler *Decoder) { 1403 DecodeStatus S = MCDisassembler::Success; 1404 1405 // According to the Arm ARM RegNo = 14 is undefined, but we return fail 1406 // rather than SoftFail as there is no GPRPair table entry for index 7. 1407 if (RegNo > 13) 1408 return MCDisassembler::Fail; 1409 1410 if (RegNo & 1) 1411 S = MCDisassembler::SoftFail; 1412 1413 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; 1414 Inst.addOperand(MCOperand::createReg(RegisterPair)); 1415 return S; 1416} 1417 1418static DecodeStatus 1419DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 1420 const MCDisassembler *Decoder) { 1421 if (RegNo > 13) 1422 return MCDisassembler::Fail; 1423 1424 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; 1425 Inst.addOperand(MCOperand::createReg(RegisterPair)); 1426 1427 if ((RegNo & 1) || RegNo > 10) 1428 return MCDisassembler::SoftFail; 1429 return MCDisassembler::Success; 1430} 1431 1432static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo, 1433 uint64_t Address, 1434 const MCDisassembler *Decoder) { 1435 if (RegNo != 13) 1436 return MCDisassembler::Fail; 1437 1438 unsigned Register = GPRDecoderTable[RegNo]; 1439 Inst.addOperand(MCOperand::createReg(Register)); 1440 return MCDisassembler::Success; 1441} 1442 1443static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1444 uint64_t Address, 1445 const MCDisassembler *Decoder) { 1446 unsigned Register = 0; 1447 switch (RegNo) { 1448 case 0: 1449 Register = ARM::R0; 1450 break; 1451 case 1: 1452 Register = ARM::R1; 1453 break; 1454 case 2: 1455 Register = ARM::R2; 1456 break; 1457 case 3: 1458 Register = ARM::R3; 1459 break; 1460 case 9: 1461 Register = ARM::R9; 1462 break; 1463 case 12: 1464 Register = ARM::R12; 1465 break; 1466 default: 1467 return MCDisassembler::Fail; 1468 } 1469 1470 Inst.addOperand(MCOperand::createReg(Register)); 1471 return MCDisassembler::Success; 1472} 1473 1474static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 1475 uint64_t Address, 1476 const MCDisassembler *Decoder) { 1477 DecodeStatus S = MCDisassembler::Success; 1478 1479 const FeatureBitset &featureBits = 1480 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1481 1482 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15) 1483 S = MCDisassembler::SoftFail; 1484 1485 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 1486 return S; 1487} 1488 1489static const uint16_t SPRDecoderTable[] = { 1490 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 1491 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 1492 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 1493 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 1494 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 1495 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 1496 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 1497 ARM::S28, ARM::S29, ARM::S30, ARM::S31 1498}; 1499 1500static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 1501 uint64_t Address, 1502 const MCDisassembler *Decoder) { 1503 if (RegNo > 31) 1504 return MCDisassembler::Fail; 1505 1506 unsigned Register = SPRDecoderTable[RegNo]; 1507 Inst.addOperand(MCOperand::createReg(Register)); 1508 return MCDisassembler::Success; 1509} 1510 1511static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo, 1512 uint64_t Address, 1513 const MCDisassembler *Decoder) { 1514 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); 1515} 1516 1517static const uint16_t DPRDecoderTable[] = { 1518 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 1519 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 1520 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 1521 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 1522 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 1523 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 1524 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 1525 ARM::D28, ARM::D29, ARM::D30, ARM::D31 1526}; 1527 1528static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 1529 uint64_t Address, 1530 const MCDisassembler *Decoder) { 1531 const FeatureBitset &featureBits = 1532 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1533 1534 bool hasD32 = featureBits[ARM::FeatureD32]; 1535 1536 if (RegNo > 31 || (!hasD32 && RegNo > 15)) 1537 return MCDisassembler::Fail; 1538 1539 unsigned Register = DPRDecoderTable[RegNo]; 1540 Inst.addOperand(MCOperand::createReg(Register)); 1541 return MCDisassembler::Success; 1542} 1543 1544static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1545 uint64_t Address, 1546 const MCDisassembler *Decoder) { 1547 if (RegNo > 7) 1548 return MCDisassembler::Fail; 1549 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1550} 1551 1552static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1553 uint64_t Address, 1554 const MCDisassembler *Decoder) { 1555 if (RegNo > 15) 1556 return MCDisassembler::Fail; 1557 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder); 1558} 1559 1560static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 1561 uint64_t Address, 1562 const MCDisassembler *Decoder) { 1563 if (RegNo > 15) 1564 return MCDisassembler::Fail; 1565 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1566} 1567 1568static const uint16_t QPRDecoderTable[] = { 1569 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 1570 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 1571 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 1572 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 1573}; 1574 1575static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 1576 uint64_t Address, 1577 const MCDisassembler *Decoder) { 1578 if (RegNo > 31 || (RegNo & 1) != 0) 1579 return MCDisassembler::Fail; 1580 RegNo >>= 1; 1581 1582 unsigned Register = QPRDecoderTable[RegNo]; 1583 Inst.addOperand(MCOperand::createReg(Register)); 1584 return MCDisassembler::Success; 1585} 1586 1587static const uint16_t DPairDecoderTable[] = { 1588 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 1589 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 1590 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 1591 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 1592 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 1593 ARM::Q15 1594}; 1595 1596static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 1597 uint64_t Address, 1598 const MCDisassembler *Decoder) { 1599 if (RegNo > 30) 1600 return MCDisassembler::Fail; 1601 1602 unsigned Register = DPairDecoderTable[RegNo]; 1603 Inst.addOperand(MCOperand::createReg(Register)); 1604 return MCDisassembler::Success; 1605} 1606 1607static const uint16_t DPairSpacedDecoderTable[] = { 1608 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1609 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1610 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1611 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1612 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1613 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1614 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1615 ARM::D28_D30, ARM::D29_D31 1616}; 1617 1618static DecodeStatus 1619DecodeDPairSpacedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, 1620 const MCDisassembler *Decoder) { 1621 if (RegNo > 29) 1622 return MCDisassembler::Fail; 1623 1624 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1625 Inst.addOperand(MCOperand::createReg(Register)); 1626 return MCDisassembler::Success; 1627} 1628 1629static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1630 uint64_t Address, 1631 const MCDisassembler *Decoder) { 1632 DecodeStatus S = MCDisassembler::Success; 1633 if (Val == 0xF) return MCDisassembler::Fail; 1634 // AL predicate is not allowed on Thumb1 branches. 1635 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1636 return MCDisassembler::Fail; 1637 const MCInstrInfo *MCII = 1638 static_cast<const ARMDisassembler *>(Decoder)->MCII.get(); 1639 if (Val != ARMCC::AL && !MCII->get(Inst.getOpcode()).isPredicable()) 1640 Check(S, MCDisassembler::SoftFail); 1641 Inst.addOperand(MCOperand::createImm(Val)); 1642 if (Val == ARMCC::AL) { 1643 Inst.addOperand(MCOperand::createReg(0)); 1644 } else 1645 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1646 return S; 1647} 1648 1649static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1650 uint64_t Address, 1651 const MCDisassembler *Decoder) { 1652 if (Val) 1653 Inst.addOperand(MCOperand::createReg(ARM::CPSR)); 1654 else 1655 Inst.addOperand(MCOperand::createReg(0)); 1656 return MCDisassembler::Success; 1657} 1658 1659static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 1660 uint64_t Address, 1661 const MCDisassembler *Decoder) { 1662 DecodeStatus S = MCDisassembler::Success; 1663 1664 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1665 unsigned type = fieldFromInstruction(Val, 5, 2); 1666 unsigned imm = fieldFromInstruction(Val, 7, 5); 1667 1668 // Register-immediate 1669 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 1670 return MCDisassembler::Fail; 1671 1672 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1673 switch (type) { 1674 case 0: 1675 Shift = ARM_AM::lsl; 1676 break; 1677 case 1: 1678 Shift = ARM_AM::lsr; 1679 break; 1680 case 2: 1681 Shift = ARM_AM::asr; 1682 break; 1683 case 3: 1684 Shift = ARM_AM::ror; 1685 break; 1686 } 1687 1688 if (Shift == ARM_AM::ror && imm == 0) 1689 Shift = ARM_AM::rrx; 1690 1691 unsigned Op = Shift | (imm << 3); 1692 Inst.addOperand(MCOperand::createImm(Op)); 1693 1694 return S; 1695} 1696 1697static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 1698 uint64_t Address, 1699 const MCDisassembler *Decoder) { 1700 DecodeStatus S = MCDisassembler::Success; 1701 1702 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1703 unsigned type = fieldFromInstruction(Val, 5, 2); 1704 unsigned Rs = fieldFromInstruction(Val, 8, 4); 1705 1706 // Register-register 1707 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1708 return MCDisassembler::Fail; 1709 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1710 return MCDisassembler::Fail; 1711 1712 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1713 switch (type) { 1714 case 0: 1715 Shift = ARM_AM::lsl; 1716 break; 1717 case 1: 1718 Shift = ARM_AM::lsr; 1719 break; 1720 case 2: 1721 Shift = ARM_AM::asr; 1722 break; 1723 case 3: 1724 Shift = ARM_AM::ror; 1725 break; 1726 } 1727 1728 Inst.addOperand(MCOperand::createImm(Shift)); 1729 1730 return S; 1731} 1732 1733static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1734 uint64_t Address, 1735 const MCDisassembler *Decoder) { 1736 DecodeStatus S = MCDisassembler::Success; 1737 1738 bool NeedDisjointWriteback = false; 1739 unsigned WritebackReg = 0; 1740 bool CLRM = false; 1741 switch (Inst.getOpcode()) { 1742 default: 1743 break; 1744 case ARM::LDMIA_UPD: 1745 case ARM::LDMDB_UPD: 1746 case ARM::LDMIB_UPD: 1747 case ARM::LDMDA_UPD: 1748 case ARM::t2LDMIA_UPD: 1749 case ARM::t2LDMDB_UPD: 1750 case ARM::t2STMIA_UPD: 1751 case ARM::t2STMDB_UPD: 1752 NeedDisjointWriteback = true; 1753 WritebackReg = Inst.getOperand(0).getReg(); 1754 break; 1755 case ARM::t2CLRM: 1756 CLRM = true; 1757 break; 1758 } 1759 1760 // Empty register lists are not allowed. 1761 if (Val == 0) return MCDisassembler::Fail; 1762 for (unsigned i = 0; i < 16; ++i) { 1763 if (Val & (1 << i)) { 1764 if (CLRM) { 1765 if (!Check(S, DecodeCLRMGPRRegisterClass(Inst, i, Address, Decoder))) { 1766 return MCDisassembler::Fail; 1767 } 1768 } else { 1769 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1770 return MCDisassembler::Fail; 1771 // Writeback not allowed if Rn is in the target list. 1772 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg()) 1773 Check(S, MCDisassembler::SoftFail); 1774 } 1775 } 1776 } 1777 1778 return S; 1779} 1780 1781static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1782 uint64_t Address, 1783 const MCDisassembler *Decoder) { 1784 DecodeStatus S = MCDisassembler::Success; 1785 1786 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1787 unsigned regs = fieldFromInstruction(Val, 0, 8); 1788 1789 // In case of unpredictable encoding, tweak the operands. 1790 if (regs == 0 || (Vd + regs) > 32) { 1791 regs = Vd + regs > 32 ? 32 - Vd : regs; 1792 regs = std::max( 1u, regs); 1793 S = MCDisassembler::SoftFail; 1794 } 1795 1796 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1797 return MCDisassembler::Fail; 1798 for (unsigned i = 0; i < (regs - 1); ++i) { 1799 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1800 return MCDisassembler::Fail; 1801 } 1802 1803 return S; 1804} 1805 1806static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 1807 uint64_t Address, 1808 const MCDisassembler *Decoder) { 1809 DecodeStatus S = MCDisassembler::Success; 1810 1811 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1812 unsigned regs = fieldFromInstruction(Val, 1, 7); 1813 1814 // In case of unpredictable encoding, tweak the operands. 1815 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { 1816 regs = Vd + regs > 32 ? 32 - Vd : regs; 1817 regs = std::max( 1u, regs); 1818 regs = std::min(16u, regs); 1819 S = MCDisassembler::SoftFail; 1820 } 1821 1822 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1823 return MCDisassembler::Fail; 1824 for (unsigned i = 0; i < (regs - 1); ++i) { 1825 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1826 return MCDisassembler::Fail; 1827 } 1828 1829 return S; 1830} 1831 1832static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 1833 uint64_t Address, 1834 const MCDisassembler *Decoder) { 1835 // This operand encodes a mask of contiguous zeros between a specified MSB 1836 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1837 // the mask of all bits LSB-and-lower, and then xor them to create 1838 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1839 // create the final mask. 1840 unsigned msb = fieldFromInstruction(Val, 5, 5); 1841 unsigned lsb = fieldFromInstruction(Val, 0, 5); 1842 1843 DecodeStatus S = MCDisassembler::Success; 1844 if (lsb > msb) { 1845 Check(S, MCDisassembler::SoftFail); 1846 // The check above will cause the warning for the "potentially undefined 1847 // instruction encoding" but we can't build a bad MCOperand value here 1848 // with a lsb > msb or else printing the MCInst will cause a crash. 1849 lsb = msb; 1850 } 1851 1852 uint32_t msb_mask = 0xFFFFFFFF; 1853 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1854 uint32_t lsb_mask = (1U << lsb) - 1; 1855 1856 Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask))); 1857 return S; 1858} 1859 1860static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 1861 uint64_t Address, 1862 const MCDisassembler *Decoder) { 1863 DecodeStatus S = MCDisassembler::Success; 1864 1865 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1866 unsigned CRd = fieldFromInstruction(Insn, 12, 4); 1867 unsigned coproc = fieldFromInstruction(Insn, 8, 4); 1868 unsigned imm = fieldFromInstruction(Insn, 0, 8); 1869 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1870 unsigned U = fieldFromInstruction(Insn, 23, 1); 1871 const FeatureBitset &featureBits = 1872 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 1873 1874 switch (Inst.getOpcode()) { 1875 case ARM::LDC_OFFSET: 1876 case ARM::LDC_PRE: 1877 case ARM::LDC_POST: 1878 case ARM::LDC_OPTION: 1879 case ARM::LDCL_OFFSET: 1880 case ARM::LDCL_PRE: 1881 case ARM::LDCL_POST: 1882 case ARM::LDCL_OPTION: 1883 case ARM::STC_OFFSET: 1884 case ARM::STC_PRE: 1885 case ARM::STC_POST: 1886 case ARM::STC_OPTION: 1887 case ARM::STCL_OFFSET: 1888 case ARM::STCL_PRE: 1889 case ARM::STCL_POST: 1890 case ARM::STCL_OPTION: 1891 case ARM::t2LDC_OFFSET: 1892 case ARM::t2LDC_PRE: 1893 case ARM::t2LDC_POST: 1894 case ARM::t2LDC_OPTION: 1895 case ARM::t2LDCL_OFFSET: 1896 case ARM::t2LDCL_PRE: 1897 case ARM::t2LDCL_POST: 1898 case ARM::t2LDCL_OPTION: 1899 case ARM::t2STC_OFFSET: 1900 case ARM::t2STC_PRE: 1901 case ARM::t2STC_POST: 1902 case ARM::t2STC_OPTION: 1903 case ARM::t2STCL_OFFSET: 1904 case ARM::t2STCL_PRE: 1905 case ARM::t2STCL_POST: 1906 case ARM::t2STCL_OPTION: 1907 case ARM::t2LDC2_OFFSET: 1908 case ARM::t2LDC2L_OFFSET: 1909 case ARM::t2LDC2_PRE: 1910 case ARM::t2LDC2L_PRE: 1911 case ARM::t2STC2_OFFSET: 1912 case ARM::t2STC2L_OFFSET: 1913 case ARM::t2STC2_PRE: 1914 case ARM::t2STC2L_PRE: 1915 case ARM::LDC2_OFFSET: 1916 case ARM::LDC2L_OFFSET: 1917 case ARM::LDC2_PRE: 1918 case ARM::LDC2L_PRE: 1919 case ARM::STC2_OFFSET: 1920 case ARM::STC2L_OFFSET: 1921 case ARM::STC2_PRE: 1922 case ARM::STC2L_PRE: 1923 case ARM::t2LDC2_OPTION: 1924 case ARM::t2STC2_OPTION: 1925 case ARM::t2LDC2_POST: 1926 case ARM::t2LDC2L_POST: 1927 case ARM::t2STC2_POST: 1928 case ARM::t2STC2L_POST: 1929 case ARM::LDC2_POST: 1930 case ARM::LDC2L_POST: 1931 case ARM::STC2_POST: 1932 case ARM::STC2L_POST: 1933 if (coproc == 0xA || coproc == 0xB || 1934 (featureBits[ARM::HasV8_1MMainlineOps] && 1935 (coproc == 0x8 || coproc == 0x9 || coproc == 0xA || coproc == 0xB || 1936 coproc == 0xE || coproc == 0xF))) 1937 return MCDisassembler::Fail; 1938 break; 1939 default: 1940 break; 1941 } 1942 1943 if (featureBits[ARM::HasV8Ops] && (coproc != 14)) 1944 return MCDisassembler::Fail; 1945 1946 Inst.addOperand(MCOperand::createImm(coproc)); 1947 Inst.addOperand(MCOperand::createImm(CRd)); 1948 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1949 return MCDisassembler::Fail; 1950 1951 switch (Inst.getOpcode()) { 1952 case ARM::t2LDC2_OFFSET: 1953 case ARM::t2LDC2L_OFFSET: 1954 case ARM::t2LDC2_PRE: 1955 case ARM::t2LDC2L_PRE: 1956 case ARM::t2STC2_OFFSET: 1957 case ARM::t2STC2L_OFFSET: 1958 case ARM::t2STC2_PRE: 1959 case ARM::t2STC2L_PRE: 1960 case ARM::LDC2_OFFSET: 1961 case ARM::LDC2L_OFFSET: 1962 case ARM::LDC2_PRE: 1963 case ARM::LDC2L_PRE: 1964 case ARM::STC2_OFFSET: 1965 case ARM::STC2L_OFFSET: 1966 case ARM::STC2_PRE: 1967 case ARM::STC2L_PRE: 1968 case ARM::t2LDC_OFFSET: 1969 case ARM::t2LDCL_OFFSET: 1970 case ARM::t2LDC_PRE: 1971 case ARM::t2LDCL_PRE: 1972 case ARM::t2STC_OFFSET: 1973 case ARM::t2STCL_OFFSET: 1974 case ARM::t2STC_PRE: 1975 case ARM::t2STCL_PRE: 1976 case ARM::LDC_OFFSET: 1977 case ARM::LDCL_OFFSET: 1978 case ARM::LDC_PRE: 1979 case ARM::LDCL_PRE: 1980 case ARM::STC_OFFSET: 1981 case ARM::STCL_OFFSET: 1982 case ARM::STC_PRE: 1983 case ARM::STCL_PRE: 1984 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1985 Inst.addOperand(MCOperand::createImm(imm)); 1986 break; 1987 case ARM::t2LDC2_POST: 1988 case ARM::t2LDC2L_POST: 1989 case ARM::t2STC2_POST: 1990 case ARM::t2STC2L_POST: 1991 case ARM::LDC2_POST: 1992 case ARM::LDC2L_POST: 1993 case ARM::STC2_POST: 1994 case ARM::STC2L_POST: 1995 case ARM::t2LDC_POST: 1996 case ARM::t2LDCL_POST: 1997 case ARM::t2STC_POST: 1998 case ARM::t2STCL_POST: 1999 case ARM::LDC_POST: 2000 case ARM::LDCL_POST: 2001 case ARM::STC_POST: 2002 case ARM::STCL_POST: 2003 imm |= U << 8; 2004 [[fallthrough]]; 2005 default: 2006 // The 'option' variant doesn't encode 'U' in the immediate since 2007 // the immediate is unsigned [0,255]. 2008 Inst.addOperand(MCOperand::createImm(imm)); 2009 break; 2010 } 2011 2012 switch (Inst.getOpcode()) { 2013 case ARM::LDC_OFFSET: 2014 case ARM::LDC_PRE: 2015 case ARM::LDC_POST: 2016 case ARM::LDC_OPTION: 2017 case ARM::LDCL_OFFSET: 2018 case ARM::LDCL_PRE: 2019 case ARM::LDCL_POST: 2020 case ARM::LDCL_OPTION: 2021 case ARM::STC_OFFSET: 2022 case ARM::STC_PRE: 2023 case ARM::STC_POST: 2024 case ARM::STC_OPTION: 2025 case ARM::STCL_OFFSET: 2026 case ARM::STCL_PRE: 2027 case ARM::STCL_POST: 2028 case ARM::STCL_OPTION: 2029 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2030 return MCDisassembler::Fail; 2031 break; 2032 default: 2033 break; 2034 } 2035 2036 return S; 2037} 2038 2039static DecodeStatus 2040DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 2041 const MCDisassembler *Decoder) { 2042 DecodeStatus S = MCDisassembler::Success; 2043 2044 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2045 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 2046 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2047 unsigned imm = fieldFromInstruction(Insn, 0, 12); 2048 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2049 unsigned reg = fieldFromInstruction(Insn, 25, 1); 2050 unsigned P = fieldFromInstruction(Insn, 24, 1); 2051 unsigned W = fieldFromInstruction(Insn, 21, 1); 2052 2053 // On stores, the writeback operand precedes Rt. 2054 switch (Inst.getOpcode()) { 2055 case ARM::STR_POST_IMM: 2056 case ARM::STR_POST_REG: 2057 case ARM::STRB_POST_IMM: 2058 case ARM::STRB_POST_REG: 2059 case ARM::STRT_POST_REG: 2060 case ARM::STRT_POST_IMM: 2061 case ARM::STRBT_POST_REG: 2062 case ARM::STRBT_POST_IMM: 2063 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2064 return MCDisassembler::Fail; 2065 break; 2066 default: 2067 break; 2068 } 2069 2070 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 2071 return MCDisassembler::Fail; 2072 2073 // On loads, the writeback operand comes after Rt. 2074 switch (Inst.getOpcode()) { 2075 case ARM::LDR_POST_IMM: 2076 case ARM::LDR_POST_REG: 2077 case ARM::LDRB_POST_IMM: 2078 case ARM::LDRB_POST_REG: 2079 case ARM::LDRBT_POST_REG: 2080 case ARM::LDRBT_POST_IMM: 2081 case ARM::LDRT_POST_REG: 2082 case ARM::LDRT_POST_IMM: 2083 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2084 return MCDisassembler::Fail; 2085 break; 2086 default: 2087 break; 2088 } 2089 2090 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2091 return MCDisassembler::Fail; 2092 2093 ARM_AM::AddrOpc Op = ARM_AM::add; 2094 if (!fieldFromInstruction(Insn, 23, 1)) 2095 Op = ARM_AM::sub; 2096 2097 bool writeback = (P == 0) || (W == 1); 2098 unsigned idx_mode = 0; 2099 if (P && writeback) 2100 idx_mode = ARMII::IndexModePre; 2101 else if (!P && writeback) 2102 idx_mode = ARMII::IndexModePost; 2103 2104 if (writeback && (Rn == 15 || Rn == Rt)) 2105 S = MCDisassembler::SoftFail; // UNPREDICTABLE 2106 2107 if (reg) { 2108 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2109 return MCDisassembler::Fail; 2110 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 2111 switch( fieldFromInstruction(Insn, 5, 2)) { 2112 case 0: 2113 Opc = ARM_AM::lsl; 2114 break; 2115 case 1: 2116 Opc = ARM_AM::lsr; 2117 break; 2118 case 2: 2119 Opc = ARM_AM::asr; 2120 break; 2121 case 3: 2122 Opc = ARM_AM::ror; 2123 break; 2124 default: 2125 return MCDisassembler::Fail; 2126 } 2127 unsigned amt = fieldFromInstruction(Insn, 7, 5); 2128 if (Opc == ARM_AM::ror && amt == 0) 2129 Opc = ARM_AM::rrx; 2130 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 2131 2132 Inst.addOperand(MCOperand::createImm(imm)); 2133 } else { 2134 Inst.addOperand(MCOperand::createReg(0)); 2135 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 2136 Inst.addOperand(MCOperand::createImm(tmp)); 2137 } 2138 2139 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2140 return MCDisassembler::Fail; 2141 2142 return S; 2143} 2144 2145static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 2146 uint64_t Address, 2147 const MCDisassembler *Decoder) { 2148 DecodeStatus S = MCDisassembler::Success; 2149 2150 unsigned Rn = fieldFromInstruction(Val, 13, 4); 2151 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2152 unsigned type = fieldFromInstruction(Val, 5, 2); 2153 unsigned imm = fieldFromInstruction(Val, 7, 5); 2154 unsigned U = fieldFromInstruction(Val, 12, 1); 2155 2156 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 2157 switch (type) { 2158 case 0: 2159 ShOp = ARM_AM::lsl; 2160 break; 2161 case 1: 2162 ShOp = ARM_AM::lsr; 2163 break; 2164 case 2: 2165 ShOp = ARM_AM::asr; 2166 break; 2167 case 3: 2168 ShOp = ARM_AM::ror; 2169 break; 2170 } 2171 2172 if (ShOp == ARM_AM::ror && imm == 0) 2173 ShOp = ARM_AM::rrx; 2174 2175 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2176 return MCDisassembler::Fail; 2177 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2178 return MCDisassembler::Fail; 2179 unsigned shift; 2180 if (U) 2181 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 2182 else 2183 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 2184 Inst.addOperand(MCOperand::createImm(shift)); 2185 2186 return S; 2187} 2188 2189static DecodeStatus DecodeTSBInstruction(MCInst &Inst, unsigned Insn, 2190 uint64_t Address, 2191 const MCDisassembler *Decoder) { 2192 if (Inst.getOpcode() != ARM::TSB && Inst.getOpcode() != ARM::t2TSB) 2193 return MCDisassembler::Fail; 2194 2195 // The "csync" operand is not encoded into the "tsb" instruction (as this is 2196 // the only available operand), but LLVM expects the instruction to have one 2197 // operand, so we need to add the csync when decoding. 2198 Inst.addOperand(MCOperand::createImm(ARM_TSB::CSYNC)); 2199 return MCDisassembler::Success; 2200} 2201 2202static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 2203 uint64_t Address, 2204 const MCDisassembler *Decoder) { 2205 DecodeStatus S = MCDisassembler::Success; 2206 2207 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 2208 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2209 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2210 unsigned type = fieldFromInstruction(Insn, 22, 1); 2211 unsigned imm = fieldFromInstruction(Insn, 8, 4); 2212 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8; 2213 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2214 unsigned W = fieldFromInstruction(Insn, 21, 1); 2215 unsigned P = fieldFromInstruction(Insn, 24, 1); 2216 unsigned Rt2 = Rt + 1; 2217 2218 bool writeback = (W == 1) | (P == 0); 2219 2220 // For {LD,ST}RD, Rt must be even, else undefined. 2221 switch (Inst.getOpcode()) { 2222 case ARM::STRD: 2223 case ARM::STRD_PRE: 2224 case ARM::STRD_POST: 2225 case ARM::LDRD: 2226 case ARM::LDRD_PRE: 2227 case ARM::LDRD_POST: 2228 if (Rt & 0x1) S = MCDisassembler::SoftFail; 2229 break; 2230 default: 2231 break; 2232 } 2233 switch (Inst.getOpcode()) { 2234 case ARM::STRD: 2235 case ARM::STRD_PRE: 2236 case ARM::STRD_POST: 2237 if (P == 0 && W == 1) 2238 S = MCDisassembler::SoftFail; 2239 2240 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 2241 S = MCDisassembler::SoftFail; 2242 if (type && Rm == 15) 2243 S = MCDisassembler::SoftFail; 2244 if (Rt2 == 15) 2245 S = MCDisassembler::SoftFail; 2246 if (!type && fieldFromInstruction(Insn, 8, 4)) 2247 S = MCDisassembler::SoftFail; 2248 break; 2249 case ARM::STRH: 2250 case ARM::STRH_PRE: 2251 case ARM::STRH_POST: 2252 if (Rt == 15) 2253 S = MCDisassembler::SoftFail; 2254 if (writeback && (Rn == 15 || Rn == Rt)) 2255 S = MCDisassembler::SoftFail; 2256 if (!type && Rm == 15) 2257 S = MCDisassembler::SoftFail; 2258 break; 2259 case ARM::LDRD: 2260 case ARM::LDRD_PRE: 2261 case ARM::LDRD_POST: 2262 if (type && Rn == 15) { 2263 if (Rt2 == 15) 2264 S = MCDisassembler::SoftFail; 2265 break; 2266 } 2267 if (P == 0 && W == 1) 2268 S = MCDisassembler::SoftFail; 2269 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 2270 S = MCDisassembler::SoftFail; 2271 if (!type && writeback && Rn == 15) 2272 S = MCDisassembler::SoftFail; 2273 if (writeback && (Rn == Rt || Rn == Rt2)) 2274 S = MCDisassembler::SoftFail; 2275 break; 2276 case ARM::LDRH: 2277 case ARM::LDRH_PRE: 2278 case ARM::LDRH_POST: 2279 if (type && Rn == 15) { 2280 if (Rt == 15) 2281 S = MCDisassembler::SoftFail; 2282 break; 2283 } 2284 if (Rt == 15) 2285 S = MCDisassembler::SoftFail; 2286 if (!type && Rm == 15) 2287 S = MCDisassembler::SoftFail; 2288 if (!type && writeback && (Rn == 15 || Rn == Rt)) 2289 S = MCDisassembler::SoftFail; 2290 break; 2291 case ARM::LDRSH: 2292 case ARM::LDRSH_PRE: 2293 case ARM::LDRSH_POST: 2294 case ARM::LDRSB: 2295 case ARM::LDRSB_PRE: 2296 case ARM::LDRSB_POST: 2297 if (type && Rn == 15) { 2298 if (Rt == 15) 2299 S = MCDisassembler::SoftFail; 2300 break; 2301 } 2302 if (type && (Rt == 15 || (writeback && Rn == Rt))) 2303 S = MCDisassembler::SoftFail; 2304 if (!type && (Rt == 15 || Rm == 15)) 2305 S = MCDisassembler::SoftFail; 2306 if (!type && writeback && (Rn == 15 || Rn == Rt)) 2307 S = MCDisassembler::SoftFail; 2308 break; 2309 default: 2310 break; 2311 } 2312 2313 if (writeback) { // Writeback 2314 if (P) 2315 U |= ARMII::IndexModePre << 9; 2316 else 2317 U |= ARMII::IndexModePost << 9; 2318 2319 // On stores, the writeback operand precedes Rt. 2320 switch (Inst.getOpcode()) { 2321 case ARM::STRD: 2322 case ARM::STRD_PRE: 2323 case ARM::STRD_POST: 2324 case ARM::STRH: 2325 case ARM::STRH_PRE: 2326 case ARM::STRH_POST: 2327 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2328 return MCDisassembler::Fail; 2329 break; 2330 default: 2331 break; 2332 } 2333 } 2334 2335 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 2336 return MCDisassembler::Fail; 2337 switch (Inst.getOpcode()) { 2338 case ARM::STRD: 2339 case ARM::STRD_PRE: 2340 case ARM::STRD_POST: 2341 case ARM::LDRD: 2342 case ARM::LDRD_PRE: 2343 case ARM::LDRD_POST: 2344 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 2345 return MCDisassembler::Fail; 2346 break; 2347 default: 2348 break; 2349 } 2350 2351 if (writeback) { 2352 // On loads, the writeback operand comes after Rt. 2353 switch (Inst.getOpcode()) { 2354 case ARM::LDRD: 2355 case ARM::LDRD_PRE: 2356 case ARM::LDRD_POST: 2357 case ARM::LDRH: 2358 case ARM::LDRH_PRE: 2359 case ARM::LDRH_POST: 2360 case ARM::LDRSH: 2361 case ARM::LDRSH_PRE: 2362 case ARM::LDRSH_POST: 2363 case ARM::LDRSB: 2364 case ARM::LDRSB_PRE: 2365 case ARM::LDRSB_POST: 2366 case ARM::LDRHTr: 2367 case ARM::LDRSBTr: 2368 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2369 return MCDisassembler::Fail; 2370 break; 2371 default: 2372 break; 2373 } 2374 } 2375 2376 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2377 return MCDisassembler::Fail; 2378 2379 if (type) { 2380 Inst.addOperand(MCOperand::createReg(0)); 2381 Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm)); 2382 } else { 2383 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2384 return MCDisassembler::Fail; 2385 Inst.addOperand(MCOperand::createImm(U)); 2386 } 2387 2388 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2389 return MCDisassembler::Fail; 2390 2391 return S; 2392} 2393 2394static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 2395 uint64_t Address, 2396 const MCDisassembler *Decoder) { 2397 DecodeStatus S = MCDisassembler::Success; 2398 2399 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2400 unsigned mode = fieldFromInstruction(Insn, 23, 2); 2401 2402 switch (mode) { 2403 case 0: 2404 mode = ARM_AM::da; 2405 break; 2406 case 1: 2407 mode = ARM_AM::ia; 2408 break; 2409 case 2: 2410 mode = ARM_AM::db; 2411 break; 2412 case 3: 2413 mode = ARM_AM::ib; 2414 break; 2415 } 2416 2417 Inst.addOperand(MCOperand::createImm(mode)); 2418 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2419 return MCDisassembler::Fail; 2420 2421 return S; 2422} 2423 2424static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 2425 uint64_t Address, 2426 const MCDisassembler *Decoder) { 2427 DecodeStatus S = MCDisassembler::Success; 2428 2429 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2430 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2431 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2432 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2433 2434 if (pred == 0xF) 2435 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2436 2437 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2438 return MCDisassembler::Fail; 2439 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2440 return MCDisassembler::Fail; 2441 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2442 return MCDisassembler::Fail; 2443 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2444 return MCDisassembler::Fail; 2445 return S; 2446} 2447 2448static DecodeStatus 2449DecodeMemMultipleWritebackInstruction(MCInst &Inst, unsigned Insn, 2450 uint64_t Address, 2451 const MCDisassembler *Decoder) { 2452 DecodeStatus S = MCDisassembler::Success; 2453 2454 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2455 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2456 unsigned reglist = fieldFromInstruction(Insn, 0, 16); 2457 2458 if (pred == 0xF) { 2459 // Ambiguous with RFE and SRS 2460 switch (Inst.getOpcode()) { 2461 case ARM::LDMDA: 2462 Inst.setOpcode(ARM::RFEDA); 2463 break; 2464 case ARM::LDMDA_UPD: 2465 Inst.setOpcode(ARM::RFEDA_UPD); 2466 break; 2467 case ARM::LDMDB: 2468 Inst.setOpcode(ARM::RFEDB); 2469 break; 2470 case ARM::LDMDB_UPD: 2471 Inst.setOpcode(ARM::RFEDB_UPD); 2472 break; 2473 case ARM::LDMIA: 2474 Inst.setOpcode(ARM::RFEIA); 2475 break; 2476 case ARM::LDMIA_UPD: 2477 Inst.setOpcode(ARM::RFEIA_UPD); 2478 break; 2479 case ARM::LDMIB: 2480 Inst.setOpcode(ARM::RFEIB); 2481 break; 2482 case ARM::LDMIB_UPD: 2483 Inst.setOpcode(ARM::RFEIB_UPD); 2484 break; 2485 case ARM::STMDA: 2486 Inst.setOpcode(ARM::SRSDA); 2487 break; 2488 case ARM::STMDA_UPD: 2489 Inst.setOpcode(ARM::SRSDA_UPD); 2490 break; 2491 case ARM::STMDB: 2492 Inst.setOpcode(ARM::SRSDB); 2493 break; 2494 case ARM::STMDB_UPD: 2495 Inst.setOpcode(ARM::SRSDB_UPD); 2496 break; 2497 case ARM::STMIA: 2498 Inst.setOpcode(ARM::SRSIA); 2499 break; 2500 case ARM::STMIA_UPD: 2501 Inst.setOpcode(ARM::SRSIA_UPD); 2502 break; 2503 case ARM::STMIB: 2504 Inst.setOpcode(ARM::SRSIB); 2505 break; 2506 case ARM::STMIB_UPD: 2507 Inst.setOpcode(ARM::SRSIB_UPD); 2508 break; 2509 default: 2510 return MCDisassembler::Fail; 2511 } 2512 2513 // For stores (which become SRS's, the only operand is the mode. 2514 if (fieldFromInstruction(Insn, 20, 1) == 0) { 2515 // Check SRS encoding constraints 2516 if (!(fieldFromInstruction(Insn, 22, 1) == 1 && 2517 fieldFromInstruction(Insn, 20, 1) == 0)) 2518 return MCDisassembler::Fail; 2519 2520 Inst.addOperand( 2521 MCOperand::createImm(fieldFromInstruction(Insn, 0, 4))); 2522 return S; 2523 } 2524 2525 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 2526 } 2527 2528 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2529 return MCDisassembler::Fail; 2530 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2531 return MCDisassembler::Fail; // Tied 2532 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2533 return MCDisassembler::Fail; 2534 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 2535 return MCDisassembler::Fail; 2536 2537 return S; 2538} 2539 2540// Check for UNPREDICTABLE predicated ESB instruction 2541static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn, 2542 uint64_t Address, 2543 const MCDisassembler *Decoder) { 2544 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2545 unsigned imm8 = fieldFromInstruction(Insn, 0, 8); 2546 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 2547 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 2548 2549 DecodeStatus S = MCDisassembler::Success; 2550 2551 Inst.addOperand(MCOperand::createImm(imm8)); 2552 2553 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2554 return MCDisassembler::Fail; 2555 2556 // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP, 2557 // so all predicates should be allowed. 2558 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0)) 2559 S = MCDisassembler::SoftFail; 2560 2561 return S; 2562} 2563 2564static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 2565 uint64_t Address, 2566 const MCDisassembler *Decoder) { 2567 unsigned imod = fieldFromInstruction(Insn, 18, 2); 2568 unsigned M = fieldFromInstruction(Insn, 17, 1); 2569 unsigned iflags = fieldFromInstruction(Insn, 6, 3); 2570 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2571 2572 DecodeStatus S = MCDisassembler::Success; 2573 2574 // This decoder is called from multiple location that do not check 2575 // the full encoding is valid before they do. 2576 if (fieldFromInstruction(Insn, 5, 1) != 0 || 2577 fieldFromInstruction(Insn, 16, 1) != 0 || 2578 fieldFromInstruction(Insn, 20, 8) != 0x10) 2579 return MCDisassembler::Fail; 2580 2581 // imod == '01' --> UNPREDICTABLE 2582 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2583 // return failure here. The '01' imod value is unprintable, so there's 2584 // nothing useful we could do even if we returned UNPREDICTABLE. 2585 2586 if (imod == 1) return MCDisassembler::Fail; 2587 2588 if (imod && M) { 2589 Inst.setOpcode(ARM::CPS3p); 2590 Inst.addOperand(MCOperand::createImm(imod)); 2591 Inst.addOperand(MCOperand::createImm(iflags)); 2592 Inst.addOperand(MCOperand::createImm(mode)); 2593 } else if (imod && !M) { 2594 Inst.setOpcode(ARM::CPS2p); 2595 Inst.addOperand(MCOperand::createImm(imod)); 2596 Inst.addOperand(MCOperand::createImm(iflags)); 2597 if (mode) S = MCDisassembler::SoftFail; 2598 } else if (!imod && M) { 2599 Inst.setOpcode(ARM::CPS1p); 2600 Inst.addOperand(MCOperand::createImm(mode)); 2601 if (iflags) S = MCDisassembler::SoftFail; 2602 } else { 2603 // imod == '00' && M == '0' --> UNPREDICTABLE 2604 Inst.setOpcode(ARM::CPS1p); 2605 Inst.addOperand(MCOperand::createImm(mode)); 2606 S = MCDisassembler::SoftFail; 2607 } 2608 2609 return S; 2610} 2611 2612static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 2613 uint64_t Address, 2614 const MCDisassembler *Decoder) { 2615 unsigned imod = fieldFromInstruction(Insn, 9, 2); 2616 unsigned M = fieldFromInstruction(Insn, 8, 1); 2617 unsigned iflags = fieldFromInstruction(Insn, 5, 3); 2618 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2619 2620 DecodeStatus S = MCDisassembler::Success; 2621 2622 // imod == '01' --> UNPREDICTABLE 2623 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2624 // return failure here. The '01' imod value is unprintable, so there's 2625 // nothing useful we could do even if we returned UNPREDICTABLE. 2626 2627 if (imod == 1) return MCDisassembler::Fail; 2628 2629 if (imod && M) { 2630 Inst.setOpcode(ARM::t2CPS3p); 2631 Inst.addOperand(MCOperand::createImm(imod)); 2632 Inst.addOperand(MCOperand::createImm(iflags)); 2633 Inst.addOperand(MCOperand::createImm(mode)); 2634 } else if (imod && !M) { 2635 Inst.setOpcode(ARM::t2CPS2p); 2636 Inst.addOperand(MCOperand::createImm(imod)); 2637 Inst.addOperand(MCOperand::createImm(iflags)); 2638 if (mode) S = MCDisassembler::SoftFail; 2639 } else if (!imod && M) { 2640 Inst.setOpcode(ARM::t2CPS1p); 2641 Inst.addOperand(MCOperand::createImm(mode)); 2642 if (iflags) S = MCDisassembler::SoftFail; 2643 } else { 2644 // imod == '00' && M == '0' --> this is a HINT instruction 2645 int imm = fieldFromInstruction(Insn, 0, 8); 2646 // HINT are defined only for immediate in [0..4] 2647 if(imm > 4) return MCDisassembler::Fail; 2648 Inst.setOpcode(ARM::t2HINT); 2649 Inst.addOperand(MCOperand::createImm(imm)); 2650 } 2651 2652 return S; 2653} 2654 2655static DecodeStatus 2656DecodeT2HintSpaceInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, 2657 const MCDisassembler *Decoder) { 2658 unsigned imm = fieldFromInstruction(Insn, 0, 8); 2659 2660 unsigned Opcode = ARM::t2HINT; 2661 2662 if (imm == 0x0D) { 2663 Opcode = ARM::t2PACBTI; 2664 } else if (imm == 0x1D) { 2665 Opcode = ARM::t2PAC; 2666 } else if (imm == 0x2D) { 2667 Opcode = ARM::t2AUT; 2668 } else if (imm == 0x0F) { 2669 Opcode = ARM::t2BTI; 2670 } 2671 2672 Inst.setOpcode(Opcode); 2673 if (Opcode == ARM::t2HINT) { 2674 Inst.addOperand(MCOperand::createImm(imm)); 2675 } 2676 2677 return MCDisassembler::Success; 2678} 2679 2680static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 2681 uint64_t Address, 2682 const MCDisassembler *Decoder) { 2683 DecodeStatus S = MCDisassembler::Success; 2684 2685 unsigned Rd = fieldFromInstruction(Insn, 8, 4); 2686 unsigned imm = 0; 2687 2688 imm |= (fieldFromInstruction(Insn, 0, 8) << 0); 2689 imm |= (fieldFromInstruction(Insn, 12, 3) << 8); 2690 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2691 imm |= (fieldFromInstruction(Insn, 26, 1) << 11); 2692 2693 if (Inst.getOpcode() == ARM::t2MOVTi16) 2694 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2695 return MCDisassembler::Fail; 2696 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2697 return MCDisassembler::Fail; 2698 2699 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2700 Inst.addOperand(MCOperand::createImm(imm)); 2701 2702 return S; 2703} 2704 2705static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 2706 uint64_t Address, 2707 const MCDisassembler *Decoder) { 2708 DecodeStatus S = MCDisassembler::Success; 2709 2710 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2711 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2712 unsigned imm = 0; 2713 2714 imm |= (fieldFromInstruction(Insn, 0, 12) << 0); 2715 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2716 2717 if (Inst.getOpcode() == ARM::MOVTi16) 2718 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2719 return MCDisassembler::Fail; 2720 2721 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2722 return MCDisassembler::Fail; 2723 2724 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2725 Inst.addOperand(MCOperand::createImm(imm)); 2726 2727 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2728 return MCDisassembler::Fail; 2729 2730 return S; 2731} 2732 2733static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 2734 uint64_t Address, 2735 const MCDisassembler *Decoder) { 2736 DecodeStatus S = MCDisassembler::Success; 2737 2738 unsigned Rd = fieldFromInstruction(Insn, 16, 4); 2739 unsigned Rn = fieldFromInstruction(Insn, 0, 4); 2740 unsigned Rm = fieldFromInstruction(Insn, 8, 4); 2741 unsigned Ra = fieldFromInstruction(Insn, 12, 4); 2742 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2743 2744 if (pred == 0xF) 2745 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2746 2747 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2748 return MCDisassembler::Fail; 2749 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2750 return MCDisassembler::Fail; 2751 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2752 return MCDisassembler::Fail; 2753 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 2754 return MCDisassembler::Fail; 2755 2756 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2757 return MCDisassembler::Fail; 2758 2759 return S; 2760} 2761 2762static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, 2763 uint64_t Address, 2764 const MCDisassembler *Decoder) { 2765 DecodeStatus S = MCDisassembler::Success; 2766 2767 unsigned Pred = fieldFromInstruction(Insn, 28, 4); 2768 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2769 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2770 2771 if (Pred == 0xF) 2772 return DecodeSETPANInstruction(Inst, Insn, Address, Decoder); 2773 2774 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2775 return MCDisassembler::Fail; 2776 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2777 return MCDisassembler::Fail; 2778 if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder))) 2779 return MCDisassembler::Fail; 2780 2781 return S; 2782} 2783 2784static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, 2785 uint64_t Address, 2786 const MCDisassembler *Decoder) { 2787 DecodeStatus S = MCDisassembler::Success; 2788 2789 unsigned Imm = fieldFromInstruction(Insn, 9, 1); 2790 2791 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 2792 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); 2793 2794 if (!FeatureBits[ARM::HasV8_1aOps] || 2795 !FeatureBits[ARM::HasV8Ops]) 2796 return MCDisassembler::Fail; 2797 2798 // Decoder can be called from DecodeTST, which does not check the full 2799 // encoding is valid. 2800 if (fieldFromInstruction(Insn, 20,12) != 0xf11 || 2801 fieldFromInstruction(Insn, 4,4) != 0) 2802 return MCDisassembler::Fail; 2803 if (fieldFromInstruction(Insn, 10,10) != 0 || 2804 fieldFromInstruction(Insn, 0,4) != 0) 2805 S = MCDisassembler::SoftFail; 2806 2807 Inst.setOpcode(ARM::SETPAN); 2808 Inst.addOperand(MCOperand::createImm(Imm)); 2809 2810 return S; 2811} 2812 2813static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 2814 uint64_t Address, 2815 const MCDisassembler *Decoder) { 2816 DecodeStatus S = MCDisassembler::Success; 2817 2818 unsigned add = fieldFromInstruction(Val, 12, 1); 2819 unsigned imm = fieldFromInstruction(Val, 0, 12); 2820 unsigned Rn = fieldFromInstruction(Val, 13, 4); 2821 2822 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2823 return MCDisassembler::Fail; 2824 2825 if (!add) imm *= -1; 2826 if (imm == 0 && !add) imm = INT32_MIN; 2827 Inst.addOperand(MCOperand::createImm(imm)); 2828 if (Rn == 15) 2829 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2830 2831 return S; 2832} 2833 2834static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2835 uint64_t Address, 2836 const MCDisassembler *Decoder) { 2837 DecodeStatus S = MCDisassembler::Success; 2838 2839 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2840 // U == 1 to add imm, 0 to subtract it. 2841 unsigned U = fieldFromInstruction(Val, 8, 1); 2842 unsigned imm = fieldFromInstruction(Val, 0, 8); 2843 2844 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2845 return MCDisassembler::Fail; 2846 2847 if (U) 2848 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2849 else 2850 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2851 2852 return S; 2853} 2854 2855static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val, 2856 uint64_t Address, 2857 const MCDisassembler *Decoder) { 2858 DecodeStatus S = MCDisassembler::Success; 2859 2860 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2861 // U == 1 to add imm, 0 to subtract it. 2862 unsigned U = fieldFromInstruction(Val, 8, 1); 2863 unsigned imm = fieldFromInstruction(Val, 0, 8); 2864 2865 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2866 return MCDisassembler::Fail; 2867 2868 if (U) 2869 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::add, imm))); 2870 else 2871 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::sub, imm))); 2872 2873 return S; 2874} 2875 2876static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 2877 uint64_t Address, 2878 const MCDisassembler *Decoder) { 2879 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2880} 2881 2882static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 2883 uint64_t Address, 2884 const MCDisassembler *Decoder) { 2885 DecodeStatus Status = MCDisassembler::Success; 2886 2887 // Note the J1 and J2 values are from the encoded instruction. So here 2888 // change them to I1 and I2 values via as documented: 2889 // I1 = NOT(J1 EOR S); 2890 // I2 = NOT(J2 EOR S); 2891 // and build the imm32 with one trailing zero as documented: 2892 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 2893 unsigned S = fieldFromInstruction(Insn, 26, 1); 2894 unsigned J1 = fieldFromInstruction(Insn, 13, 1); 2895 unsigned J2 = fieldFromInstruction(Insn, 11, 1); 2896 unsigned I1 = !(J1 ^ S); 2897 unsigned I2 = !(J2 ^ S); 2898 unsigned imm10 = fieldFromInstruction(Insn, 16, 10); 2899 unsigned imm11 = fieldFromInstruction(Insn, 0, 11); 2900 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; 2901 int imm32 = SignExtend32<25>(tmp << 1); 2902 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 2903 true, 4, Inst, Decoder)) 2904 Inst.addOperand(MCOperand::createImm(imm32)); 2905 2906 return Status; 2907} 2908 2909static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 2910 uint64_t Address, 2911 const MCDisassembler *Decoder) { 2912 DecodeStatus S = MCDisassembler::Success; 2913 2914 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2915 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2; 2916 2917 if (pred == 0xF) { 2918 Inst.setOpcode(ARM::BLXi); 2919 imm |= fieldFromInstruction(Insn, 24, 1) << 1; 2920 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2921 true, 4, Inst, Decoder)) 2922 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2923 return S; 2924 } 2925 2926 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2927 true, 4, Inst, Decoder)) 2928 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); 2929 2930 // We already have BL_pred for BL w/ predicate, no need to add addition 2931 // predicate opreands for BL 2932 if (Inst.getOpcode() != ARM::BL) 2933 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2934 return MCDisassembler::Fail; 2935 2936 return S; 2937} 2938 2939static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 2940 uint64_t Address, 2941 const MCDisassembler *Decoder) { 2942 DecodeStatus S = MCDisassembler::Success; 2943 2944 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2945 unsigned align = fieldFromInstruction(Val, 4, 2); 2946 2947 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2948 return MCDisassembler::Fail; 2949 if (!align) 2950 Inst.addOperand(MCOperand::createImm(0)); 2951 else 2952 Inst.addOperand(MCOperand::createImm(4 << align)); 2953 2954 return S; 2955} 2956 2957static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 2958 uint64_t Address, 2959 const MCDisassembler *Decoder) { 2960 DecodeStatus S = MCDisassembler::Success; 2961 2962 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2963 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2964 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2965 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2966 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2967 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2968 2969 // First output register 2970 switch (Inst.getOpcode()) { 2971 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2972 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2973 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2974 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2975 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2976 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2977 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2978 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2979 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2980 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2981 return MCDisassembler::Fail; 2982 break; 2983 case ARM::VLD2b16: 2984 case ARM::VLD2b32: 2985 case ARM::VLD2b8: 2986 case ARM::VLD2b16wb_fixed: 2987 case ARM::VLD2b16wb_register: 2988 case ARM::VLD2b32wb_fixed: 2989 case ARM::VLD2b32wb_register: 2990 case ARM::VLD2b8wb_fixed: 2991 case ARM::VLD2b8wb_register: 2992 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2993 return MCDisassembler::Fail; 2994 break; 2995 default: 2996 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2997 return MCDisassembler::Fail; 2998 } 2999 3000 // Second output register 3001 switch (Inst.getOpcode()) { 3002 case ARM::VLD3d8: 3003 case ARM::VLD3d16: 3004 case ARM::VLD3d32: 3005 case ARM::VLD3d8_UPD: 3006 case ARM::VLD3d16_UPD: 3007 case ARM::VLD3d32_UPD: 3008 case ARM::VLD4d8: 3009 case ARM::VLD4d16: 3010 case ARM::VLD4d32: 3011 case ARM::VLD4d8_UPD: 3012 case ARM::VLD4d16_UPD: 3013 case ARM::VLD4d32_UPD: 3014 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 3015 return MCDisassembler::Fail; 3016 break; 3017 case ARM::VLD3q8: 3018 case ARM::VLD3q16: 3019 case ARM::VLD3q32: 3020 case ARM::VLD3q8_UPD: 3021 case ARM::VLD3q16_UPD: 3022 case ARM::VLD3q32_UPD: 3023 case ARM::VLD4q8: 3024 case ARM::VLD4q16: 3025 case ARM::VLD4q32: 3026 case ARM::VLD4q8_UPD: 3027 case ARM::VLD4q16_UPD: 3028 case ARM::VLD4q32_UPD: 3029 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3030 return MCDisassembler::Fail; 3031 break; 3032 default: 3033 break; 3034 } 3035 3036 // Third output register 3037 switch(Inst.getOpcode()) { 3038 case ARM::VLD3d8: 3039 case ARM::VLD3d16: 3040 case ARM::VLD3d32: 3041 case ARM::VLD3d8_UPD: 3042 case ARM::VLD3d16_UPD: 3043 case ARM::VLD3d32_UPD: 3044 case ARM::VLD4d8: 3045 case ARM::VLD4d16: 3046 case ARM::VLD4d32: 3047 case ARM::VLD4d8_UPD: 3048 case ARM::VLD4d16_UPD: 3049 case ARM::VLD4d32_UPD: 3050 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3051 return MCDisassembler::Fail; 3052 break; 3053 case ARM::VLD3q8: 3054 case ARM::VLD3q16: 3055 case ARM::VLD3q32: 3056 case ARM::VLD3q8_UPD: 3057 case ARM::VLD3q16_UPD: 3058 case ARM::VLD3q32_UPD: 3059 case ARM::VLD4q8: 3060 case ARM::VLD4q16: 3061 case ARM::VLD4q32: 3062 case ARM::VLD4q8_UPD: 3063 case ARM::VLD4q16_UPD: 3064 case ARM::VLD4q32_UPD: 3065 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 3066 return MCDisassembler::Fail; 3067 break; 3068 default: 3069 break; 3070 } 3071 3072 // Fourth output register 3073 switch (Inst.getOpcode()) { 3074 case ARM::VLD4d8: 3075 case ARM::VLD4d16: 3076 case ARM::VLD4d32: 3077 case ARM::VLD4d8_UPD: 3078 case ARM::VLD4d16_UPD: 3079 case ARM::VLD4d32_UPD: 3080 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 3081 return MCDisassembler::Fail; 3082 break; 3083 case ARM::VLD4q8: 3084 case ARM::VLD4q16: 3085 case ARM::VLD4q32: 3086 case ARM::VLD4q8_UPD: 3087 case ARM::VLD4q16_UPD: 3088 case ARM::VLD4q32_UPD: 3089 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 3090 return MCDisassembler::Fail; 3091 break; 3092 default: 3093 break; 3094 } 3095 3096 // Writeback operand 3097 switch (Inst.getOpcode()) { 3098 case ARM::VLD1d8wb_fixed: 3099 case ARM::VLD1d16wb_fixed: 3100 case ARM::VLD1d32wb_fixed: 3101 case ARM::VLD1d64wb_fixed: 3102 case ARM::VLD1d8wb_register: 3103 case ARM::VLD1d16wb_register: 3104 case ARM::VLD1d32wb_register: 3105 case ARM::VLD1d64wb_register: 3106 case ARM::VLD1q8wb_fixed: 3107 case ARM::VLD1q16wb_fixed: 3108 case ARM::VLD1q32wb_fixed: 3109 case ARM::VLD1q64wb_fixed: 3110 case ARM::VLD1q8wb_register: 3111 case ARM::VLD1q16wb_register: 3112 case ARM::VLD1q32wb_register: 3113 case ARM::VLD1q64wb_register: 3114 case ARM::VLD1d8Twb_fixed: 3115 case ARM::VLD1d8Twb_register: 3116 case ARM::VLD1d16Twb_fixed: 3117 case ARM::VLD1d16Twb_register: 3118 case ARM::VLD1d32Twb_fixed: 3119 case ARM::VLD1d32Twb_register: 3120 case ARM::VLD1d64Twb_fixed: 3121 case ARM::VLD1d64Twb_register: 3122 case ARM::VLD1d8Qwb_fixed: 3123 case ARM::VLD1d8Qwb_register: 3124 case ARM::VLD1d16Qwb_fixed: 3125 case ARM::VLD1d16Qwb_register: 3126 case ARM::VLD1d32Qwb_fixed: 3127 case ARM::VLD1d32Qwb_register: 3128 case ARM::VLD1d64Qwb_fixed: 3129 case ARM::VLD1d64Qwb_register: 3130 case ARM::VLD2d8wb_fixed: 3131 case ARM::VLD2d16wb_fixed: 3132 case ARM::VLD2d32wb_fixed: 3133 case ARM::VLD2q8wb_fixed: 3134 case ARM::VLD2q16wb_fixed: 3135 case ARM::VLD2q32wb_fixed: 3136 case ARM::VLD2d8wb_register: 3137 case ARM::VLD2d16wb_register: 3138 case ARM::VLD2d32wb_register: 3139 case ARM::VLD2q8wb_register: 3140 case ARM::VLD2q16wb_register: 3141 case ARM::VLD2q32wb_register: 3142 case ARM::VLD2b8wb_fixed: 3143 case ARM::VLD2b16wb_fixed: 3144 case ARM::VLD2b32wb_fixed: 3145 case ARM::VLD2b8wb_register: 3146 case ARM::VLD2b16wb_register: 3147 case ARM::VLD2b32wb_register: 3148 Inst.addOperand(MCOperand::createImm(0)); 3149 break; 3150 case ARM::VLD3d8_UPD: 3151 case ARM::VLD3d16_UPD: 3152 case ARM::VLD3d32_UPD: 3153 case ARM::VLD3q8_UPD: 3154 case ARM::VLD3q16_UPD: 3155 case ARM::VLD3q32_UPD: 3156 case ARM::VLD4d8_UPD: 3157 case ARM::VLD4d16_UPD: 3158 case ARM::VLD4d32_UPD: 3159 case ARM::VLD4q8_UPD: 3160 case ARM::VLD4q16_UPD: 3161 case ARM::VLD4q32_UPD: 3162 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 3163 return MCDisassembler::Fail; 3164 break; 3165 default: 3166 break; 3167 } 3168 3169 // AddrMode6 Base (register+alignment) 3170 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 3171 return MCDisassembler::Fail; 3172 3173 // AddrMode6 Offset (register) 3174 switch (Inst.getOpcode()) { 3175 default: 3176 // The below have been updated to have explicit am6offset split 3177 // between fixed and register offset. For those instructions not 3178 // yet updated, we need to add an additional reg0 operand for the 3179 // fixed variant. 3180 // 3181 // The fixed offset encodes as Rm == 0xd, so we check for that. 3182 if (Rm == 0xd) { 3183 Inst.addOperand(MCOperand::createReg(0)); 3184 break; 3185 } 3186 // Fall through to handle the register offset variant. 3187 [[fallthrough]]; 3188 case ARM::VLD1d8wb_fixed: 3189 case ARM::VLD1d16wb_fixed: 3190 case ARM::VLD1d32wb_fixed: 3191 case ARM::VLD1d64wb_fixed: 3192 case ARM::VLD1d8Twb_fixed: 3193 case ARM::VLD1d16Twb_fixed: 3194 case ARM::VLD1d32Twb_fixed: 3195 case ARM::VLD1d64Twb_fixed: 3196 case ARM::VLD1d8Qwb_fixed: 3197 case ARM::VLD1d16Qwb_fixed: 3198 case ARM::VLD1d32Qwb_fixed: 3199 case ARM::VLD1d64Qwb_fixed: 3200 case ARM::VLD1d8wb_register: 3201 case ARM::VLD1d16wb_register: 3202 case ARM::VLD1d32wb_register: 3203 case ARM::VLD1d64wb_register: 3204 case ARM::VLD1q8wb_fixed: 3205 case ARM::VLD1q16wb_fixed: 3206 case ARM::VLD1q32wb_fixed: 3207 case ARM::VLD1q64wb_fixed: 3208 case ARM::VLD1q8wb_register: 3209 case ARM::VLD1q16wb_register: 3210 case ARM::VLD1q32wb_register: 3211 case ARM::VLD1q64wb_register: 3212 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 3213 // variant encodes Rm == 0xf. Anything else is a register offset post- 3214 // increment and we need to add the register operand to the instruction. 3215 if (Rm != 0xD && Rm != 0xF && 3216 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3217 return MCDisassembler::Fail; 3218 break; 3219 case ARM::VLD2d8wb_fixed: 3220 case ARM::VLD2d16wb_fixed: 3221 case ARM::VLD2d32wb_fixed: 3222 case ARM::VLD2b8wb_fixed: 3223 case ARM::VLD2b16wb_fixed: 3224 case ARM::VLD2b32wb_fixed: 3225 case ARM::VLD2q8wb_fixed: 3226 case ARM::VLD2q16wb_fixed: 3227 case ARM::VLD2q32wb_fixed: 3228 break; 3229 } 3230 3231 return S; 3232} 3233 3234static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn, 3235 uint64_t Address, 3236 const MCDisassembler *Decoder) { 3237 unsigned type = fieldFromInstruction(Insn, 8, 4); 3238 unsigned align = fieldFromInstruction(Insn, 4, 2); 3239 if (type == 6 && (align & 2)) return MCDisassembler::Fail; 3240 if (type == 7 && (align & 2)) return MCDisassembler::Fail; 3241 if (type == 10 && align == 3) return MCDisassembler::Fail; 3242 3243 unsigned load = fieldFromInstruction(Insn, 21, 1); 3244 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 3245 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 3246} 3247 3248static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn, 3249 uint64_t Address, 3250 const MCDisassembler *Decoder) { 3251 unsigned size = fieldFromInstruction(Insn, 6, 2); 3252 if (size == 3) return MCDisassembler::Fail; 3253 3254 unsigned type = fieldFromInstruction(Insn, 8, 4); 3255 unsigned align = fieldFromInstruction(Insn, 4, 2); 3256 if (type == 8 && align == 3) return MCDisassembler::Fail; 3257 if (type == 9 && align == 3) return MCDisassembler::Fail; 3258 3259 unsigned load = fieldFromInstruction(Insn, 21, 1); 3260 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 3261 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 3262} 3263 3264static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn, 3265 uint64_t Address, 3266 const MCDisassembler *Decoder) { 3267 unsigned size = fieldFromInstruction(Insn, 6, 2); 3268 if (size == 3) return MCDisassembler::Fail; 3269 3270 unsigned align = fieldFromInstruction(Insn, 4, 2); 3271 if (align & 2) return MCDisassembler::Fail; 3272 3273 unsigned load = fieldFromInstruction(Insn, 21, 1); 3274 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 3275 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 3276} 3277 3278static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn, 3279 uint64_t Address, 3280 const MCDisassembler *Decoder) { 3281 unsigned size = fieldFromInstruction(Insn, 6, 2); 3282 if (size == 3) return MCDisassembler::Fail; 3283 3284 unsigned load = fieldFromInstruction(Insn, 21, 1); 3285 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 3286 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 3287} 3288 3289static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 3290 uint64_t Address, 3291 const MCDisassembler *Decoder) { 3292 DecodeStatus S = MCDisassembler::Success; 3293 3294 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3295 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3296 unsigned wb = fieldFromInstruction(Insn, 16, 4); 3297 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3298 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 3299 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3300 3301 // Writeback Operand 3302 switch (Inst.getOpcode()) { 3303 case ARM::VST1d8wb_fixed: 3304 case ARM::VST1d16wb_fixed: 3305 case ARM::VST1d32wb_fixed: 3306 case ARM::VST1d64wb_fixed: 3307 case ARM::VST1d8wb_register: 3308 case ARM::VST1d16wb_register: 3309 case ARM::VST1d32wb_register: 3310 case ARM::VST1d64wb_register: 3311 case ARM::VST1q8wb_fixed: 3312 case ARM::VST1q16wb_fixed: 3313 case ARM::VST1q32wb_fixed: 3314 case ARM::VST1q64wb_fixed: 3315 case ARM::VST1q8wb_register: 3316 case ARM::VST1q16wb_register: 3317 case ARM::VST1q32wb_register: 3318 case ARM::VST1q64wb_register: 3319 case ARM::VST1d8Twb_fixed: 3320 case ARM::VST1d16Twb_fixed: 3321 case ARM::VST1d32Twb_fixed: 3322 case ARM::VST1d64Twb_fixed: 3323 case ARM::VST1d8Twb_register: 3324 case ARM::VST1d16Twb_register: 3325 case ARM::VST1d32Twb_register: 3326 case ARM::VST1d64Twb_register: 3327 case ARM::VST1d8Qwb_fixed: 3328 case ARM::VST1d16Qwb_fixed: 3329 case ARM::VST1d32Qwb_fixed: 3330 case ARM::VST1d64Qwb_fixed: 3331 case ARM::VST1d8Qwb_register: 3332 case ARM::VST1d16Qwb_register: 3333 case ARM::VST1d32Qwb_register: 3334 case ARM::VST1d64Qwb_register: 3335 case ARM::VST2d8wb_fixed: 3336 case ARM::VST2d16wb_fixed: 3337 case ARM::VST2d32wb_fixed: 3338 case ARM::VST2d8wb_register: 3339 case ARM::VST2d16wb_register: 3340 case ARM::VST2d32wb_register: 3341 case ARM::VST2q8wb_fixed: 3342 case ARM::VST2q16wb_fixed: 3343 case ARM::VST2q32wb_fixed: 3344 case ARM::VST2q8wb_register: 3345 case ARM::VST2q16wb_register: 3346 case ARM::VST2q32wb_register: 3347 case ARM::VST2b8wb_fixed: 3348 case ARM::VST2b16wb_fixed: 3349 case ARM::VST2b32wb_fixed: 3350 case ARM::VST2b8wb_register: 3351 case ARM::VST2b16wb_register: 3352 case ARM::VST2b32wb_register: 3353 if (Rm == 0xF) 3354 return MCDisassembler::Fail; 3355 Inst.addOperand(MCOperand::createImm(0)); 3356 break; 3357 case ARM::VST3d8_UPD: 3358 case ARM::VST3d16_UPD: 3359 case ARM::VST3d32_UPD: 3360 case ARM::VST3q8_UPD: 3361 case ARM::VST3q16_UPD: 3362 case ARM::VST3q32_UPD: 3363 case ARM::VST4d8_UPD: 3364 case ARM::VST4d16_UPD: 3365 case ARM::VST4d32_UPD: 3366 case ARM::VST4q8_UPD: 3367 case ARM::VST4q16_UPD: 3368 case ARM::VST4q32_UPD: 3369 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 3370 return MCDisassembler::Fail; 3371 break; 3372 default: 3373 break; 3374 } 3375 3376 // AddrMode6 Base (register+alignment) 3377 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 3378 return MCDisassembler::Fail; 3379 3380 // AddrMode6 Offset (register) 3381 switch (Inst.getOpcode()) { 3382 default: 3383 if (Rm == 0xD) 3384 Inst.addOperand(MCOperand::createReg(0)); 3385 else if (Rm != 0xF) { 3386 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3387 return MCDisassembler::Fail; 3388 } 3389 break; 3390 case ARM::VST1d8wb_fixed: 3391 case ARM::VST1d16wb_fixed: 3392 case ARM::VST1d32wb_fixed: 3393 case ARM::VST1d64wb_fixed: 3394 case ARM::VST1q8wb_fixed: 3395 case ARM::VST1q16wb_fixed: 3396 case ARM::VST1q32wb_fixed: 3397 case ARM::VST1q64wb_fixed: 3398 case ARM::VST1d8Twb_fixed: 3399 case ARM::VST1d16Twb_fixed: 3400 case ARM::VST1d32Twb_fixed: 3401 case ARM::VST1d64Twb_fixed: 3402 case ARM::VST1d8Qwb_fixed: 3403 case ARM::VST1d16Qwb_fixed: 3404 case ARM::VST1d32Qwb_fixed: 3405 case ARM::VST1d64Qwb_fixed: 3406 case ARM::VST2d8wb_fixed: 3407 case ARM::VST2d16wb_fixed: 3408 case ARM::VST2d32wb_fixed: 3409 case ARM::VST2q8wb_fixed: 3410 case ARM::VST2q16wb_fixed: 3411 case ARM::VST2q32wb_fixed: 3412 case ARM::VST2b8wb_fixed: 3413 case ARM::VST2b16wb_fixed: 3414 case ARM::VST2b32wb_fixed: 3415 break; 3416 } 3417 3418 // First input register 3419 switch (Inst.getOpcode()) { 3420 case ARM::VST1q16: 3421 case ARM::VST1q32: 3422 case ARM::VST1q64: 3423 case ARM::VST1q8: 3424 case ARM::VST1q16wb_fixed: 3425 case ARM::VST1q16wb_register: 3426 case ARM::VST1q32wb_fixed: 3427 case ARM::VST1q32wb_register: 3428 case ARM::VST1q64wb_fixed: 3429 case ARM::VST1q64wb_register: 3430 case ARM::VST1q8wb_fixed: 3431 case ARM::VST1q8wb_register: 3432 case ARM::VST2d16: 3433 case ARM::VST2d32: 3434 case ARM::VST2d8: 3435 case ARM::VST2d16wb_fixed: 3436 case ARM::VST2d16wb_register: 3437 case ARM::VST2d32wb_fixed: 3438 case ARM::VST2d32wb_register: 3439 case ARM::VST2d8wb_fixed: 3440 case ARM::VST2d8wb_register: 3441 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3442 return MCDisassembler::Fail; 3443 break; 3444 case ARM::VST2b16: 3445 case ARM::VST2b32: 3446 case ARM::VST2b8: 3447 case ARM::VST2b16wb_fixed: 3448 case ARM::VST2b16wb_register: 3449 case ARM::VST2b32wb_fixed: 3450 case ARM::VST2b32wb_register: 3451 case ARM::VST2b8wb_fixed: 3452 case ARM::VST2b8wb_register: 3453 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 3454 return MCDisassembler::Fail; 3455 break; 3456 default: 3457 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3458 return MCDisassembler::Fail; 3459 } 3460 3461 // Second input register 3462 switch (Inst.getOpcode()) { 3463 case ARM::VST3d8: 3464 case ARM::VST3d16: 3465 case ARM::VST3d32: 3466 case ARM::VST3d8_UPD: 3467 case ARM::VST3d16_UPD: 3468 case ARM::VST3d32_UPD: 3469 case ARM::VST4d8: 3470 case ARM::VST4d16: 3471 case ARM::VST4d32: 3472 case ARM::VST4d8_UPD: 3473 case ARM::VST4d16_UPD: 3474 case ARM::VST4d32_UPD: 3475 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 3476 return MCDisassembler::Fail; 3477 break; 3478 case ARM::VST3q8: 3479 case ARM::VST3q16: 3480 case ARM::VST3q32: 3481 case ARM::VST3q8_UPD: 3482 case ARM::VST3q16_UPD: 3483 case ARM::VST3q32_UPD: 3484 case ARM::VST4q8: 3485 case ARM::VST4q16: 3486 case ARM::VST4q32: 3487 case ARM::VST4q8_UPD: 3488 case ARM::VST4q16_UPD: 3489 case ARM::VST4q32_UPD: 3490 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3491 return MCDisassembler::Fail; 3492 break; 3493 default: 3494 break; 3495 } 3496 3497 // Third input register 3498 switch (Inst.getOpcode()) { 3499 case ARM::VST3d8: 3500 case ARM::VST3d16: 3501 case ARM::VST3d32: 3502 case ARM::VST3d8_UPD: 3503 case ARM::VST3d16_UPD: 3504 case ARM::VST3d32_UPD: 3505 case ARM::VST4d8: 3506 case ARM::VST4d16: 3507 case ARM::VST4d32: 3508 case ARM::VST4d8_UPD: 3509 case ARM::VST4d16_UPD: 3510 case ARM::VST4d32_UPD: 3511 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 3512 return MCDisassembler::Fail; 3513 break; 3514 case ARM::VST3q8: 3515 case ARM::VST3q16: 3516 case ARM::VST3q32: 3517 case ARM::VST3q8_UPD: 3518 case ARM::VST3q16_UPD: 3519 case ARM::VST3q32_UPD: 3520 case ARM::VST4q8: 3521 case ARM::VST4q16: 3522 case ARM::VST4q32: 3523 case ARM::VST4q8_UPD: 3524 case ARM::VST4q16_UPD: 3525 case ARM::VST4q32_UPD: 3526 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 3527 return MCDisassembler::Fail; 3528 break; 3529 default: 3530 break; 3531 } 3532 3533 // Fourth input register 3534 switch (Inst.getOpcode()) { 3535 case ARM::VST4d8: 3536 case ARM::VST4d16: 3537 case ARM::VST4d32: 3538 case ARM::VST4d8_UPD: 3539 case ARM::VST4d16_UPD: 3540 case ARM::VST4d32_UPD: 3541 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 3542 return MCDisassembler::Fail; 3543 break; 3544 case ARM::VST4q8: 3545 case ARM::VST4q16: 3546 case ARM::VST4q32: 3547 case ARM::VST4q8_UPD: 3548 case ARM::VST4q16_UPD: 3549 case ARM::VST4q32_UPD: 3550 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 3551 return MCDisassembler::Fail; 3552 break; 3553 default: 3554 break; 3555 } 3556 3557 return S; 3558} 3559 3560static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 3561 uint64_t Address, 3562 const MCDisassembler *Decoder) { 3563 DecodeStatus S = MCDisassembler::Success; 3564 3565 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3566 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3567 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3568 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3569 unsigned align = fieldFromInstruction(Insn, 4, 1); 3570 unsigned size = fieldFromInstruction(Insn, 6, 2); 3571 3572 if (size == 0 && align == 1) 3573 return MCDisassembler::Fail; 3574 align *= (1 << size); 3575 3576 switch (Inst.getOpcode()) { 3577 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 3578 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 3579 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 3580 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 3581 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3582 return MCDisassembler::Fail; 3583 break; 3584 default: 3585 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3586 return MCDisassembler::Fail; 3587 break; 3588 } 3589 if (Rm != 0xF) { 3590 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3591 return MCDisassembler::Fail; 3592 } 3593 3594 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3595 return MCDisassembler::Fail; 3596 Inst.addOperand(MCOperand::createImm(align)); 3597 3598 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 3599 // variant encodes Rm == 0xf. Anything else is a register offset post- 3600 // increment and we need to add the register operand to the instruction. 3601 if (Rm != 0xD && Rm != 0xF && 3602 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3603 return MCDisassembler::Fail; 3604 3605 return S; 3606} 3607 3608static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 3609 uint64_t Address, 3610 const MCDisassembler *Decoder) { 3611 DecodeStatus S = MCDisassembler::Success; 3612 3613 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3614 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3615 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3616 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3617 unsigned align = fieldFromInstruction(Insn, 4, 1); 3618 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2); 3619 align *= 2*size; 3620 3621 switch (Inst.getOpcode()) { 3622 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 3623 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 3624 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 3625 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 3626 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 3627 return MCDisassembler::Fail; 3628 break; 3629 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 3630 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 3631 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 3632 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 3633 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 3634 return MCDisassembler::Fail; 3635 break; 3636 default: 3637 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3638 return MCDisassembler::Fail; 3639 break; 3640 } 3641 3642 if (Rm != 0xF) 3643 Inst.addOperand(MCOperand::createImm(0)); 3644 3645 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3646 return MCDisassembler::Fail; 3647 Inst.addOperand(MCOperand::createImm(align)); 3648 3649 if (Rm != 0xD && Rm != 0xF) { 3650 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3651 return MCDisassembler::Fail; 3652 } 3653 3654 return S; 3655} 3656 3657static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 3658 uint64_t Address, 3659 const MCDisassembler *Decoder) { 3660 DecodeStatus S = MCDisassembler::Success; 3661 3662 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3663 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3664 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3665 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3666 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3667 3668 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3669 return MCDisassembler::Fail; 3670 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3671 return MCDisassembler::Fail; 3672 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3673 return MCDisassembler::Fail; 3674 if (Rm != 0xF) { 3675 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3676 return MCDisassembler::Fail; 3677 } 3678 3679 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3680 return MCDisassembler::Fail; 3681 Inst.addOperand(MCOperand::createImm(0)); 3682 3683 if (Rm == 0xD) 3684 Inst.addOperand(MCOperand::createReg(0)); 3685 else if (Rm != 0xF) { 3686 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3687 return MCDisassembler::Fail; 3688 } 3689 3690 return S; 3691} 3692 3693static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 3694 uint64_t Address, 3695 const MCDisassembler *Decoder) { 3696 DecodeStatus S = MCDisassembler::Success; 3697 3698 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3699 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3700 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3701 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3702 unsigned size = fieldFromInstruction(Insn, 6, 2); 3703 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 3704 unsigned align = fieldFromInstruction(Insn, 4, 1); 3705 3706 if (size == 0x3) { 3707 if (align == 0) 3708 return MCDisassembler::Fail; 3709 align = 16; 3710 } else { 3711 if (size == 2) { 3712 align *= 8; 3713 } else { 3714 size = 1 << size; 3715 align *= 4*size; 3716 } 3717 } 3718 3719 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3720 return MCDisassembler::Fail; 3721 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 3722 return MCDisassembler::Fail; 3723 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 3724 return MCDisassembler::Fail; 3725 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 3726 return MCDisassembler::Fail; 3727 if (Rm != 0xF) { 3728 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3729 return MCDisassembler::Fail; 3730 } 3731 3732 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3733 return MCDisassembler::Fail; 3734 Inst.addOperand(MCOperand::createImm(align)); 3735 3736 if (Rm == 0xD) 3737 Inst.addOperand(MCOperand::createReg(0)); 3738 else if (Rm != 0xF) { 3739 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3740 return MCDisassembler::Fail; 3741 } 3742 3743 return S; 3744} 3745 3746static DecodeStatus DecodeVMOVModImmInstruction(MCInst &Inst, unsigned Insn, 3747 uint64_t Address, 3748 const MCDisassembler *Decoder) { 3749 DecodeStatus S = MCDisassembler::Success; 3750 3751 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3752 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3753 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3754 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3755 imm |= fieldFromInstruction(Insn, 24, 1) << 7; 3756 imm |= fieldFromInstruction(Insn, 8, 4) << 8; 3757 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3758 unsigned Q = fieldFromInstruction(Insn, 6, 1); 3759 3760 if (Q) { 3761 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3762 return MCDisassembler::Fail; 3763 } else { 3764 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3765 return MCDisassembler::Fail; 3766 } 3767 3768 Inst.addOperand(MCOperand::createImm(imm)); 3769 3770 switch (Inst.getOpcode()) { 3771 case ARM::VORRiv4i16: 3772 case ARM::VORRiv2i32: 3773 case ARM::VBICiv4i16: 3774 case ARM::VBICiv2i32: 3775 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3776 return MCDisassembler::Fail; 3777 break; 3778 case ARM::VORRiv8i16: 3779 case ARM::VORRiv4i32: 3780 case ARM::VBICiv8i16: 3781 case ARM::VBICiv4i32: 3782 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3783 return MCDisassembler::Fail; 3784 break; 3785 default: 3786 break; 3787 } 3788 3789 return S; 3790} 3791 3792static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst, unsigned Insn, 3793 uint64_t Address, 3794 const MCDisassembler *Decoder) { 3795 DecodeStatus S = MCDisassembler::Success; 3796 3797 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 3798 fieldFromInstruction(Insn, 13, 3)); 3799 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 3800 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3801 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3802 imm |= fieldFromInstruction(Insn, 28, 1) << 7; 3803 imm |= cmode << 8; 3804 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3805 3806 if (cmode == 0xF && Inst.getOpcode() == ARM::MVE_VMVNimmi32) 3807 return MCDisassembler::Fail; 3808 3809 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 3810 return MCDisassembler::Fail; 3811 3812 Inst.addOperand(MCOperand::createImm(imm)); 3813 3814 Inst.addOperand(MCOperand::createImm(ARMVCC::None)); 3815 Inst.addOperand(MCOperand::createReg(0)); 3816 Inst.addOperand(MCOperand::createImm(0)); 3817 3818 return S; 3819} 3820 3821static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn, 3822 uint64_t Address, 3823 const MCDisassembler *Decoder) { 3824 DecodeStatus S = MCDisassembler::Success; 3825 3826 unsigned Qd = fieldFromInstruction(Insn, 13, 3); 3827 Qd |= fieldFromInstruction(Insn, 22, 1) << 3; 3828 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 3829 return MCDisassembler::Fail; 3830 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 3831 3832 unsigned Qn = fieldFromInstruction(Insn, 17, 3); 3833 Qn |= fieldFromInstruction(Insn, 7, 1) << 3; 3834 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder))) 3835 return MCDisassembler::Fail; 3836 unsigned Qm = fieldFromInstruction(Insn, 1, 3); 3837 Qm |= fieldFromInstruction(Insn, 5, 1) << 3; 3838 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 3839 return MCDisassembler::Fail; 3840 if (!fieldFromInstruction(Insn, 12, 1)) // I bit clear => need input FPSCR 3841 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 3842 Inst.addOperand(MCOperand::createImm(Qd)); 3843 3844 return S; 3845} 3846 3847static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 3848 uint64_t Address, 3849 const MCDisassembler *Decoder) { 3850 DecodeStatus S = MCDisassembler::Success; 3851 3852 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3853 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3854 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3855 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3856 unsigned size = fieldFromInstruction(Insn, 18, 2); 3857 3858 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3859 return MCDisassembler::Fail; 3860 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3861 return MCDisassembler::Fail; 3862 Inst.addOperand(MCOperand::createImm(8 << size)); 3863 3864 return S; 3865} 3866 3867static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 3868 uint64_t Address, 3869 const MCDisassembler *Decoder) { 3870 Inst.addOperand(MCOperand::createImm(8 - Val)); 3871 return MCDisassembler::Success; 3872} 3873 3874static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 3875 uint64_t Address, 3876 const MCDisassembler *Decoder) { 3877 Inst.addOperand(MCOperand::createImm(16 - Val)); 3878 return MCDisassembler::Success; 3879} 3880 3881static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 3882 uint64_t Address, 3883 const MCDisassembler *Decoder) { 3884 Inst.addOperand(MCOperand::createImm(32 - Val)); 3885 return MCDisassembler::Success; 3886} 3887 3888static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 3889 uint64_t Address, 3890 const MCDisassembler *Decoder) { 3891 Inst.addOperand(MCOperand::createImm(64 - Val)); 3892 return MCDisassembler::Success; 3893} 3894 3895static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 3896 uint64_t Address, 3897 const MCDisassembler *Decoder) { 3898 DecodeStatus S = MCDisassembler::Success; 3899 3900 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3901 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3902 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3903 Rn |= fieldFromInstruction(Insn, 7, 1) << 4; 3904 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3905 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3906 unsigned op = fieldFromInstruction(Insn, 6, 1); 3907 3908 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3909 return MCDisassembler::Fail; 3910 if (op) { 3911 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3912 return MCDisassembler::Fail; // Writeback 3913 } 3914 3915 switch (Inst.getOpcode()) { 3916 case ARM::VTBL2: 3917 case ARM::VTBX2: 3918 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 3919 return MCDisassembler::Fail; 3920 break; 3921 default: 3922 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 3923 return MCDisassembler::Fail; 3924 } 3925 3926 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3927 return MCDisassembler::Fail; 3928 3929 return S; 3930} 3931 3932static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 3933 uint64_t Address, 3934 const MCDisassembler *Decoder) { 3935 DecodeStatus S = MCDisassembler::Success; 3936 3937 unsigned dst = fieldFromInstruction(Insn, 8, 3); 3938 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3939 3940 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 3941 return MCDisassembler::Fail; 3942 3943 switch(Inst.getOpcode()) { 3944 default: 3945 return MCDisassembler::Fail; 3946 case ARM::tADR: 3947 break; // tADR does not explicitly represent the PC as an operand. 3948 case ARM::tADDrSPi: 3949 Inst.addOperand(MCOperand::createReg(ARM::SP)); 3950 break; 3951 } 3952 3953 Inst.addOperand(MCOperand::createImm(imm)); 3954 return S; 3955} 3956 3957static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 3958 uint64_t Address, 3959 const MCDisassembler *Decoder) { 3960 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, 3961 true, 2, Inst, Decoder)) 3962 Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1))); 3963 return MCDisassembler::Success; 3964} 3965 3966static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 3967 uint64_t Address, 3968 const MCDisassembler *Decoder) { 3969 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4, 3970 true, 4, Inst, Decoder)) 3971 Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val))); 3972 return MCDisassembler::Success; 3973} 3974 3975static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 3976 uint64_t Address, 3977 const MCDisassembler *Decoder) { 3978 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4, 3979 true, 2, Inst, Decoder)) 3980 Inst.addOperand(MCOperand::createImm(Val << 1)); 3981 return MCDisassembler::Success; 3982} 3983 3984static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 3985 uint64_t Address, 3986 const MCDisassembler *Decoder) { 3987 DecodeStatus S = MCDisassembler::Success; 3988 3989 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3990 unsigned Rm = fieldFromInstruction(Val, 3, 3); 3991 3992 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3993 return MCDisassembler::Fail; 3994 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 3995 return MCDisassembler::Fail; 3996 3997 return S; 3998} 3999 4000static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 4001 uint64_t Address, 4002 const MCDisassembler *Decoder) { 4003 DecodeStatus S = MCDisassembler::Success; 4004 4005 unsigned Rn = fieldFromInstruction(Val, 0, 3); 4006 unsigned imm = fieldFromInstruction(Val, 3, 5); 4007 4008 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 4009 return MCDisassembler::Fail; 4010 Inst.addOperand(MCOperand::createImm(imm)); 4011 4012 return S; 4013} 4014 4015static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 4016 uint64_t Address, 4017 const MCDisassembler *Decoder) { 4018 unsigned imm = Val << 2; 4019 4020 Inst.addOperand(MCOperand::createImm(imm)); 4021 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 4022 4023 return MCDisassembler::Success; 4024} 4025 4026static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 4027 uint64_t Address, 4028 const MCDisassembler *Decoder) { 4029 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4030 Inst.addOperand(MCOperand::createImm(Val)); 4031 4032 return MCDisassembler::Success; 4033} 4034 4035static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 4036 uint64_t Address, 4037 const MCDisassembler *Decoder) { 4038 DecodeStatus S = MCDisassembler::Success; 4039 4040 unsigned Rn = fieldFromInstruction(Val, 6, 4); 4041 unsigned Rm = fieldFromInstruction(Val, 2, 4); 4042 unsigned imm = fieldFromInstruction(Val, 0, 2); 4043 4044 // Thumb stores cannot use PC as dest register. 4045 switch (Inst.getOpcode()) { 4046 case ARM::t2STRHs: 4047 case ARM::t2STRBs: 4048 case ARM::t2STRs: 4049 if (Rn == 15) 4050 return MCDisassembler::Fail; 4051 break; 4052 default: 4053 break; 4054 } 4055 4056 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4057 return MCDisassembler::Fail; 4058 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 4059 return MCDisassembler::Fail; 4060 Inst.addOperand(MCOperand::createImm(imm)); 4061 4062 return S; 4063} 4064 4065static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 4066 uint64_t Address, 4067 const MCDisassembler *Decoder) { 4068 DecodeStatus S = MCDisassembler::Success; 4069 4070 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4071 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4072 4073 const FeatureBitset &featureBits = 4074 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4075 4076 bool hasMP = featureBits[ARM::FeatureMP]; 4077 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 4078 4079 if (Rn == 15) { 4080 switch (Inst.getOpcode()) { 4081 case ARM::t2LDRBs: 4082 Inst.setOpcode(ARM::t2LDRBpci); 4083 break; 4084 case ARM::t2LDRHs: 4085 Inst.setOpcode(ARM::t2LDRHpci); 4086 break; 4087 case ARM::t2LDRSHs: 4088 Inst.setOpcode(ARM::t2LDRSHpci); 4089 break; 4090 case ARM::t2LDRSBs: 4091 Inst.setOpcode(ARM::t2LDRSBpci); 4092 break; 4093 case ARM::t2LDRs: 4094 Inst.setOpcode(ARM::t2LDRpci); 4095 break; 4096 case ARM::t2PLDs: 4097 Inst.setOpcode(ARM::t2PLDpci); 4098 break; 4099 case ARM::t2PLIs: 4100 Inst.setOpcode(ARM::t2PLIpci); 4101 break; 4102 default: 4103 return MCDisassembler::Fail; 4104 } 4105 4106 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4107 } 4108 4109 if (Rt == 15) { 4110 switch (Inst.getOpcode()) { 4111 case ARM::t2LDRSHs: 4112 return MCDisassembler::Fail; 4113 case ARM::t2LDRHs: 4114 Inst.setOpcode(ARM::t2PLDWs); 4115 break; 4116 case ARM::t2LDRSBs: 4117 Inst.setOpcode(ARM::t2PLIs); 4118 break; 4119 default: 4120 break; 4121 } 4122 } 4123 4124 switch (Inst.getOpcode()) { 4125 case ARM::t2PLDs: 4126 break; 4127 case ARM::t2PLIs: 4128 if (!hasV7Ops) 4129 return MCDisassembler::Fail; 4130 break; 4131 case ARM::t2PLDWs: 4132 if (!hasV7Ops || !hasMP) 4133 return MCDisassembler::Fail; 4134 break; 4135 default: 4136 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4137 return MCDisassembler::Fail; 4138 } 4139 4140 unsigned addrmode = fieldFromInstruction(Insn, 4, 2); 4141 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2; 4142 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6; 4143 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 4144 return MCDisassembler::Fail; 4145 4146 return S; 4147} 4148 4149static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 4150 uint64_t Address, 4151 const MCDisassembler *Decoder) { 4152 DecodeStatus S = MCDisassembler::Success; 4153 4154 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4155 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4156 unsigned U = fieldFromInstruction(Insn, 9, 1); 4157 unsigned imm = fieldFromInstruction(Insn, 0, 8); 4158 imm |= (U << 8); 4159 imm |= (Rn << 9); 4160 unsigned add = fieldFromInstruction(Insn, 9, 1); 4161 4162 const FeatureBitset &featureBits = 4163 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4164 4165 bool hasMP = featureBits[ARM::FeatureMP]; 4166 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 4167 4168 if (Rn == 15) { 4169 switch (Inst.getOpcode()) { 4170 case ARM::t2LDRi8: 4171 Inst.setOpcode(ARM::t2LDRpci); 4172 break; 4173 case ARM::t2LDRBi8: 4174 Inst.setOpcode(ARM::t2LDRBpci); 4175 break; 4176 case ARM::t2LDRSBi8: 4177 Inst.setOpcode(ARM::t2LDRSBpci); 4178 break; 4179 case ARM::t2LDRHi8: 4180 Inst.setOpcode(ARM::t2LDRHpci); 4181 break; 4182 case ARM::t2LDRSHi8: 4183 Inst.setOpcode(ARM::t2LDRSHpci); 4184 break; 4185 case ARM::t2PLDi8: 4186 Inst.setOpcode(ARM::t2PLDpci); 4187 break; 4188 case ARM::t2PLIi8: 4189 Inst.setOpcode(ARM::t2PLIpci); 4190 break; 4191 default: 4192 return MCDisassembler::Fail; 4193 } 4194 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4195 } 4196 4197 if (Rt == 15) { 4198 switch (Inst.getOpcode()) { 4199 case ARM::t2LDRSHi8: 4200 return MCDisassembler::Fail; 4201 case ARM::t2LDRHi8: 4202 if (!add) 4203 Inst.setOpcode(ARM::t2PLDWi8); 4204 break; 4205 case ARM::t2LDRSBi8: 4206 Inst.setOpcode(ARM::t2PLIi8); 4207 break; 4208 default: 4209 break; 4210 } 4211 } 4212 4213 switch (Inst.getOpcode()) { 4214 case ARM::t2PLDi8: 4215 break; 4216 case ARM::t2PLIi8: 4217 if (!hasV7Ops) 4218 return MCDisassembler::Fail; 4219 break; 4220 case ARM::t2PLDWi8: 4221 if (!hasV7Ops || !hasMP) 4222 return MCDisassembler::Fail; 4223 break; 4224 default: 4225 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4226 return MCDisassembler::Fail; 4227 } 4228 4229 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 4230 return MCDisassembler::Fail; 4231 return S; 4232} 4233 4234static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 4235 uint64_t Address, 4236 const MCDisassembler *Decoder) { 4237 DecodeStatus S = MCDisassembler::Success; 4238 4239 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4240 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4241 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4242 imm |= (Rn << 13); 4243 4244 const FeatureBitset &featureBits = 4245 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4246 4247 bool hasMP = featureBits[ARM::FeatureMP]; 4248 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 4249 4250 if (Rn == 15) { 4251 switch (Inst.getOpcode()) { 4252 case ARM::t2LDRi12: 4253 Inst.setOpcode(ARM::t2LDRpci); 4254 break; 4255 case ARM::t2LDRHi12: 4256 Inst.setOpcode(ARM::t2LDRHpci); 4257 break; 4258 case ARM::t2LDRSHi12: 4259 Inst.setOpcode(ARM::t2LDRSHpci); 4260 break; 4261 case ARM::t2LDRBi12: 4262 Inst.setOpcode(ARM::t2LDRBpci); 4263 break; 4264 case ARM::t2LDRSBi12: 4265 Inst.setOpcode(ARM::t2LDRSBpci); 4266 break; 4267 case ARM::t2PLDi12: 4268 Inst.setOpcode(ARM::t2PLDpci); 4269 break; 4270 case ARM::t2PLIi12: 4271 Inst.setOpcode(ARM::t2PLIpci); 4272 break; 4273 default: 4274 return MCDisassembler::Fail; 4275 } 4276 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4277 } 4278 4279 if (Rt == 15) { 4280 switch (Inst.getOpcode()) { 4281 case ARM::t2LDRSHi12: 4282 return MCDisassembler::Fail; 4283 case ARM::t2LDRHi12: 4284 Inst.setOpcode(ARM::t2PLDWi12); 4285 break; 4286 case ARM::t2LDRSBi12: 4287 Inst.setOpcode(ARM::t2PLIi12); 4288 break; 4289 default: 4290 break; 4291 } 4292 } 4293 4294 switch (Inst.getOpcode()) { 4295 case ARM::t2PLDi12: 4296 break; 4297 case ARM::t2PLIi12: 4298 if (!hasV7Ops) 4299 return MCDisassembler::Fail; 4300 break; 4301 case ARM::t2PLDWi12: 4302 if (!hasV7Ops || !hasMP) 4303 return MCDisassembler::Fail; 4304 break; 4305 default: 4306 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4307 return MCDisassembler::Fail; 4308 } 4309 4310 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder))) 4311 return MCDisassembler::Fail; 4312 return S; 4313} 4314 4315static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, uint64_t Address, 4316 const MCDisassembler *Decoder) { 4317 DecodeStatus S = MCDisassembler::Success; 4318 4319 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4320 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4321 unsigned imm = fieldFromInstruction(Insn, 0, 8); 4322 imm |= (Rn << 9); 4323 4324 if (Rn == 15) { 4325 switch (Inst.getOpcode()) { 4326 case ARM::t2LDRT: 4327 Inst.setOpcode(ARM::t2LDRpci); 4328 break; 4329 case ARM::t2LDRBT: 4330 Inst.setOpcode(ARM::t2LDRBpci); 4331 break; 4332 case ARM::t2LDRHT: 4333 Inst.setOpcode(ARM::t2LDRHpci); 4334 break; 4335 case ARM::t2LDRSBT: 4336 Inst.setOpcode(ARM::t2LDRSBpci); 4337 break; 4338 case ARM::t2LDRSHT: 4339 Inst.setOpcode(ARM::t2LDRSHpci); 4340 break; 4341 default: 4342 return MCDisassembler::Fail; 4343 } 4344 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4345 } 4346 4347 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4348 return MCDisassembler::Fail; 4349 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 4350 return MCDisassembler::Fail; 4351 return S; 4352} 4353 4354static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 4355 uint64_t Address, 4356 const MCDisassembler *Decoder) { 4357 DecodeStatus S = MCDisassembler::Success; 4358 4359 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4360 unsigned U = fieldFromInstruction(Insn, 23, 1); 4361 int imm = fieldFromInstruction(Insn, 0, 12); 4362 4363 const FeatureBitset &featureBits = 4364 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4365 4366 bool hasV7Ops = featureBits[ARM::HasV7Ops]; 4367 4368 if (Rt == 15) { 4369 switch (Inst.getOpcode()) { 4370 case ARM::t2LDRBpci: 4371 case ARM::t2LDRHpci: 4372 Inst.setOpcode(ARM::t2PLDpci); 4373 break; 4374 case ARM::t2LDRSBpci: 4375 Inst.setOpcode(ARM::t2PLIpci); 4376 break; 4377 case ARM::t2LDRSHpci: 4378 return MCDisassembler::Fail; 4379 default: 4380 break; 4381 } 4382 } 4383 4384 switch(Inst.getOpcode()) { 4385 case ARM::t2PLDpci: 4386 break; 4387 case ARM::t2PLIpci: 4388 if (!hasV7Ops) 4389 return MCDisassembler::Fail; 4390 break; 4391 default: 4392 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4393 return MCDisassembler::Fail; 4394 } 4395 4396 if (!U) { 4397 // Special case for #-0. 4398 if (imm == 0) 4399 imm = INT32_MIN; 4400 else 4401 imm = -imm; 4402 } 4403 Inst.addOperand(MCOperand::createImm(imm)); 4404 4405 return S; 4406} 4407 4408static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, uint64_t Address, 4409 const MCDisassembler *Decoder) { 4410 if (Val == 0) 4411 Inst.addOperand(MCOperand::createImm(INT32_MIN)); 4412 else { 4413 int imm = Val & 0xFF; 4414 4415 if (!(Val & 0x100)) imm *= -1; 4416 Inst.addOperand(MCOperand::createImm(imm * 4)); 4417 } 4418 4419 return MCDisassembler::Success; 4420} 4421 4422static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address, 4423 const MCDisassembler *Decoder) { 4424 if (Val == 0) 4425 Inst.addOperand(MCOperand::createImm(INT32_MIN)); 4426 else { 4427 int imm = Val & 0x7F; 4428 4429 if (!(Val & 0x80)) 4430 imm *= -1; 4431 Inst.addOperand(MCOperand::createImm(imm * 4)); 4432 } 4433 4434 return MCDisassembler::Success; 4435} 4436 4437static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 4438 uint64_t Address, 4439 const MCDisassembler *Decoder) { 4440 DecodeStatus S = MCDisassembler::Success; 4441 4442 unsigned Rn = fieldFromInstruction(Val, 9, 4); 4443 unsigned imm = fieldFromInstruction(Val, 0, 9); 4444 4445 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4446 return MCDisassembler::Fail; 4447 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 4448 return MCDisassembler::Fail; 4449 4450 return S; 4451} 4452 4453static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val, 4454 uint64_t Address, 4455 const MCDisassembler *Decoder) { 4456 DecodeStatus S = MCDisassembler::Success; 4457 4458 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4459 unsigned imm = fieldFromInstruction(Val, 0, 8); 4460 4461 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4462 return MCDisassembler::Fail; 4463 if (!Check(S, DecodeT2Imm7S4(Inst, imm, Address, Decoder))) 4464 return MCDisassembler::Fail; 4465 4466 return S; 4467} 4468 4469static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst, unsigned Val, 4470 uint64_t Address, 4471 const MCDisassembler *Decoder) { 4472 DecodeStatus S = MCDisassembler::Success; 4473 4474 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4475 unsigned imm = fieldFromInstruction(Val, 0, 8); 4476 4477 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4478 return MCDisassembler::Fail; 4479 4480 Inst.addOperand(MCOperand::createImm(imm)); 4481 4482 return S; 4483} 4484 4485static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, uint64_t Address, 4486 const MCDisassembler *Decoder) { 4487 int imm = Val & 0xFF; 4488 if (Val == 0) 4489 imm = INT32_MIN; 4490 else if (!(Val & 0x100)) 4491 imm *= -1; 4492 Inst.addOperand(MCOperand::createImm(imm)); 4493 4494 return MCDisassembler::Success; 4495} 4496 4497template <int shift> 4498static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, uint64_t Address, 4499 const MCDisassembler *Decoder) { 4500 int imm = Val & 0x7F; 4501 if (Val == 0) 4502 imm = INT32_MIN; 4503 else if (!(Val & 0x80)) 4504 imm *= -1; 4505 if (imm != INT32_MIN) 4506 imm *= (1U << shift); 4507 Inst.addOperand(MCOperand::createImm(imm)); 4508 4509 return MCDisassembler::Success; 4510} 4511 4512static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 4513 uint64_t Address, 4514 const MCDisassembler *Decoder) { 4515 DecodeStatus S = MCDisassembler::Success; 4516 4517 unsigned Rn = fieldFromInstruction(Val, 9, 4); 4518 unsigned imm = fieldFromInstruction(Val, 0, 9); 4519 4520 // Thumb stores cannot use PC as dest register. 4521 switch (Inst.getOpcode()) { 4522 case ARM::t2STRT: 4523 case ARM::t2STRBT: 4524 case ARM::t2STRHT: 4525 case ARM::t2STRi8: 4526 case ARM::t2STRHi8: 4527 case ARM::t2STRBi8: 4528 if (Rn == 15) 4529 return MCDisassembler::Fail; 4530 break; 4531 default: 4532 break; 4533 } 4534 4535 // Some instructions always use an additive offset. 4536 switch (Inst.getOpcode()) { 4537 case ARM::t2LDRT: 4538 case ARM::t2LDRBT: 4539 case ARM::t2LDRHT: 4540 case ARM::t2LDRSBT: 4541 case ARM::t2LDRSHT: 4542 case ARM::t2STRT: 4543 case ARM::t2STRBT: 4544 case ARM::t2STRHT: 4545 imm |= 0x100; 4546 break; 4547 default: 4548 break; 4549 } 4550 4551 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4552 return MCDisassembler::Fail; 4553 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 4554 return MCDisassembler::Fail; 4555 4556 return S; 4557} 4558 4559template <int shift> 4560static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val, 4561 uint64_t Address, 4562 const MCDisassembler *Decoder) { 4563 DecodeStatus S = MCDisassembler::Success; 4564 4565 unsigned Rn = fieldFromInstruction(Val, 8, 3); 4566 unsigned imm = fieldFromInstruction(Val, 0, 8); 4567 4568 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 4569 return MCDisassembler::Fail; 4570 if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder))) 4571 return MCDisassembler::Fail; 4572 4573 return S; 4574} 4575 4576template <int shift, int WriteBack> 4577static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val, 4578 uint64_t Address, 4579 const MCDisassembler *Decoder) { 4580 DecodeStatus S = MCDisassembler::Success; 4581 4582 unsigned Rn = fieldFromInstruction(Val, 8, 4); 4583 unsigned imm = fieldFromInstruction(Val, 0, 8); 4584 if (WriteBack) { 4585 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4586 return MCDisassembler::Fail; 4587 } else if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4588 return MCDisassembler::Fail; 4589 if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder))) 4590 return MCDisassembler::Fail; 4591 4592 return S; 4593} 4594 4595static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 4596 uint64_t Address, 4597 const MCDisassembler *Decoder) { 4598 DecodeStatus S = MCDisassembler::Success; 4599 4600 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4601 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4602 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4603 addr |= fieldFromInstruction(Insn, 9, 1) << 8; 4604 addr |= Rn << 9; 4605 unsigned load = fieldFromInstruction(Insn, 20, 1); 4606 4607 if (Rn == 15) { 4608 switch (Inst.getOpcode()) { 4609 case ARM::t2LDR_PRE: 4610 case ARM::t2LDR_POST: 4611 Inst.setOpcode(ARM::t2LDRpci); 4612 break; 4613 case ARM::t2LDRB_PRE: 4614 case ARM::t2LDRB_POST: 4615 Inst.setOpcode(ARM::t2LDRBpci); 4616 break; 4617 case ARM::t2LDRH_PRE: 4618 case ARM::t2LDRH_POST: 4619 Inst.setOpcode(ARM::t2LDRHpci); 4620 break; 4621 case ARM::t2LDRSB_PRE: 4622 case ARM::t2LDRSB_POST: 4623 if (Rt == 15) 4624 Inst.setOpcode(ARM::t2PLIpci); 4625 else 4626 Inst.setOpcode(ARM::t2LDRSBpci); 4627 break; 4628 case ARM::t2LDRSH_PRE: 4629 case ARM::t2LDRSH_POST: 4630 Inst.setOpcode(ARM::t2LDRSHpci); 4631 break; 4632 default: 4633 return MCDisassembler::Fail; 4634 } 4635 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 4636 } 4637 4638 if (!load) { 4639 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4640 return MCDisassembler::Fail; 4641 } 4642 4643 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4644 return MCDisassembler::Fail; 4645 4646 if (load) { 4647 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4648 return MCDisassembler::Fail; 4649 } 4650 4651 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 4652 return MCDisassembler::Fail; 4653 4654 return S; 4655} 4656 4657static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 4658 uint64_t Address, 4659 const MCDisassembler *Decoder) { 4660 DecodeStatus S = MCDisassembler::Success; 4661 4662 unsigned Rn = fieldFromInstruction(Val, 13, 4); 4663 unsigned imm = fieldFromInstruction(Val, 0, 12); 4664 4665 // Thumb stores cannot use PC as dest register. 4666 switch (Inst.getOpcode()) { 4667 case ARM::t2STRi12: 4668 case ARM::t2STRBi12: 4669 case ARM::t2STRHi12: 4670 if (Rn == 15) 4671 return MCDisassembler::Fail; 4672 break; 4673 default: 4674 break; 4675 } 4676 4677 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4678 return MCDisassembler::Fail; 4679 Inst.addOperand(MCOperand::createImm(imm)); 4680 4681 return S; 4682} 4683 4684static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 4685 uint64_t Address, 4686 const MCDisassembler *Decoder) { 4687 unsigned imm = fieldFromInstruction(Insn, 0, 7); 4688 4689 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4690 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4691 Inst.addOperand(MCOperand::createImm(imm)); 4692 4693 return MCDisassembler::Success; 4694} 4695 4696static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 4697 uint64_t Address, 4698 const MCDisassembler *Decoder) { 4699 DecodeStatus S = MCDisassembler::Success; 4700 4701 if (Inst.getOpcode() == ARM::tADDrSP) { 4702 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); 4703 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; 4704 4705 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 4706 return MCDisassembler::Fail; 4707 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4708 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 4709 return MCDisassembler::Fail; 4710 } else if (Inst.getOpcode() == ARM::tADDspr) { 4711 unsigned Rm = fieldFromInstruction(Insn, 3, 4); 4712 4713 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4714 Inst.addOperand(MCOperand::createReg(ARM::SP)); 4715 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4716 return MCDisassembler::Fail; 4717 } 4718 4719 return S; 4720} 4721 4722static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 4723 uint64_t Address, 4724 const MCDisassembler *Decoder) { 4725 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; 4726 unsigned flags = fieldFromInstruction(Insn, 0, 3); 4727 4728 Inst.addOperand(MCOperand::createImm(imod)); 4729 Inst.addOperand(MCOperand::createImm(flags)); 4730 4731 return MCDisassembler::Success; 4732} 4733 4734static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 4735 uint64_t Address, 4736 const MCDisassembler *Decoder) { 4737 DecodeStatus S = MCDisassembler::Success; 4738 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4739 unsigned add = fieldFromInstruction(Insn, 4, 1); 4740 4741 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 4742 return MCDisassembler::Fail; 4743 Inst.addOperand(MCOperand::createImm(add)); 4744 4745 return S; 4746} 4747 4748static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn, 4749 uint64_t Address, 4750 const MCDisassembler *Decoder) { 4751 DecodeStatus S = MCDisassembler::Success; 4752 unsigned Rn = fieldFromInstruction(Insn, 3, 4); 4753 unsigned Qm = fieldFromInstruction(Insn, 0, 3); 4754 4755 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4756 return MCDisassembler::Fail; 4757 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 4758 return MCDisassembler::Fail; 4759 4760 return S; 4761} 4762 4763template <int shift> 4764static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn, 4765 uint64_t Address, 4766 const MCDisassembler *Decoder) { 4767 DecodeStatus S = MCDisassembler::Success; 4768 unsigned Qm = fieldFromInstruction(Insn, 8, 3); 4769 int imm = fieldFromInstruction(Insn, 0, 7); 4770 4771 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 4772 return MCDisassembler::Fail; 4773 4774 if(!fieldFromInstruction(Insn, 7, 1)) { 4775 if (imm == 0) 4776 imm = INT32_MIN; // indicate -0 4777 else 4778 imm *= -1; 4779 } 4780 if (imm != INT32_MIN) 4781 imm *= (1U << shift); 4782 Inst.addOperand(MCOperand::createImm(imm)); 4783 4784 return S; 4785} 4786 4787static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 4788 uint64_t Address, 4789 const MCDisassembler *Decoder) { 4790 // Val is passed in as S:J1:J2:imm10H:imm10L:'0' 4791 // Note only one trailing zero not two. Also the J1 and J2 values are from 4792 // the encoded instruction. So here change to I1 and I2 values via: 4793 // I1 = NOT(J1 EOR S); 4794 // I2 = NOT(J2 EOR S); 4795 // and build the imm32 with two trailing zeros as documented: 4796 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); 4797 unsigned S = (Val >> 23) & 1; 4798 unsigned J1 = (Val >> 22) & 1; 4799 unsigned J2 = (Val >> 21) & 1; 4800 unsigned I1 = !(J1 ^ S); 4801 unsigned I2 = !(J2 ^ S); 4802 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4803 int imm32 = SignExtend32<25>(tmp << 1); 4804 4805 if (!tryAddingSymbolicOperand(Address, 4806 (Address & ~2u) + imm32 + 4, 4807 true, 4, Inst, Decoder)) 4808 Inst.addOperand(MCOperand::createImm(imm32)); 4809 return MCDisassembler::Success; 4810} 4811 4812static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 4813 uint64_t Address, 4814 const MCDisassembler *Decoder) { 4815 if (Val == 0xA || Val == 0xB) 4816 return MCDisassembler::Fail; 4817 4818 const FeatureBitset &featureBits = 4819 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4820 4821 if (!isValidCoprocessorNumber(Val, featureBits)) 4822 return MCDisassembler::Fail; 4823 4824 Inst.addOperand(MCOperand::createImm(Val)); 4825 return MCDisassembler::Success; 4826} 4827 4828static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 4829 uint64_t Address, 4830 const MCDisassembler *Decoder) { 4831 const FeatureBitset &FeatureBits = 4832 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4833 DecodeStatus S = MCDisassembler::Success; 4834 4835 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4836 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4837 4838 if (Rn == 13 && !FeatureBits[ARM::HasV8Ops]) S = MCDisassembler::SoftFail; 4839 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4840 return MCDisassembler::Fail; 4841 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 4842 return MCDisassembler::Fail; 4843 return S; 4844} 4845 4846static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 4847 uint64_t Address, 4848 const MCDisassembler *Decoder) { 4849 DecodeStatus S = MCDisassembler::Success; 4850 4851 unsigned pred = fieldFromInstruction(Insn, 22, 4); 4852 if (pred == 0xE || pred == 0xF) { 4853 unsigned opc = fieldFromInstruction(Insn, 4, 28); 4854 switch (opc) { 4855 default: 4856 return MCDisassembler::Fail; 4857 case 0xf3bf8f4: 4858 Inst.setOpcode(ARM::t2DSB); 4859 break; 4860 case 0xf3bf8f5: 4861 Inst.setOpcode(ARM::t2DMB); 4862 break; 4863 case 0xf3bf8f6: 4864 Inst.setOpcode(ARM::t2ISB); 4865 break; 4866 } 4867 4868 unsigned imm = fieldFromInstruction(Insn, 0, 4); 4869 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 4870 } 4871 4872 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; 4873 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19; 4874 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18; 4875 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12; 4876 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20; 4877 4878 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 4879 return MCDisassembler::Fail; 4880 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4881 return MCDisassembler::Fail; 4882 4883 return S; 4884} 4885 4886// Decode a shifted immediate operand. These basically consist 4887// of an 8-bit value, and a 4-bit directive that specifies either 4888// a splat operation or a rotation. 4889static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, uint64_t Address, 4890 const MCDisassembler *Decoder) { 4891 unsigned ctrl = fieldFromInstruction(Val, 10, 2); 4892 if (ctrl == 0) { 4893 unsigned byte = fieldFromInstruction(Val, 8, 2); 4894 unsigned imm = fieldFromInstruction(Val, 0, 8); 4895 switch (byte) { 4896 case 0: 4897 Inst.addOperand(MCOperand::createImm(imm)); 4898 break; 4899 case 1: 4900 Inst.addOperand(MCOperand::createImm((imm << 16) | imm)); 4901 break; 4902 case 2: 4903 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8))); 4904 break; 4905 case 3: 4906 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) | 4907 (imm << 8) | imm)); 4908 break; 4909 } 4910 } else { 4911 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80; 4912 unsigned rot = fieldFromInstruction(Val, 7, 5); 4913 unsigned imm = llvm::rotr<uint32_t>(unrot, rot); 4914 Inst.addOperand(MCOperand::createImm(imm)); 4915 } 4916 4917 return MCDisassembler::Success; 4918} 4919 4920static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 4921 uint64_t Address, 4922 const MCDisassembler *Decoder) { 4923 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4, 4924 true, 2, Inst, Decoder)) 4925 Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1))); 4926 return MCDisassembler::Success; 4927} 4928 4929static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 4930 uint64_t Address, 4931 const MCDisassembler *Decoder) { 4932 // Val is passed in as S:J1:J2:imm10:imm11 4933 // Note no trailing zero after imm11. Also the J1 and J2 values are from 4934 // the encoded instruction. So here change to I1 and I2 values via: 4935 // I1 = NOT(J1 EOR S); 4936 // I2 = NOT(J2 EOR S); 4937 // and build the imm32 with one trailing zero as documented: 4938 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 4939 unsigned S = (Val >> 23) & 1; 4940 unsigned J1 = (Val >> 22) & 1; 4941 unsigned J2 = (Val >> 21) & 1; 4942 unsigned I1 = !(J1 ^ S); 4943 unsigned I2 = !(J2 ^ S); 4944 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 4945 int imm32 = SignExtend32<25>(tmp << 1); 4946 4947 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 4948 true, 4, Inst, Decoder)) 4949 Inst.addOperand(MCOperand::createImm(imm32)); 4950 return MCDisassembler::Success; 4951} 4952 4953static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 4954 uint64_t Address, 4955 const MCDisassembler *Decoder) { 4956 if (Val & ~0xf) 4957 return MCDisassembler::Fail; 4958 4959 Inst.addOperand(MCOperand::createImm(Val)); 4960 return MCDisassembler::Success; 4961} 4962 4963static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val, 4964 uint64_t Address, 4965 const MCDisassembler *Decoder) { 4966 if (Val & ~0xf) 4967 return MCDisassembler::Fail; 4968 4969 Inst.addOperand(MCOperand::createImm(Val)); 4970 return MCDisassembler::Success; 4971} 4972 4973static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, uint64_t Address, 4974 const MCDisassembler *Decoder) { 4975 DecodeStatus S = MCDisassembler::Success; 4976 const FeatureBitset &FeatureBits = 4977 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); 4978 4979 if (FeatureBits[ARM::FeatureMClass]) { 4980 unsigned ValLow = Val & 0xff; 4981 4982 // Validate the SYSm value first. 4983 switch (ValLow) { 4984 case 0: // apsr 4985 case 1: // iapsr 4986 case 2: // eapsr 4987 case 3: // xpsr 4988 case 5: // ipsr 4989 case 6: // epsr 4990 case 7: // iepsr 4991 case 8: // msp 4992 case 9: // psp 4993 case 16: // primask 4994 case 20: // control 4995 break; 4996 case 17: // basepri 4997 case 18: // basepri_max 4998 case 19: // faultmask 4999 if (!(FeatureBits[ARM::HasV7Ops])) 5000 // Values basepri, basepri_max and faultmask are only valid for v7m. 5001 return MCDisassembler::Fail; 5002 break; 5003 case 0x8a: // msplim_ns 5004 case 0x8b: // psplim_ns 5005 case 0x91: // basepri_ns 5006 case 0x93: // faultmask_ns 5007 if (!(FeatureBits[ARM::HasV8MMainlineOps])) 5008 return MCDisassembler::Fail; 5009 [[fallthrough]]; 5010 case 10: // msplim 5011 case 11: // psplim 5012 case 0x88: // msp_ns 5013 case 0x89: // psp_ns 5014 case 0x90: // primask_ns 5015 case 0x94: // control_ns 5016 case 0x98: // sp_ns 5017 if (!(FeatureBits[ARM::Feature8MSecExt])) 5018 return MCDisassembler::Fail; 5019 break; 5020 case 0x20: // pac_key_p_0 5021 case 0x21: // pac_key_p_1 5022 case 0x22: // pac_key_p_2 5023 case 0x23: // pac_key_p_3 5024 case 0x24: // pac_key_u_0 5025 case 0x25: // pac_key_u_1 5026 case 0x26: // pac_key_u_2 5027 case 0x27: // pac_key_u_3 5028 case 0xa0: // pac_key_p_0_ns 5029 case 0xa1: // pac_key_p_1_ns 5030 case 0xa2: // pac_key_p_2_ns 5031 case 0xa3: // pac_key_p_3_ns 5032 case 0xa4: // pac_key_u_0_ns 5033 case 0xa5: // pac_key_u_1_ns 5034 case 0xa6: // pac_key_u_2_ns 5035 case 0xa7: // pac_key_u_3_ns 5036 if (!(FeatureBits[ARM::FeaturePACBTI])) 5037 return MCDisassembler::Fail; 5038 break; 5039 default: 5040 // Architecturally defined as unpredictable 5041 S = MCDisassembler::SoftFail; 5042 break; 5043 } 5044 5045 if (Inst.getOpcode() == ARM::t2MSR_M) { 5046 unsigned Mask = fieldFromInstruction(Val, 10, 2); 5047 if (!(FeatureBits[ARM::HasV7Ops])) { 5048 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are 5049 // unpredictable. 5050 if (Mask != 2) 5051 S = MCDisassembler::SoftFail; 5052 } 5053 else { 5054 // The ARMv7-M architecture stores an additional 2-bit mask value in 5055 // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and 5056 // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if 5057 // the NZCVQ bits should be moved by the instruction. Bit mask{0} 5058 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set 5059 // only if the processor includes the DSP extension. 5060 if (Mask == 0 || (Mask != 2 && ValLow > 3) || 5061 (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1))) 5062 S = MCDisassembler::SoftFail; 5063 } 5064 } 5065 } else { 5066 // A/R class 5067 if (Val == 0) 5068 return MCDisassembler::Fail; 5069 } 5070 Inst.addOperand(MCOperand::createImm(Val)); 5071 return S; 5072} 5073 5074static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val, 5075 uint64_t Address, 5076 const MCDisassembler *Decoder) { 5077 unsigned R = fieldFromInstruction(Val, 5, 1); 5078 unsigned SysM = fieldFromInstruction(Val, 0, 5); 5079 5080 // The table of encodings for these banked registers comes from B9.2.3 of the 5081 // ARM ARM. There are patterns, but nothing regular enough to make this logic 5082 // neater. So by fiat, these values are UNPREDICTABLE: 5083 if (!ARMBankedReg::lookupBankedRegByEncoding((R << 5) | SysM)) 5084 return MCDisassembler::Fail; 5085 5086 Inst.addOperand(MCOperand::createImm(Val)); 5087 return MCDisassembler::Success; 5088} 5089 5090static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 5091 uint64_t Address, 5092 const MCDisassembler *Decoder) { 5093 DecodeStatus S = MCDisassembler::Success; 5094 5095 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5096 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5097 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5098 5099 if (Rn == 0xF) 5100 S = MCDisassembler::SoftFail; 5101 5102 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 5103 return MCDisassembler::Fail; 5104 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5105 return MCDisassembler::Fail; 5106 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5107 return MCDisassembler::Fail; 5108 5109 return S; 5110} 5111 5112static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 5113 uint64_t Address, 5114 const MCDisassembler *Decoder) { 5115 DecodeStatus S = MCDisassembler::Success; 5116 5117 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5118 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 5119 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5120 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5121 5122 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 5123 return MCDisassembler::Fail; 5124 5125 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1) 5126 S = MCDisassembler::SoftFail; 5127 5128 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 5129 return MCDisassembler::Fail; 5130 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5131 return MCDisassembler::Fail; 5132 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5133 return MCDisassembler::Fail; 5134 5135 return S; 5136} 5137 5138static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 5139 uint64_t Address, 5140 const MCDisassembler *Decoder) { 5141 DecodeStatus S = MCDisassembler::Success; 5142 5143 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5144 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5145 unsigned imm = fieldFromInstruction(Insn, 0, 12); 5146 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 5147 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 5148 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5149 5150 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 5151 5152 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 5153 return MCDisassembler::Fail; 5154 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5155 return MCDisassembler::Fail; 5156 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 5157 return MCDisassembler::Fail; 5158 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5159 return MCDisassembler::Fail; 5160 5161 return S; 5162} 5163 5164static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 5165 uint64_t Address, 5166 const MCDisassembler *Decoder) { 5167 DecodeStatus S = MCDisassembler::Success; 5168 5169 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5170 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5171 unsigned imm = fieldFromInstruction(Insn, 0, 12); 5172 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 5173 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 5174 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5175 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5176 5177 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 5178 if (Rm == 0xF) S = MCDisassembler::SoftFail; 5179 5180 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 5181 return MCDisassembler::Fail; 5182 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5183 return MCDisassembler::Fail; 5184 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 5185 return MCDisassembler::Fail; 5186 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5187 return MCDisassembler::Fail; 5188 5189 return S; 5190} 5191 5192static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 5193 uint64_t Address, 5194 const MCDisassembler *Decoder) { 5195 DecodeStatus S = MCDisassembler::Success; 5196 5197 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5198 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5199 unsigned imm = fieldFromInstruction(Insn, 0, 12); 5200 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 5201 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 5202 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5203 5204 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 5205 5206 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5207 return MCDisassembler::Fail; 5208 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 5209 return MCDisassembler::Fail; 5210 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 5211 return MCDisassembler::Fail; 5212 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5213 return MCDisassembler::Fail; 5214 5215 return S; 5216} 5217 5218static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 5219 uint64_t Address, 5220 const MCDisassembler *Decoder) { 5221 DecodeStatus S = MCDisassembler::Success; 5222 5223 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5224 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5225 unsigned imm = fieldFromInstruction(Insn, 0, 12); 5226 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 5227 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 5228 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5229 5230 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 5231 5232 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5233 return MCDisassembler::Fail; 5234 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 5235 return MCDisassembler::Fail; 5236 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 5237 return MCDisassembler::Fail; 5238 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5239 return MCDisassembler::Fail; 5240 5241 return S; 5242} 5243 5244static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, uint64_t Address, 5245 const MCDisassembler *Decoder) { 5246 DecodeStatus S = MCDisassembler::Success; 5247 5248 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5249 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5250 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5251 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5252 unsigned size = fieldFromInstruction(Insn, 10, 2); 5253 5254 unsigned align = 0; 5255 unsigned index = 0; 5256 switch (size) { 5257 default: 5258 return MCDisassembler::Fail; 5259 case 0: 5260 if (fieldFromInstruction(Insn, 4, 1)) 5261 return MCDisassembler::Fail; // UNDEFINED 5262 index = fieldFromInstruction(Insn, 5, 3); 5263 break; 5264 case 1: 5265 if (fieldFromInstruction(Insn, 5, 1)) 5266 return MCDisassembler::Fail; // UNDEFINED 5267 index = fieldFromInstruction(Insn, 6, 2); 5268 if (fieldFromInstruction(Insn, 4, 1)) 5269 align = 2; 5270 break; 5271 case 2: 5272 if (fieldFromInstruction(Insn, 6, 1)) 5273 return MCDisassembler::Fail; // UNDEFINED 5274 index = fieldFromInstruction(Insn, 7, 1); 5275 5276 switch (fieldFromInstruction(Insn, 4, 2)) { 5277 case 0 : 5278 align = 0; break; 5279 case 3: 5280 align = 4; break; 5281 default: 5282 return MCDisassembler::Fail; 5283 } 5284 break; 5285 } 5286 5287 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5288 return MCDisassembler::Fail; 5289 if (Rm != 0xF) { // Writeback 5290 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5291 return MCDisassembler::Fail; 5292 } 5293 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5294 return MCDisassembler::Fail; 5295 Inst.addOperand(MCOperand::createImm(align)); 5296 if (Rm != 0xF) { 5297 if (Rm != 0xD) { 5298 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5299 return MCDisassembler::Fail; 5300 } else 5301 Inst.addOperand(MCOperand::createReg(0)); 5302 } 5303 5304 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5305 return MCDisassembler::Fail; 5306 Inst.addOperand(MCOperand::createImm(index)); 5307 5308 return S; 5309} 5310 5311static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, uint64_t Address, 5312 const MCDisassembler *Decoder) { 5313 DecodeStatus S = MCDisassembler::Success; 5314 5315 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5316 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5317 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5318 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5319 unsigned size = fieldFromInstruction(Insn, 10, 2); 5320 5321 unsigned align = 0; 5322 unsigned index = 0; 5323 switch (size) { 5324 default: 5325 return MCDisassembler::Fail; 5326 case 0: 5327 if (fieldFromInstruction(Insn, 4, 1)) 5328 return MCDisassembler::Fail; // UNDEFINED 5329 index = fieldFromInstruction(Insn, 5, 3); 5330 break; 5331 case 1: 5332 if (fieldFromInstruction(Insn, 5, 1)) 5333 return MCDisassembler::Fail; // UNDEFINED 5334 index = fieldFromInstruction(Insn, 6, 2); 5335 if (fieldFromInstruction(Insn, 4, 1)) 5336 align = 2; 5337 break; 5338 case 2: 5339 if (fieldFromInstruction(Insn, 6, 1)) 5340 return MCDisassembler::Fail; // UNDEFINED 5341 index = fieldFromInstruction(Insn, 7, 1); 5342 5343 switch (fieldFromInstruction(Insn, 4, 2)) { 5344 case 0: 5345 align = 0; break; 5346 case 3: 5347 align = 4; break; 5348 default: 5349 return MCDisassembler::Fail; 5350 } 5351 break; 5352 } 5353 5354 if (Rm != 0xF) { // Writeback 5355 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5356 return MCDisassembler::Fail; 5357 } 5358 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5359 return MCDisassembler::Fail; 5360 Inst.addOperand(MCOperand::createImm(align)); 5361 if (Rm != 0xF) { 5362 if (Rm != 0xD) { 5363 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5364 return MCDisassembler::Fail; 5365 } else 5366 Inst.addOperand(MCOperand::createReg(0)); 5367 } 5368 5369 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5370 return MCDisassembler::Fail; 5371 Inst.addOperand(MCOperand::createImm(index)); 5372 5373 return S; 5374} 5375 5376static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, uint64_t Address, 5377 const MCDisassembler *Decoder) { 5378 DecodeStatus S = MCDisassembler::Success; 5379 5380 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5381 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5382 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5383 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5384 unsigned size = fieldFromInstruction(Insn, 10, 2); 5385 5386 unsigned align = 0; 5387 unsigned index = 0; 5388 unsigned inc = 1; 5389 switch (size) { 5390 default: 5391 return MCDisassembler::Fail; 5392 case 0: 5393 index = fieldFromInstruction(Insn, 5, 3); 5394 if (fieldFromInstruction(Insn, 4, 1)) 5395 align = 2; 5396 break; 5397 case 1: 5398 index = fieldFromInstruction(Insn, 6, 2); 5399 if (fieldFromInstruction(Insn, 4, 1)) 5400 align = 4; 5401 if (fieldFromInstruction(Insn, 5, 1)) 5402 inc = 2; 5403 break; 5404 case 2: 5405 if (fieldFromInstruction(Insn, 5, 1)) 5406 return MCDisassembler::Fail; // UNDEFINED 5407 index = fieldFromInstruction(Insn, 7, 1); 5408 if (fieldFromInstruction(Insn, 4, 1) != 0) 5409 align = 8; 5410 if (fieldFromInstruction(Insn, 6, 1)) 5411 inc = 2; 5412 break; 5413 } 5414 5415 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5416 return MCDisassembler::Fail; 5417 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5418 return MCDisassembler::Fail; 5419 if (Rm != 0xF) { // Writeback 5420 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5421 return MCDisassembler::Fail; 5422 } 5423 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5424 return MCDisassembler::Fail; 5425 Inst.addOperand(MCOperand::createImm(align)); 5426 if (Rm != 0xF) { 5427 if (Rm != 0xD) { 5428 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5429 return MCDisassembler::Fail; 5430 } else 5431 Inst.addOperand(MCOperand::createReg(0)); 5432 } 5433 5434 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5435 return MCDisassembler::Fail; 5436 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5437 return MCDisassembler::Fail; 5438 Inst.addOperand(MCOperand::createImm(index)); 5439 5440 return S; 5441} 5442 5443static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, uint64_t Address, 5444 const MCDisassembler *Decoder) { 5445 DecodeStatus S = MCDisassembler::Success; 5446 5447 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5448 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5449 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5450 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5451 unsigned size = fieldFromInstruction(Insn, 10, 2); 5452 5453 unsigned align = 0; 5454 unsigned index = 0; 5455 unsigned inc = 1; 5456 switch (size) { 5457 default: 5458 return MCDisassembler::Fail; 5459 case 0: 5460 index = fieldFromInstruction(Insn, 5, 3); 5461 if (fieldFromInstruction(Insn, 4, 1)) 5462 align = 2; 5463 break; 5464 case 1: 5465 index = fieldFromInstruction(Insn, 6, 2); 5466 if (fieldFromInstruction(Insn, 4, 1)) 5467 align = 4; 5468 if (fieldFromInstruction(Insn, 5, 1)) 5469 inc = 2; 5470 break; 5471 case 2: 5472 if (fieldFromInstruction(Insn, 5, 1)) 5473 return MCDisassembler::Fail; // UNDEFINED 5474 index = fieldFromInstruction(Insn, 7, 1); 5475 if (fieldFromInstruction(Insn, 4, 1) != 0) 5476 align = 8; 5477 if (fieldFromInstruction(Insn, 6, 1)) 5478 inc = 2; 5479 break; 5480 } 5481 5482 if (Rm != 0xF) { // Writeback 5483 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5484 return MCDisassembler::Fail; 5485 } 5486 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5487 return MCDisassembler::Fail; 5488 Inst.addOperand(MCOperand::createImm(align)); 5489 if (Rm != 0xF) { 5490 if (Rm != 0xD) { 5491 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5492 return MCDisassembler::Fail; 5493 } else 5494 Inst.addOperand(MCOperand::createReg(0)); 5495 } 5496 5497 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5498 return MCDisassembler::Fail; 5499 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5500 return MCDisassembler::Fail; 5501 Inst.addOperand(MCOperand::createImm(index)); 5502 5503 return S; 5504} 5505 5506static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, uint64_t Address, 5507 const MCDisassembler *Decoder) { 5508 DecodeStatus S = MCDisassembler::Success; 5509 5510 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5511 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5512 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5513 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5514 unsigned size = fieldFromInstruction(Insn, 10, 2); 5515 5516 unsigned align = 0; 5517 unsigned index = 0; 5518 unsigned inc = 1; 5519 switch (size) { 5520 default: 5521 return MCDisassembler::Fail; 5522 case 0: 5523 if (fieldFromInstruction(Insn, 4, 1)) 5524 return MCDisassembler::Fail; // UNDEFINED 5525 index = fieldFromInstruction(Insn, 5, 3); 5526 break; 5527 case 1: 5528 if (fieldFromInstruction(Insn, 4, 1)) 5529 return MCDisassembler::Fail; // UNDEFINED 5530 index = fieldFromInstruction(Insn, 6, 2); 5531 if (fieldFromInstruction(Insn, 5, 1)) 5532 inc = 2; 5533 break; 5534 case 2: 5535 if (fieldFromInstruction(Insn, 4, 2)) 5536 return MCDisassembler::Fail; // UNDEFINED 5537 index = fieldFromInstruction(Insn, 7, 1); 5538 if (fieldFromInstruction(Insn, 6, 1)) 5539 inc = 2; 5540 break; 5541 } 5542 5543 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5544 return MCDisassembler::Fail; 5545 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5546 return MCDisassembler::Fail; 5547 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5548 return MCDisassembler::Fail; 5549 5550 if (Rm != 0xF) { // Writeback 5551 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5552 return MCDisassembler::Fail; 5553 } 5554 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5555 return MCDisassembler::Fail; 5556 Inst.addOperand(MCOperand::createImm(align)); 5557 if (Rm != 0xF) { 5558 if (Rm != 0xD) { 5559 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5560 return MCDisassembler::Fail; 5561 } else 5562 Inst.addOperand(MCOperand::createReg(0)); 5563 } 5564 5565 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5566 return MCDisassembler::Fail; 5567 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5568 return MCDisassembler::Fail; 5569 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5570 return MCDisassembler::Fail; 5571 Inst.addOperand(MCOperand::createImm(index)); 5572 5573 return S; 5574} 5575 5576static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, uint64_t Address, 5577 const MCDisassembler *Decoder) { 5578 DecodeStatus S = MCDisassembler::Success; 5579 5580 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5581 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5582 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5583 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5584 unsigned size = fieldFromInstruction(Insn, 10, 2); 5585 5586 unsigned align = 0; 5587 unsigned index = 0; 5588 unsigned inc = 1; 5589 switch (size) { 5590 default: 5591 return MCDisassembler::Fail; 5592 case 0: 5593 if (fieldFromInstruction(Insn, 4, 1)) 5594 return MCDisassembler::Fail; // UNDEFINED 5595 index = fieldFromInstruction(Insn, 5, 3); 5596 break; 5597 case 1: 5598 if (fieldFromInstruction(Insn, 4, 1)) 5599 return MCDisassembler::Fail; // UNDEFINED 5600 index = fieldFromInstruction(Insn, 6, 2); 5601 if (fieldFromInstruction(Insn, 5, 1)) 5602 inc = 2; 5603 break; 5604 case 2: 5605 if (fieldFromInstruction(Insn, 4, 2)) 5606 return MCDisassembler::Fail; // UNDEFINED 5607 index = fieldFromInstruction(Insn, 7, 1); 5608 if (fieldFromInstruction(Insn, 6, 1)) 5609 inc = 2; 5610 break; 5611 } 5612 5613 if (Rm != 0xF) { // Writeback 5614 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5615 return MCDisassembler::Fail; 5616 } 5617 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5618 return MCDisassembler::Fail; 5619 Inst.addOperand(MCOperand::createImm(align)); 5620 if (Rm != 0xF) { 5621 if (Rm != 0xD) { 5622 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5623 return MCDisassembler::Fail; 5624 } else 5625 Inst.addOperand(MCOperand::createReg(0)); 5626 } 5627 5628 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5629 return MCDisassembler::Fail; 5630 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5631 return MCDisassembler::Fail; 5632 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5633 return MCDisassembler::Fail; 5634 Inst.addOperand(MCOperand::createImm(index)); 5635 5636 return S; 5637} 5638 5639static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, uint64_t Address, 5640 const MCDisassembler *Decoder) { 5641 DecodeStatus S = MCDisassembler::Success; 5642 5643 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5644 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5645 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5646 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5647 unsigned size = fieldFromInstruction(Insn, 10, 2); 5648 5649 unsigned align = 0; 5650 unsigned index = 0; 5651 unsigned inc = 1; 5652 switch (size) { 5653 default: 5654 return MCDisassembler::Fail; 5655 case 0: 5656 if (fieldFromInstruction(Insn, 4, 1)) 5657 align = 4; 5658 index = fieldFromInstruction(Insn, 5, 3); 5659 break; 5660 case 1: 5661 if (fieldFromInstruction(Insn, 4, 1)) 5662 align = 8; 5663 index = fieldFromInstruction(Insn, 6, 2); 5664 if (fieldFromInstruction(Insn, 5, 1)) 5665 inc = 2; 5666 break; 5667 case 2: 5668 switch (fieldFromInstruction(Insn, 4, 2)) { 5669 case 0: 5670 align = 0; break; 5671 case 3: 5672 return MCDisassembler::Fail; 5673 default: 5674 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 5675 } 5676 5677 index = fieldFromInstruction(Insn, 7, 1); 5678 if (fieldFromInstruction(Insn, 6, 1)) 5679 inc = 2; 5680 break; 5681 } 5682 5683 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5684 return MCDisassembler::Fail; 5685 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5686 return MCDisassembler::Fail; 5687 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5688 return MCDisassembler::Fail; 5689 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5690 return MCDisassembler::Fail; 5691 5692 if (Rm != 0xF) { // Writeback 5693 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5694 return MCDisassembler::Fail; 5695 } 5696 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5697 return MCDisassembler::Fail; 5698 Inst.addOperand(MCOperand::createImm(align)); 5699 if (Rm != 0xF) { 5700 if (Rm != 0xD) { 5701 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5702 return MCDisassembler::Fail; 5703 } else 5704 Inst.addOperand(MCOperand::createReg(0)); 5705 } 5706 5707 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5708 return MCDisassembler::Fail; 5709 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5710 return MCDisassembler::Fail; 5711 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5712 return MCDisassembler::Fail; 5713 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5714 return MCDisassembler::Fail; 5715 Inst.addOperand(MCOperand::createImm(index)); 5716 5717 return S; 5718} 5719 5720static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, uint64_t Address, 5721 const MCDisassembler *Decoder) { 5722 DecodeStatus S = MCDisassembler::Success; 5723 5724 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5725 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 5726 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 5727 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 5728 unsigned size = fieldFromInstruction(Insn, 10, 2); 5729 5730 unsigned align = 0; 5731 unsigned index = 0; 5732 unsigned inc = 1; 5733 switch (size) { 5734 default: 5735 return MCDisassembler::Fail; 5736 case 0: 5737 if (fieldFromInstruction(Insn, 4, 1)) 5738 align = 4; 5739 index = fieldFromInstruction(Insn, 5, 3); 5740 break; 5741 case 1: 5742 if (fieldFromInstruction(Insn, 4, 1)) 5743 align = 8; 5744 index = fieldFromInstruction(Insn, 6, 2); 5745 if (fieldFromInstruction(Insn, 5, 1)) 5746 inc = 2; 5747 break; 5748 case 2: 5749 switch (fieldFromInstruction(Insn, 4, 2)) { 5750 case 0: 5751 align = 0; break; 5752 case 3: 5753 return MCDisassembler::Fail; 5754 default: 5755 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 5756 } 5757 5758 index = fieldFromInstruction(Insn, 7, 1); 5759 if (fieldFromInstruction(Insn, 6, 1)) 5760 inc = 2; 5761 break; 5762 } 5763 5764 if (Rm != 0xF) { // Writeback 5765 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5766 return MCDisassembler::Fail; 5767 } 5768 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 5769 return MCDisassembler::Fail; 5770 Inst.addOperand(MCOperand::createImm(align)); 5771 if (Rm != 0xF) { 5772 if (Rm != 0xD) { 5773 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 5774 return MCDisassembler::Fail; 5775 } else 5776 Inst.addOperand(MCOperand::createReg(0)); 5777 } 5778 5779 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 5780 return MCDisassembler::Fail; 5781 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 5782 return MCDisassembler::Fail; 5783 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 5784 return MCDisassembler::Fail; 5785 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 5786 return MCDisassembler::Fail; 5787 Inst.addOperand(MCOperand::createImm(index)); 5788 5789 return S; 5790} 5791 5792static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, uint64_t Address, 5793 const MCDisassembler *Decoder) { 5794 DecodeStatus S = MCDisassembler::Success; 5795 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5796 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 5797 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 5798 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5799 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 5800 5801 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 5802 S = MCDisassembler::SoftFail; 5803 5804 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 5805 return MCDisassembler::Fail; 5806 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 5807 return MCDisassembler::Fail; 5808 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 5809 return MCDisassembler::Fail; 5810 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 5811 return MCDisassembler::Fail; 5812 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5813 return MCDisassembler::Fail; 5814 5815 return S; 5816} 5817 5818static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, uint64_t Address, 5819 const MCDisassembler *Decoder) { 5820 DecodeStatus S = MCDisassembler::Success; 5821 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5822 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 5823 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 5824 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5825 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 5826 5827 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 5828 S = MCDisassembler::SoftFail; 5829 5830 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 5831 return MCDisassembler::Fail; 5832 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 5833 return MCDisassembler::Fail; 5834 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 5835 return MCDisassembler::Fail; 5836 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 5837 return MCDisassembler::Fail; 5838 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5839 return MCDisassembler::Fail; 5840 5841 return S; 5842} 5843 5844static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, uint64_t Address, 5845 const MCDisassembler *Decoder) { 5846 DecodeStatus S = MCDisassembler::Success; 5847 unsigned pred = fieldFromInstruction(Insn, 4, 4); 5848 unsigned mask = fieldFromInstruction(Insn, 0, 4); 5849 5850 if (pred == 0xF) { 5851 pred = 0xE; 5852 S = MCDisassembler::SoftFail; 5853 } 5854 5855 if (mask == 0x0) 5856 return MCDisassembler::Fail; 5857 5858 // IT masks are encoded as a sequence of replacement low-order bits 5859 // for the condition code. So if the low bit of the starting 5860 // condition code is 1, then we have to flip all the bits above the 5861 // terminating bit (which is the lowest 1 bit). 5862 if (pred & 1) { 5863 unsigned LowBit = mask & -mask; 5864 unsigned BitsAboveLowBit = 0xF & (-LowBit << 1); 5865 mask ^= BitsAboveLowBit; 5866 } 5867 5868 Inst.addOperand(MCOperand::createImm(pred)); 5869 Inst.addOperand(MCOperand::createImm(mask)); 5870 return S; 5871} 5872 5873static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 5874 uint64_t Address, 5875 const MCDisassembler *Decoder) { 5876 DecodeStatus S = MCDisassembler::Success; 5877 5878 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5879 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5880 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5881 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5882 unsigned W = fieldFromInstruction(Insn, 21, 1); 5883 unsigned U = fieldFromInstruction(Insn, 23, 1); 5884 unsigned P = fieldFromInstruction(Insn, 24, 1); 5885 bool writeback = (W == 1) | (P == 0); 5886 5887 addr |= (U << 8) | (Rn << 9); 5888 5889 if (writeback && (Rn == Rt || Rn == Rt2)) 5890 Check(S, MCDisassembler::SoftFail); 5891 if (Rt == Rt2) 5892 Check(S, MCDisassembler::SoftFail); 5893 5894 // Rt 5895 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5896 return MCDisassembler::Fail; 5897 // Rt2 5898 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5899 return MCDisassembler::Fail; 5900 // Writeback operand 5901 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5902 return MCDisassembler::Fail; 5903 // addr 5904 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5905 return MCDisassembler::Fail; 5906 5907 return S; 5908} 5909 5910static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 5911 uint64_t Address, 5912 const MCDisassembler *Decoder) { 5913 DecodeStatus S = MCDisassembler::Success; 5914 5915 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5916 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 5917 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5918 unsigned addr = fieldFromInstruction(Insn, 0, 8); 5919 unsigned W = fieldFromInstruction(Insn, 21, 1); 5920 unsigned U = fieldFromInstruction(Insn, 23, 1); 5921 unsigned P = fieldFromInstruction(Insn, 24, 1); 5922 bool writeback = (W == 1) | (P == 0); 5923 5924 addr |= (U << 8) | (Rn << 9); 5925 5926 if (writeback && (Rn == Rt || Rn == Rt2)) 5927 Check(S, MCDisassembler::SoftFail); 5928 5929 // Writeback operand 5930 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 5931 return MCDisassembler::Fail; 5932 // Rt 5933 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 5934 return MCDisassembler::Fail; 5935 // Rt2 5936 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 5937 return MCDisassembler::Fail; 5938 // addr 5939 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 5940 return MCDisassembler::Fail; 5941 5942 return S; 5943} 5944 5945static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, uint64_t Address, 5946 const MCDisassembler *Decoder) { 5947 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 5948 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 5949 if (sign1 != sign2) return MCDisassembler::Fail; 5950 const unsigned Rd = fieldFromInstruction(Insn, 8, 4); 5951 assert(Inst.getNumOperands() == 0 && "We should receive an empty Inst"); 5952 DecodeStatus S = DecoderGPRRegisterClass(Inst, Rd, Address, Decoder); 5953 5954 unsigned Val = fieldFromInstruction(Insn, 0, 8); 5955 Val |= fieldFromInstruction(Insn, 12, 3) << 8; 5956 Val |= fieldFromInstruction(Insn, 26, 1) << 11; 5957 // If sign, then it is decreasing the address. 5958 if (sign1) { 5959 // Following ARMv7 Architecture Manual, when the offset 5960 // is zero, it is decoded as a subw, not as a adr.w 5961 if (!Val) { 5962 Inst.setOpcode(ARM::t2SUBri12); 5963 Inst.addOperand(MCOperand::createReg(ARM::PC)); 5964 } else 5965 Val = -Val; 5966 } 5967 Inst.addOperand(MCOperand::createImm(Val)); 5968 return S; 5969} 5970 5971static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 5972 uint64_t Address, 5973 const MCDisassembler *Decoder) { 5974 DecodeStatus S = MCDisassembler::Success; 5975 5976 // Shift of "asr #32" is not allowed in Thumb2 mode. 5977 if (Val == 0x20) S = MCDisassembler::Fail; 5978 Inst.addOperand(MCOperand::createImm(Val)); 5979 return S; 5980} 5981 5982static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, uint64_t Address, 5983 const MCDisassembler *Decoder) { 5984 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 5985 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); 5986 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 5987 unsigned pred = fieldFromInstruction(Insn, 28, 4); 5988 5989 if (pred == 0xF) 5990 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 5991 5992 DecodeStatus S = MCDisassembler::Success; 5993 5994 if (Rt == Rn || Rn == Rt2) 5995 S = MCDisassembler::SoftFail; 5996 5997 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5998 return MCDisassembler::Fail; 5999 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 6000 return MCDisassembler::Fail; 6001 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 6002 return MCDisassembler::Fail; 6003 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 6004 return MCDisassembler::Fail; 6005 6006 return S; 6007} 6008 6009static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, uint64_t Address, 6010 const MCDisassembler *Decoder) { 6011 const FeatureBitset &featureBits = 6012 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 6013 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 6014 6015 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 6016 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 6017 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 6018 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 6019 unsigned imm = fieldFromInstruction(Insn, 16, 6); 6020 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 6021 unsigned op = fieldFromInstruction(Insn, 5, 1); 6022 6023 DecodeStatus S = MCDisassembler::Success; 6024 6025 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 6026 if (!(imm & 0x38)) { 6027 if (cmode == 0xF) { 6028 if (op == 1) return MCDisassembler::Fail; 6029 Inst.setOpcode(ARM::VMOVv2f32); 6030 } 6031 if (hasFullFP16) { 6032 if (cmode == 0xE) { 6033 if (op == 1) { 6034 Inst.setOpcode(ARM::VMOVv1i64); 6035 } else { 6036 Inst.setOpcode(ARM::VMOVv8i8); 6037 } 6038 } 6039 if (cmode == 0xD) { 6040 if (op == 1) { 6041 Inst.setOpcode(ARM::VMVNv2i32); 6042 } else { 6043 Inst.setOpcode(ARM::VMOVv2i32); 6044 } 6045 } 6046 if (cmode == 0xC) { 6047 if (op == 1) { 6048 Inst.setOpcode(ARM::VMVNv2i32); 6049 } else { 6050 Inst.setOpcode(ARM::VMOVv2i32); 6051 } 6052 } 6053 } 6054 return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder); 6055 } 6056 6057 if (!(imm & 0x20)) return MCDisassembler::Fail; 6058 6059 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 6060 return MCDisassembler::Fail; 6061 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 6062 return MCDisassembler::Fail; 6063 Inst.addOperand(MCOperand::createImm(64 - imm)); 6064 6065 return S; 6066} 6067 6068static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, uint64_t Address, 6069 const MCDisassembler *Decoder) { 6070 const FeatureBitset &featureBits = 6071 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 6072 bool hasFullFP16 = featureBits[ARM::FeatureFullFP16]; 6073 6074 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 6075 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 6076 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 6077 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 6078 unsigned imm = fieldFromInstruction(Insn, 16, 6); 6079 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 6080 unsigned op = fieldFromInstruction(Insn, 5, 1); 6081 6082 DecodeStatus S = MCDisassembler::Success; 6083 6084 // If the top 3 bits of imm are clear, this is a VMOV (immediate) 6085 if (!(imm & 0x38)) { 6086 if (cmode == 0xF) { 6087 if (op == 1) return MCDisassembler::Fail; 6088 Inst.setOpcode(ARM::VMOVv4f32); 6089 } 6090 if (hasFullFP16) { 6091 if (cmode == 0xE) { 6092 if (op == 1) { 6093 Inst.setOpcode(ARM::VMOVv2i64); 6094 } else { 6095 Inst.setOpcode(ARM::VMOVv16i8); 6096 } 6097 } 6098 if (cmode == 0xD) { 6099 if (op == 1) { 6100 Inst.setOpcode(ARM::VMVNv4i32); 6101 } else { 6102 Inst.setOpcode(ARM::VMOVv4i32); 6103 } 6104 } 6105 if (cmode == 0xC) { 6106 if (op == 1) { 6107 Inst.setOpcode(ARM::VMVNv4i32); 6108 } else { 6109 Inst.setOpcode(ARM::VMOVv4i32); 6110 } 6111 } 6112 } 6113 return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder); 6114 } 6115 6116 if (!(imm & 0x20)) return MCDisassembler::Fail; 6117 6118 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 6119 return MCDisassembler::Fail; 6120 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 6121 return MCDisassembler::Fail; 6122 Inst.addOperand(MCOperand::createImm(64 - imm)); 6123 6124 return S; 6125} 6126 6127static DecodeStatus 6128DecodeNEONComplexLane64Instruction(MCInst &Inst, unsigned Insn, 6129 uint64_t Address, 6130 const MCDisassembler *Decoder) { 6131 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 6132 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 6133 unsigned Vn = (fieldFromInstruction(Insn, 16, 4) << 0); 6134 Vn |= (fieldFromInstruction(Insn, 7, 1) << 4); 6135 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 6136 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 6137 unsigned q = (fieldFromInstruction(Insn, 6, 1) << 0); 6138 unsigned rotate = (fieldFromInstruction(Insn, 20, 2) << 0); 6139 6140 DecodeStatus S = MCDisassembler::Success; 6141 6142 auto DestRegDecoder = q ? DecodeQPRRegisterClass : DecodeDPRRegisterClass; 6143 6144 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) 6145 return MCDisassembler::Fail; 6146 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder))) 6147 return MCDisassembler::Fail; 6148 if (!Check(S, DestRegDecoder(Inst, Vn, Address, Decoder))) 6149 return MCDisassembler::Fail; 6150 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 6151 return MCDisassembler::Fail; 6152 // The lane index does not have any bits in the encoding, because it can only 6153 // be 0. 6154 Inst.addOperand(MCOperand::createImm(0)); 6155 Inst.addOperand(MCOperand::createImm(rotate)); 6156 6157 return S; 6158} 6159 6160static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, uint64_t Address, 6161 const MCDisassembler *Decoder) { 6162 DecodeStatus S = MCDisassembler::Success; 6163 6164 unsigned Rn = fieldFromInstruction(Val, 16, 4); 6165 unsigned Rt = fieldFromInstruction(Val, 12, 4); 6166 unsigned Rm = fieldFromInstruction(Val, 0, 4); 6167 Rm |= (fieldFromInstruction(Val, 23, 1) << 4); 6168 unsigned Cond = fieldFromInstruction(Val, 28, 4); 6169 6170 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt) 6171 S = MCDisassembler::SoftFail; 6172 6173 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 6174 return MCDisassembler::Fail; 6175 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 6176 return MCDisassembler::Fail; 6177 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 6178 return MCDisassembler::Fail; 6179 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 6180 return MCDisassembler::Fail; 6181 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 6182 return MCDisassembler::Fail; 6183 6184 return S; 6185} 6186 6187static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val, 6188 uint64_t Address, 6189 const MCDisassembler *Decoder) { 6190 DecodeStatus S = MCDisassembler::Success; 6191 6192 unsigned CRm = fieldFromInstruction(Val, 0, 4); 6193 unsigned opc1 = fieldFromInstruction(Val, 4, 4); 6194 unsigned cop = fieldFromInstruction(Val, 8, 4); 6195 unsigned Rt = fieldFromInstruction(Val, 12, 4); 6196 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); 6197 6198 if ((cop & ~0x1) == 0xa) 6199 return MCDisassembler::Fail; 6200 6201 if (Rt == Rt2) 6202 S = MCDisassembler::SoftFail; 6203 6204 // We have to check if the instruction is MRRC2 6205 // or MCRR2 when constructing the operands for 6206 // Inst. Reason is because MRRC2 stores to two 6207 // registers so it's tablegen desc has two 6208 // outputs whereas MCRR doesn't store to any 6209 // registers so all of it's operands are listed 6210 // as inputs, therefore the operand order for 6211 // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm] 6212 // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm] 6213 6214 if (Inst.getOpcode() == ARM::MRRC2) { 6215 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 6216 return MCDisassembler::Fail; 6217 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 6218 return MCDisassembler::Fail; 6219 } 6220 Inst.addOperand(MCOperand::createImm(cop)); 6221 Inst.addOperand(MCOperand::createImm(opc1)); 6222 if (Inst.getOpcode() == ARM::MCRR2) { 6223 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 6224 return MCDisassembler::Fail; 6225 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 6226 return MCDisassembler::Fail; 6227 } 6228 Inst.addOperand(MCOperand::createImm(CRm)); 6229 6230 return S; 6231} 6232 6233static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val, 6234 uint64_t Address, 6235 const MCDisassembler *Decoder) { 6236 const FeatureBitset &featureBits = 6237 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 6238 DecodeStatus S = MCDisassembler::Success; 6239 6240 // Add explicit operand for the destination sysreg, for cases where 6241 // we have to model it for code generation purposes. 6242 switch (Inst.getOpcode()) { 6243 case ARM::VMSR_FPSCR_NZCVQC: 6244 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 6245 break; 6246 case ARM::VMSR_P0: 6247 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6248 break; 6249 } 6250 6251 if (Inst.getOpcode() != ARM::FMSTAT) { 6252 unsigned Rt = fieldFromInstruction(Val, 12, 4); 6253 6254 if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) { 6255 if (Rt == 13 || Rt == 15) 6256 S = MCDisassembler::SoftFail; 6257 Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)); 6258 } else 6259 Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)); 6260 } 6261 6262 // Add explicit operand for the source sysreg, similarly to above. 6263 switch (Inst.getOpcode()) { 6264 case ARM::VMRS_FPSCR_NZCVQC: 6265 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV)); 6266 break; 6267 case ARM::VMRS_P0: 6268 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6269 break; 6270 } 6271 6272 if (featureBits[ARM::ModeThumb]) { 6273 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 6274 Inst.addOperand(MCOperand::createReg(0)); 6275 } else { 6276 unsigned pred = fieldFromInstruction(Val, 28, 4); 6277 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 6278 return MCDisassembler::Fail; 6279 } 6280 6281 return S; 6282} 6283 6284template <bool isSigned, bool isNeg, bool zeroPermitted, int size> 6285static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned Val, 6286 uint64_t Address, 6287 const MCDisassembler *Decoder) { 6288 DecodeStatus S = MCDisassembler::Success; 6289 if (Val == 0 && !zeroPermitted) 6290 S = MCDisassembler::Fail; 6291 6292 uint64_t DecVal; 6293 if (isSigned) 6294 DecVal = SignExtend32<size + 1>(Val << 1); 6295 else 6296 DecVal = (Val << 1); 6297 6298 if (!tryAddingSymbolicOperand(Address, Address + DecVal + 4, true, 4, Inst, 6299 Decoder)) 6300 Inst.addOperand(MCOperand::createImm(isNeg ? -DecVal : DecVal)); 6301 return S; 6302} 6303 6304static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned Val, 6305 uint64_t Address, 6306 const MCDisassembler *Decoder) { 6307 6308 uint64_t LocImm = Inst.getOperand(0).getImm(); 6309 Val = LocImm + (2 << Val); 6310 if (!tryAddingSymbolicOperand(Address, Address + Val + 4, true, 4, Inst, 6311 Decoder)) 6312 Inst.addOperand(MCOperand::createImm(Val)); 6313 return MCDisassembler::Success; 6314} 6315 6316static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val, 6317 uint64_t Address, 6318 const MCDisassembler *Decoder) { 6319 if (Val >= ARMCC::AL) // also exclude the non-condition NV 6320 return MCDisassembler::Fail; 6321 Inst.addOperand(MCOperand::createImm(Val)); 6322 return MCDisassembler::Success; 6323} 6324 6325static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address, 6326 const MCDisassembler *Decoder) { 6327 DecodeStatus S = MCDisassembler::Success; 6328 6329 if (Inst.getOpcode() == ARM::MVE_LCTP) 6330 return S; 6331 6332 unsigned Imm = fieldFromInstruction(Insn, 11, 1) | 6333 fieldFromInstruction(Insn, 1, 10) << 1; 6334 switch (Inst.getOpcode()) { 6335 case ARM::t2LEUpdate: 6336 case ARM::MVE_LETP: 6337 Inst.addOperand(MCOperand::createReg(ARM::LR)); 6338 Inst.addOperand(MCOperand::createReg(ARM::LR)); 6339 [[fallthrough]]; 6340 case ARM::t2LE: 6341 if (!Check(S, DecodeBFLabelOperand<false, true, true, 11>( 6342 Inst, Imm, Address, Decoder))) 6343 return MCDisassembler::Fail; 6344 break; 6345 case ARM::t2WLS: 6346 case ARM::MVE_WLSTP_8: 6347 case ARM::MVE_WLSTP_16: 6348 case ARM::MVE_WLSTP_32: 6349 case ARM::MVE_WLSTP_64: 6350 Inst.addOperand(MCOperand::createReg(ARM::LR)); 6351 if (!Check(S, 6352 DecoderGPRRegisterClass(Inst, fieldFromInstruction(Insn, 16, 4), 6353 Address, Decoder)) || 6354 !Check(S, DecodeBFLabelOperand<false, false, true, 11>( 6355 Inst, Imm, Address, Decoder))) 6356 return MCDisassembler::Fail; 6357 break; 6358 case ARM::t2DLS: 6359 case ARM::MVE_DLSTP_8: 6360 case ARM::MVE_DLSTP_16: 6361 case ARM::MVE_DLSTP_32: 6362 case ARM::MVE_DLSTP_64: 6363 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 6364 if (Rn == 0xF) { 6365 // Enforce all the rest of the instruction bits in LCTP, which 6366 // won't have been reliably checked based on LCTP's own tablegen 6367 // record, because we came to this decode by a roundabout route. 6368 uint32_t CanonicalLCTP = 0xF00FE001, SBZMask = 0x00300FFE; 6369 if ((Insn & ~SBZMask) != CanonicalLCTP) 6370 return MCDisassembler::Fail; // a mandatory bit is wrong: hard fail 6371 if (Insn != CanonicalLCTP) 6372 Check(S, MCDisassembler::SoftFail); // an SBZ bit is wrong: soft fail 6373 6374 Inst.setOpcode(ARM::MVE_LCTP); 6375 } else { 6376 Inst.addOperand(MCOperand::createReg(ARM::LR)); 6377 if (!Check(S, DecoderGPRRegisterClass(Inst, 6378 fieldFromInstruction(Insn, 16, 4), 6379 Address, Decoder))) 6380 return MCDisassembler::Fail; 6381 } 6382 break; 6383 } 6384 return S; 6385} 6386 6387static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val, 6388 uint64_t Address, 6389 const MCDisassembler *Decoder) { 6390 DecodeStatus S = MCDisassembler::Success; 6391 6392 if (Val == 0) 6393 Val = 32; 6394 6395 Inst.addOperand(MCOperand::createImm(Val)); 6396 6397 return S; 6398} 6399 6400static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo, 6401 uint64_t Address, 6402 const MCDisassembler *Decoder) { 6403 if ((RegNo) + 1 > 11) 6404 return MCDisassembler::Fail; 6405 6406 unsigned Register = GPRDecoderTable[(RegNo) + 1]; 6407 Inst.addOperand(MCOperand::createReg(Register)); 6408 return MCDisassembler::Success; 6409} 6410 6411static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo, 6412 uint64_t Address, 6413 const MCDisassembler *Decoder) { 6414 if ((RegNo) > 14) 6415 return MCDisassembler::Fail; 6416 6417 unsigned Register = GPRDecoderTable[(RegNo)]; 6418 Inst.addOperand(MCOperand::createReg(Register)); 6419 return MCDisassembler::Success; 6420} 6421 6422static DecodeStatus 6423DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo, 6424 uint64_t Address, 6425 const MCDisassembler *Decoder) { 6426 if (RegNo == 15) { 6427 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); 6428 return MCDisassembler::Success; 6429 } 6430 6431 unsigned Register = GPRDecoderTable[RegNo]; 6432 Inst.addOperand(MCOperand::createReg(Register)); 6433 6434 if (RegNo == 13) 6435 return MCDisassembler::SoftFail; 6436 6437 return MCDisassembler::Success; 6438} 6439 6440static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address, 6441 const MCDisassembler *Decoder) { 6442 DecodeStatus S = MCDisassembler::Success; 6443 6444 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 6445 Inst.addOperand(MCOperand::createReg(0)); 6446 if (Inst.getOpcode() == ARM::VSCCLRMD) { 6447 unsigned reglist = (fieldFromInstruction(Insn, 1, 7) << 1) | 6448 (fieldFromInstruction(Insn, 12, 4) << 8) | 6449 (fieldFromInstruction(Insn, 22, 1) << 12); 6450 if (!Check(S, DecodeDPRRegListOperand(Inst, reglist, Address, Decoder))) { 6451 return MCDisassembler::Fail; 6452 } 6453 } else { 6454 unsigned reglist = fieldFromInstruction(Insn, 0, 8) | 6455 (fieldFromInstruction(Insn, 22, 1) << 8) | 6456 (fieldFromInstruction(Insn, 12, 4) << 9); 6457 if (!Check(S, DecodeSPRRegListOperand(Inst, reglist, Address, Decoder))) { 6458 return MCDisassembler::Fail; 6459 } 6460 } 6461 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6462 6463 return S; 6464} 6465 6466static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo, 6467 uint64_t Address, 6468 const MCDisassembler *Decoder) { 6469 if (RegNo > 7) 6470 return MCDisassembler::Fail; 6471 6472 unsigned Register = QPRDecoderTable[RegNo]; 6473 Inst.addOperand(MCOperand::createReg(Register)); 6474 return MCDisassembler::Success; 6475} 6476 6477static const uint16_t QQPRDecoderTable[] = { 6478 ARM::Q0_Q1, ARM::Q1_Q2, ARM::Q2_Q3, ARM::Q3_Q4, 6479 ARM::Q4_Q5, ARM::Q5_Q6, ARM::Q6_Q7 6480}; 6481 6482static DecodeStatus DecodeMQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 6483 uint64_t Address, 6484 const MCDisassembler *Decoder) { 6485 if (RegNo > 6) 6486 return MCDisassembler::Fail; 6487 6488 unsigned Register = QQPRDecoderTable[RegNo]; 6489 Inst.addOperand(MCOperand::createReg(Register)); 6490 return MCDisassembler::Success; 6491} 6492 6493static const uint16_t QQQQPRDecoderTable[] = { 6494 ARM::Q0_Q1_Q2_Q3, ARM::Q1_Q2_Q3_Q4, ARM::Q2_Q3_Q4_Q5, 6495 ARM::Q3_Q4_Q5_Q6, ARM::Q4_Q5_Q6_Q7 6496}; 6497 6498static DecodeStatus DecodeMQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo, 6499 uint64_t Address, 6500 const MCDisassembler *Decoder) { 6501 if (RegNo > 4) 6502 return MCDisassembler::Fail; 6503 6504 unsigned Register = QQQQPRDecoderTable[RegNo]; 6505 Inst.addOperand(MCOperand::createReg(Register)); 6506 return MCDisassembler::Success; 6507} 6508 6509static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val, 6510 uint64_t Address, 6511 const MCDisassembler *Decoder) { 6512 DecodeStatus S = MCDisassembler::Success; 6513 6514 // Parse VPT mask and encode it in the MCInst as an immediate with the same 6515 // format as the it_mask. That is, from the second 'e|t' encode 'e' as 1 and 6516 // 't' as 0 and finish with a 1. 6517 unsigned Imm = 0; 6518 // We always start with a 't'. 6519 unsigned CurBit = 0; 6520 for (int i = 3; i >= 0; --i) { 6521 // If the bit we are looking at is not the same as last one, invert the 6522 // CurBit, if it is the same leave it as is. 6523 CurBit ^= (Val >> i) & 1U; 6524 6525 // Encode the CurBit at the right place in the immediate. 6526 Imm |= (CurBit << i); 6527 6528 // If we are done, finish the encoding with a 1. 6529 if ((Val & ~(~0U << i)) == 0) { 6530 Imm |= 1U << i; 6531 break; 6532 } 6533 } 6534 6535 Inst.addOperand(MCOperand::createImm(Imm)); 6536 6537 return S; 6538} 6539 6540static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned RegNo, 6541 uint64_t Address, 6542 const MCDisassembler *Decoder) { 6543 // The vpred_r operand type includes an MQPR register field derived 6544 // from the encoding. But we don't actually want to add an operand 6545 // to the MCInst at this stage, because AddThumbPredicate will do it 6546 // later, and will infer the register number from the TIED_TO 6547 // constraint. So this is a deliberately empty decoder method that 6548 // will inhibit the auto-generated disassembly code from adding an 6549 // operand at all. 6550 return MCDisassembler::Success; 6551} 6552 6553[[maybe_unused]] static DecodeStatus 6554DecodeVpredNOperand(MCInst &Inst, unsigned RegNo, uint64_t Address, 6555 const MCDisassembler *Decoder) { 6556 // Similar to above, we want to ensure that no operands are added for the 6557 // vpred operands. (This is marked "maybe_unused" for the moment; because 6558 // DecoderEmitter currently (wrongly) omits operands with no instruction bits, 6559 // the decoder doesn't actually call it yet. That will be addressed in a 6560 // future change.) 6561 return MCDisassembler::Success; 6562} 6563 6564static DecodeStatus 6565DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, 6566 const MCDisassembler *Decoder) { 6567 Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::EQ : ARMCC::NE)); 6568 return MCDisassembler::Success; 6569} 6570 6571static DecodeStatus 6572DecodeRestrictedSPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, 6573 const MCDisassembler *Decoder) { 6574 unsigned Code; 6575 switch (Val & 0x3) { 6576 case 0: 6577 Code = ARMCC::GE; 6578 break; 6579 case 1: 6580 Code = ARMCC::LT; 6581 break; 6582 case 2: 6583 Code = ARMCC::GT; 6584 break; 6585 case 3: 6586 Code = ARMCC::LE; 6587 break; 6588 } 6589 Inst.addOperand(MCOperand::createImm(Code)); 6590 return MCDisassembler::Success; 6591} 6592 6593static DecodeStatus 6594DecodeRestrictedUPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, 6595 const MCDisassembler *Decoder) { 6596 Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::HS : ARMCC::HI)); 6597 return MCDisassembler::Success; 6598} 6599 6600static DecodeStatus 6601DecodeRestrictedFPPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address, 6602 const MCDisassembler *Decoder) { 6603 unsigned Code; 6604 switch (Val) { 6605 default: 6606 return MCDisassembler::Fail; 6607 case 0: 6608 Code = ARMCC::EQ; 6609 break; 6610 case 1: 6611 Code = ARMCC::NE; 6612 break; 6613 case 4: 6614 Code = ARMCC::GE; 6615 break; 6616 case 5: 6617 Code = ARMCC::LT; 6618 break; 6619 case 6: 6620 Code = ARMCC::GT; 6621 break; 6622 case 7: 6623 Code = ARMCC::LE; 6624 break; 6625 } 6626 6627 Inst.addOperand(MCOperand::createImm(Code)); 6628 return MCDisassembler::Success; 6629} 6630 6631static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Val, 6632 uint64_t Address, 6633 const MCDisassembler *Decoder) { 6634 DecodeStatus S = MCDisassembler::Success; 6635 6636 unsigned DecodedVal = 64 - Val; 6637 6638 switch (Inst.getOpcode()) { 6639 case ARM::MVE_VCVTf16s16_fix: 6640 case ARM::MVE_VCVTs16f16_fix: 6641 case ARM::MVE_VCVTf16u16_fix: 6642 case ARM::MVE_VCVTu16f16_fix: 6643 if (DecodedVal > 16) 6644 return MCDisassembler::Fail; 6645 break; 6646 case ARM::MVE_VCVTf32s32_fix: 6647 case ARM::MVE_VCVTs32f32_fix: 6648 case ARM::MVE_VCVTf32u32_fix: 6649 case ARM::MVE_VCVTu32f32_fix: 6650 if (DecodedVal > 32) 6651 return MCDisassembler::Fail; 6652 break; 6653 } 6654 6655 Inst.addOperand(MCOperand::createImm(64 - Val)); 6656 6657 return S; 6658} 6659 6660static unsigned FixedRegForVSTRVLDR_SYSREG(unsigned Opcode) { 6661 switch (Opcode) { 6662 case ARM::VSTR_P0_off: 6663 case ARM::VSTR_P0_pre: 6664 case ARM::VSTR_P0_post: 6665 case ARM::VLDR_P0_off: 6666 case ARM::VLDR_P0_pre: 6667 case ARM::VLDR_P0_post: 6668 return ARM::P0; 6669 default: 6670 return 0; 6671 } 6672} 6673 6674template <bool Writeback> 6675static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Val, 6676 uint64_t Address, 6677 const MCDisassembler *Decoder) { 6678 switch (Inst.getOpcode()) { 6679 case ARM::VSTR_FPSCR_pre: 6680 case ARM::VSTR_FPSCR_NZCVQC_pre: 6681 case ARM::VLDR_FPSCR_pre: 6682 case ARM::VLDR_FPSCR_NZCVQC_pre: 6683 case ARM::VSTR_FPSCR_off: 6684 case ARM::VSTR_FPSCR_NZCVQC_off: 6685 case ARM::VLDR_FPSCR_off: 6686 case ARM::VLDR_FPSCR_NZCVQC_off: 6687 case ARM::VSTR_FPSCR_post: 6688 case ARM::VSTR_FPSCR_NZCVQC_post: 6689 case ARM::VLDR_FPSCR_post: 6690 case ARM::VLDR_FPSCR_NZCVQC_post: 6691 const FeatureBitset &featureBits = 6692 ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits(); 6693 6694 if (!featureBits[ARM::HasMVEIntegerOps] && !featureBits[ARM::FeatureVFP2]) 6695 return MCDisassembler::Fail; 6696 } 6697 6698 DecodeStatus S = MCDisassembler::Success; 6699 if (unsigned Sysreg = FixedRegForVSTRVLDR_SYSREG(Inst.getOpcode())) 6700 Inst.addOperand(MCOperand::createReg(Sysreg)); 6701 unsigned Rn = fieldFromInstruction(Val, 16, 4); 6702 unsigned addr = fieldFromInstruction(Val, 0, 7) | 6703 (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8); 6704 6705 if (Writeback) { 6706 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 6707 return MCDisassembler::Fail; 6708 } 6709 if (!Check(S, DecodeT2AddrModeImm7s4(Inst, addr, Address, Decoder))) 6710 return MCDisassembler::Fail; 6711 6712 Inst.addOperand(MCOperand::createImm(ARMCC::AL)); 6713 Inst.addOperand(MCOperand::createReg(0)); 6714 6715 return S; 6716} 6717 6718static inline DecodeStatus 6719DecodeMVE_MEM_pre(MCInst &Inst, unsigned Val, uint64_t Address, 6720 const MCDisassembler *Decoder, unsigned Rn, 6721 OperandDecoder RnDecoder, OperandDecoder AddrDecoder) { 6722 DecodeStatus S = MCDisassembler::Success; 6723 6724 unsigned Qd = fieldFromInstruction(Val, 13, 3); 6725 unsigned addr = fieldFromInstruction(Val, 0, 7) | 6726 (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8); 6727 6728 if (!Check(S, RnDecoder(Inst, Rn, Address, Decoder))) 6729 return MCDisassembler::Fail; 6730 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6731 return MCDisassembler::Fail; 6732 if (!Check(S, AddrDecoder(Inst, addr, Address, Decoder))) 6733 return MCDisassembler::Fail; 6734 6735 return S; 6736} 6737 6738template <int shift> 6739static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val, 6740 uint64_t Address, 6741 const MCDisassembler *Decoder) { 6742 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, 6743 fieldFromInstruction(Val, 16, 3), 6744 DecodetGPRRegisterClass, 6745 DecodeTAddrModeImm7<shift>); 6746} 6747 6748template <int shift> 6749static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val, 6750 uint64_t Address, 6751 const MCDisassembler *Decoder) { 6752 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, 6753 fieldFromInstruction(Val, 16, 4), 6754 DecoderGPRRegisterClass, 6755 DecodeT2AddrModeImm7<shift,1>); 6756} 6757 6758template <int shift> 6759static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val, 6760 uint64_t Address, 6761 const MCDisassembler *Decoder) { 6762 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder, 6763 fieldFromInstruction(Val, 17, 3), 6764 DecodeMQPRRegisterClass, 6765 DecodeMveAddrModeQ<shift>); 6766} 6767 6768template <unsigned MinLog, unsigned MaxLog> 6769static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val, 6770 uint64_t Address, 6771 const MCDisassembler *Decoder) { 6772 DecodeStatus S = MCDisassembler::Success; 6773 6774 if (Val < MinLog || Val > MaxLog) 6775 return MCDisassembler::Fail; 6776 6777 Inst.addOperand(MCOperand::createImm(1LL << Val)); 6778 return S; 6779} 6780 6781template <unsigned start> 6782static DecodeStatus 6783DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, uint64_t Address, 6784 const MCDisassembler *Decoder) { 6785 DecodeStatus S = MCDisassembler::Success; 6786 6787 Inst.addOperand(MCOperand::createImm(start + Val)); 6788 6789 return S; 6790} 6791 6792static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn, 6793 uint64_t Address, 6794 const MCDisassembler *Decoder) { 6795 DecodeStatus S = MCDisassembler::Success; 6796 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 6797 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 6798 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 6799 fieldFromInstruction(Insn, 13, 3)); 6800 unsigned index = fieldFromInstruction(Insn, 4, 1); 6801 6802 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 6803 return MCDisassembler::Fail; 6804 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder))) 6805 return MCDisassembler::Fail; 6806 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6807 return MCDisassembler::Fail; 6808 if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder))) 6809 return MCDisassembler::Fail; 6810 if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder))) 6811 return MCDisassembler::Fail; 6812 6813 return S; 6814} 6815 6816static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn, 6817 uint64_t Address, 6818 const MCDisassembler *Decoder) { 6819 DecodeStatus S = MCDisassembler::Success; 6820 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 6821 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 6822 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 6823 fieldFromInstruction(Insn, 13, 3)); 6824 unsigned index = fieldFromInstruction(Insn, 4, 1); 6825 6826 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6827 return MCDisassembler::Fail; 6828 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6829 return MCDisassembler::Fail; 6830 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 6831 return MCDisassembler::Fail; 6832 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder))) 6833 return MCDisassembler::Fail; 6834 if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder))) 6835 return MCDisassembler::Fail; 6836 if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder))) 6837 return MCDisassembler::Fail; 6838 6839 return S; 6840} 6841 6842static DecodeStatus 6843DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn, uint64_t Address, 6844 const MCDisassembler *Decoder) { 6845 DecodeStatus S = MCDisassembler::Success; 6846 6847 unsigned RdaLo = fieldFromInstruction(Insn, 17, 3) << 1; 6848 unsigned RdaHi = fieldFromInstruction(Insn, 9, 3) << 1; 6849 unsigned Rm = fieldFromInstruction(Insn, 12, 4); 6850 6851 if (RdaHi == 14) { 6852 // This value of RdaHi (really indicating pc, because RdaHi has to 6853 // be an odd-numbered register, so the low bit will be set by the 6854 // decode function below) indicates that we must decode as SQRSHR 6855 // or UQRSHL, which both have a single Rda register field with all 6856 // four bits. 6857 unsigned Rda = fieldFromInstruction(Insn, 16, 4); 6858 6859 switch (Inst.getOpcode()) { 6860 case ARM::MVE_ASRLr: 6861 case ARM::MVE_SQRSHRL: 6862 Inst.setOpcode(ARM::MVE_SQRSHR); 6863 break; 6864 case ARM::MVE_LSLLr: 6865 case ARM::MVE_UQRSHLL: 6866 Inst.setOpcode(ARM::MVE_UQRSHL); 6867 break; 6868 default: 6869 llvm_unreachable("Unexpected starting opcode!"); 6870 } 6871 6872 // Rda as output parameter 6873 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder))) 6874 return MCDisassembler::Fail; 6875 6876 // Rda again as input parameter 6877 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder))) 6878 return MCDisassembler::Fail; 6879 6880 // Rm, the amount to shift by 6881 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 6882 return MCDisassembler::Fail; 6883 6884 if (fieldFromInstruction (Insn, 6, 3) != 4) 6885 return MCDisassembler::SoftFail; 6886 6887 if (Rda == Rm) 6888 return MCDisassembler::SoftFail; 6889 6890 return S; 6891 } 6892 6893 // Otherwise, we decode as whichever opcode our caller has already 6894 // put into Inst. Those all look the same: 6895 6896 // RdaLo,RdaHi as output parameters 6897 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder))) 6898 return MCDisassembler::Fail; 6899 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder))) 6900 return MCDisassembler::Fail; 6901 6902 // RdaLo,RdaHi again as input parameters 6903 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder))) 6904 return MCDisassembler::Fail; 6905 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder))) 6906 return MCDisassembler::Fail; 6907 6908 // Rm, the amount to shift by 6909 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 6910 return MCDisassembler::Fail; 6911 6912 if (Inst.getOpcode() == ARM::MVE_SQRSHRL || 6913 Inst.getOpcode() == ARM::MVE_UQRSHLL) { 6914 unsigned Saturate = fieldFromInstruction(Insn, 7, 1); 6915 // Saturate, the bit position for saturation 6916 Inst.addOperand(MCOperand::createImm(Saturate)); 6917 } 6918 6919 return S; 6920} 6921 6922static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, 6923 uint64_t Address, 6924 const MCDisassembler *Decoder) { 6925 DecodeStatus S = MCDisassembler::Success; 6926 unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) | 6927 fieldFromInstruction(Insn, 13, 3)); 6928 unsigned Qm = ((fieldFromInstruction(Insn, 5, 1) << 3) | 6929 fieldFromInstruction(Insn, 1, 3)); 6930 unsigned imm6 = fieldFromInstruction(Insn, 16, 6); 6931 6932 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder))) 6933 return MCDisassembler::Fail; 6934 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 6935 return MCDisassembler::Fail; 6936 if (!Check(S, DecodeVCVTImmOperand(Inst, imm6, Address, Decoder))) 6937 return MCDisassembler::Fail; 6938 6939 return S; 6940} 6941 6942template <bool scalar, OperandDecoder predicate_decoder> 6943static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, uint64_t Address, 6944 const MCDisassembler *Decoder) { 6945 DecodeStatus S = MCDisassembler::Success; 6946 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6947 unsigned Qn = fieldFromInstruction(Insn, 17, 3); 6948 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder))) 6949 return MCDisassembler::Fail; 6950 6951 unsigned fc; 6952 6953 if (scalar) { 6954 fc = fieldFromInstruction(Insn, 12, 1) << 2 | 6955 fieldFromInstruction(Insn, 7, 1) | 6956 fieldFromInstruction(Insn, 5, 1) << 1; 6957 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 6958 if (!Check(S, DecodeGPRwithZRRegisterClass(Inst, Rm, Address, Decoder))) 6959 return MCDisassembler::Fail; 6960 } else { 6961 fc = fieldFromInstruction(Insn, 12, 1) << 2 | 6962 fieldFromInstruction(Insn, 7, 1) | 6963 fieldFromInstruction(Insn, 0, 1) << 1; 6964 unsigned Qm = fieldFromInstruction(Insn, 5, 1) << 4 | 6965 fieldFromInstruction(Insn, 1, 3); 6966 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder))) 6967 return MCDisassembler::Fail; 6968 } 6969 6970 if (!Check(S, predicate_decoder(Inst, fc, Address, Decoder))) 6971 return MCDisassembler::Fail; 6972 6973 Inst.addOperand(MCOperand::createImm(ARMVCC::None)); 6974 Inst.addOperand(MCOperand::createReg(0)); 6975 Inst.addOperand(MCOperand::createImm(0)); 6976 6977 return S; 6978} 6979 6980static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address, 6981 const MCDisassembler *Decoder) { 6982 DecodeStatus S = MCDisassembler::Success; 6983 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6984 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 6985 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 6986 return MCDisassembler::Fail; 6987 return S; 6988} 6989 6990static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn, 6991 uint64_t Address, 6992 const MCDisassembler *Decoder) { 6993 DecodeStatus S = MCDisassembler::Success; 6994 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6995 Inst.addOperand(MCOperand::createReg(ARM::VPR)); 6996 return S; 6997} 6998 6999static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn, 7000 uint64_t Address, 7001 const MCDisassembler *Decoder) { 7002 const unsigned Rd = fieldFromInstruction(Insn, 8, 4); 7003 const unsigned Rn = fieldFromInstruction(Insn, 16, 4); 7004 const unsigned Imm12 = fieldFromInstruction(Insn, 26, 1) << 11 | 7005 fieldFromInstruction(Insn, 12, 3) << 8 | 7006 fieldFromInstruction(Insn, 0, 8); 7007 const unsigned TypeT3 = fieldFromInstruction(Insn, 25, 1); 7008 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 7009 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 7010 unsigned S = fieldFromInstruction(Insn, 20, 1); 7011 if (sign1 != sign2) 7012 return MCDisassembler::Fail; 7013 7014 // T3 does a zext of imm12, where T2 does a ThumbExpandImm (T2SOImm) 7015 DecodeStatus DS = MCDisassembler::Success; 7016 if ((!Check(DS, 7017 DecodeGPRspRegisterClass(Inst, Rd, Address, Decoder))) || // dst 7018 (!Check(DS, DecodeGPRspRegisterClass(Inst, Rn, Address, Decoder)))) 7019 return MCDisassembler::Fail; 7020 if (TypeT3) { 7021 Inst.setOpcode(sign1 ? ARM::t2SUBspImm12 : ARM::t2ADDspImm12); 7022 Inst.addOperand(MCOperand::createImm(Imm12)); // zext imm12 7023 } else { 7024 Inst.setOpcode(sign1 ? ARM::t2SUBspImm : ARM::t2ADDspImm); 7025 if (!Check(DS, DecodeT2SOImm(Inst, Imm12, Address, Decoder))) // imm12 7026 return MCDisassembler::Fail; 7027 if (!Check(DS, DecodeCCOutOperand(Inst, S, Address, Decoder))) // cc_out 7028 return MCDisassembler::Fail; 7029 } 7030 7031 return DS; 7032} 7033