Searched refs:RHSReg (Results 1 - 5 of 5) sorted by relevance

/freebsd-current/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp207 unsigned RHSReg, bool SetFlags = false,
213 unsigned RHSReg, AArch64_AM::ShiftExtendType ShiftType,
217 unsigned RHSReg, AArch64_AM::ShiftExtendType ExtType,
242 unsigned emitSubs_rr(MVT RetVT, unsigned LHSReg, unsigned RHSReg,
244 unsigned emitSubs_rs(MVT RetVT, unsigned LHSReg, unsigned RHSReg,
252 unsigned RHSReg, uint64_t ShiftImm);
1234 Register RHSReg = getRegForValue(RHS); local
1235 if (!RHSReg)
1237 return emitAddSub_rx(UseAdd, RetVT, LHSReg, RHSReg, ExtendType, 0,
1253 Register RHSReg local
1276 Register RHSReg = getRegForValue(SI->getOperand(0)); local
1288 Register RHSReg = getRegForValue(RHS); local
1298 emitAddSub_rr(bool UseAdd, MVT RetVT, unsigned LHSReg, unsigned RHSReg, bool SetFlags, bool WantResult) argument
1380 emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg, unsigned RHSReg, AArch64_AM::ShiftExtendType ShiftType, uint64_t ShiftImm, bool SetFlags, bool WantResult) argument
1422 emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg, unsigned RHSReg, AArch64_AM::ShiftExtendType ExtType, uint64_t ShiftImm, bool SetFlags, bool WantResult) argument
1521 Register RHSReg = getRegForValue(RHS); local
1567 emitSubs_rr(MVT RetVT, unsigned LHSReg, unsigned RHSReg, bool WantResult) argument
1573 emitSubs_rs(MVT RetVT, unsigned LHSReg, unsigned RHSReg, AArch64_AM::ShiftExtendType ShiftType, uint64_t ShiftImm, bool WantResult) argument
1623 Register RHSReg = getRegForValue(MulLHS); local
1637 Register RHSReg = getRegForValue(SI->getOperand(0)); local
1646 Register RHSReg = getRegForValue(RHS); local
1704 emitLogicalOp_rs(unsigned ISDOpc, MVT RetVT, unsigned LHSReg, unsigned RHSReg, uint64_t ShiftImm) argument
3818 Register RHSReg = getRegForValue(II->getArgOperand(1)); local
[all...]
/freebsd-current/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp51 // if \p LHSReg and \p RHSReg are in the relationship defined by \p Cond, or
54 ARMCC::CondCodes Cond, unsigned LHSReg, unsigned RHSReg,
502 unsigned LHSReg, unsigned RHSReg,
505 return MRI.getType(LHSReg) == MRI.getType(RHSReg) &&
507 validReg(MRI, RHSReg, ExpectedSize, ExpectedRegBankID);
544 auto RHSReg = MIB.getReg(3); local
545 if (!validOpRegPair(MRI, LHSReg, RHSReg, Helper.OperandSize,
555 if (!insertComparison(Helper, I, ResReg, ARMConds.first, LHSReg, RHSReg,
562 RHSReg, ZeroReg))
564 if (!insertComparison(Helper, I, ResReg, ARMConds.second, LHSReg, RHSReg,
501 validOpRegPair(MachineRegisterInfo &MRI, unsigned LHSReg, unsigned RHSReg, unsigned ExpectedSize, unsigned ExpectedRegBankID) const argument
573 insertComparison(CmpConstants Helper, InsertInfo I, unsigned ResReg, ARMCC::CondCodes Cond, unsigned LHSReg, unsigned RHSReg, unsigned PrevRes) const argument
[all...]
/freebsd-current/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FastISel.cpp2131 Register RHSReg = getRegForValue(RHS); local
2133 if (!LHSReg || !RHSReg)
2138 Register ResultReg = fastEmitInst_rri(Opc, RC, RHSReg, LHSReg, CC);
2187 Register RHSReg = getRegForValue(RHS); local
2190 if (!LHSReg || !RHSReg || !CmpLHSReg || !CmpRHSReg)
2212 // Place RHSReg is the passthru of the masked movss/sd operation and put
2216 unsigned MovReg = fastEmitInst_rrrr(MovOpcode, VR128X, RHSReg, CmpReg,
2238 Register VBlendReg = fastEmitInst_rrr(BlendOpcode, VR128, RHSReg, LHSReg,
2260 Register AndNReg = fastEmitInst_rr(Opc[2], VR128, CmpReg, RHSReg);
2332 Register RHSReg local
2912 unsigned RHSReg; local
3073 Register RHSReg = getRegForValue(RHS); local
[all...]
/freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp2996 Register RHSReg = MI.getOperand(2).getReg();
2999 if (!MRI.hasOneNonDBGUse(LHSReg) || !MRI.hasOneNonDBGUse(RHSReg))
3004 MachineInstr *RightHandInst = getDefIgnoringCopies(RHSReg, MRI);
4615 Register RHSReg = MI.getOffsetReg();
4617 auto NewCst = B.buildConstant(MRI.getType(RHSReg), LHSCstOff->Value);
4622 LHSPtrAdd->getOperand(2).setReg(RHSReg);
4737 Register RHSReg = MI.getOperand(2).getReg();
4739 if (tryReassocBinOp(Opc, DstReg, LHSReg, RHSReg, MatchInfo))
4741 if (tryReassocBinOp(Opc, DstReg, RHSReg, LHSReg, MatchInfo))
5800 Register RHSReg
[all...]
/freebsd-current/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp316 unsigned RHSReg; local
318 RHSReg = materializeInt(C, MVT::i32);
320 RHSReg = getRegForValue(RHS);
321 if (!RHSReg)
328 emitInst(Opc, ResultReg).addReg(LHSReg).addReg(RHSReg);

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