Target/AArch64/AArch64FastISel.cpp

207                          unsigned RHSReg, bool SetFlags = false,
213                          unsigned RHSReg, AArch64_AM::ShiftExtendType ShiftType,
217                          unsigned RHSReg, AArch64_AM::ShiftExtendType ExtType,
242   unsigned emitSubs_rr(MVT RetVT, unsigned LHSReg, unsigned RHSReg,
244   unsigned emitSubs_rs(MVT RetVT, unsigned LHSReg, unsigned RHSReg,
252                             unsigned RHSReg, uint64_t ShiftImm);
1234     Register RHSReg = getRegForValue(RHS);
1235     if (!RHSReg)
1237     return emitAddSub_rx(UseAdd, RetVT, LHSReg, RHSReg, ExtendType, 0,
1253       Register RHSReg = getRegForValue(MulLHS);
1254       if (!RHSReg)
1256       ResultReg = emitAddSub_rs(UseAdd, RetVT, LHSReg, RHSReg, AArch64_AM::LSL,
1276           Register RHSReg = getRegForValue(SI->getOperand(0));
1277           if (!RHSReg)
1279           ResultReg = emitAddSub_rs(UseAdd, RetVT, LHSReg, RHSReg, ShiftType,
1288   Register RHSReg = getRegForValue(RHS);
1289   if (!RHSReg)
1293     RHSReg = emitIntExt(SrcVT, RHSReg, RetVT, IsZExt);
1295   return emitAddSub_rr(UseAdd, RetVT, LHSReg, RHSReg, SetFlags, WantResult);
1299                                         unsigned RHSReg, bool SetFlags,
1301   assert(LHSReg && RHSReg && "Invalid register number.");
1304       RHSReg == AArch64::SP || RHSReg == AArch64::WSP)
1328   RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1);
1331       .addReg(RHSReg);
1381                                         unsigned RHSReg,
1385   assert(LHSReg && RHSReg && "Invalid register number.");
1387          RHSReg != AArch64::SP && RHSReg != AArch64::WSP);
1414   RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1);
1417       .addReg(RHSReg)
1423                                         unsigned RHSReg,
1427   assert(LHSReg && RHSReg && "Invalid register number.");
1429          RHSReg != AArch64::XZR && RHSReg != AArch64::WZR);
1458   RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1);
1461       .addReg(RHSReg)
1521   Register RHSReg = getRegForValue(RHS);
1522   if (!RHSReg)
1528       .addReg(RHSReg);
1568                                       unsigned RHSReg, bool WantResult) {
1569   return emitAddSub_rr(/*UseAdd=*/false, RetVT, LHSReg, RHSReg,
1574                                       unsigned RHSReg,
1577   return emitAddSub_rs(/*UseAdd=*/false, RetVT, LHSReg, RHSReg, ShiftType,
1623       Register RHSReg = getRegForValue(MulLHS);
1624       if (!RHSReg)
1626       ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, RHSReg, ShiftVal);
1637         Register RHSReg = getRegForValue(SI->getOperand(0));
1638         if (!RHSReg)
1640         ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, RHSReg, ShiftVal);
1646   Register RHSReg = getRegForValue(RHS);
1647   if (!RHSReg)
1651   ResultReg = fastEmit_rr(VT, VT, ISDOpc, LHSReg, RHSReg);
1705                                            unsigned LHSReg, unsigned RHSReg,
1737       fastEmitInst_rri(Opc, RC, LHSReg, RHSReg,
3704       Register RHSReg = getRegForValue(RHS);
3705       if (!RHSReg)
3709         MulReg = emitSMULL_rr(MVT::i64, LHSReg, RHSReg);
3719         // LHSReg and RHSReg cannot be killed by this Mul, since they are
3721         MulReg = emitMul_rr(VT, LHSReg, RHSReg);
3722         unsigned SMULHReg = fastEmit_rr(VT, VT, ISD::MULHS, LHSReg, RHSReg);
3734       Register RHSReg = getRegForValue(RHS);
3735       if (!RHSReg)
3739         MulReg = emitUMULL_rr(MVT::i64, LHSReg, RHSReg);
3748         // LHSReg and RHSReg cannot be killed by this Mul, since they are
3750         MulReg = emitMul_rr(VT, LHSReg, RHSReg);
3751         unsigned UMULHReg = fastEmit_rr(VT, VT, ISD::MULHU, LHSReg, RHSReg);
3818     Register RHSReg = getRegForValue(II->getArgOperand(1));
3819     if (!LHSReg || !RHSReg)
3823         fastEmitInst_rr(Opc, &AArch64::GPR32RegClass, LHSReg, RHSReg);