Searched refs:READ_REG32 (Results 1 - 13 of 13) sorted by relevance

/freebsd-current/sys/dev/qlxgb/
H A Dqla_inline.h63 if ((READ_REG32(ha, sem_reg) & SEM_LOCK_BIT))
85 READ_REG32(ha, sem_reg);
99 link_speed = READ_REG32(ha, Q8_LINK_SPEED_0);
139 mac_lo = READ_REG32(ha, mac_crb_addr);
140 mac_hi = READ_REG32(ha, (mac_crb_addr + 0x4));
H A Dqla_reg.h228 #define READ_REG32(ha, reg) bus_read_4((ha->pci_reg), reg) macro
229 #define READ_OFFSET32(ha, off) READ_REG32(ha, off)
H A Dqla_hw.c437 data = READ_REG32(ha, Q8_NX_CDRP_CMD_RSP);
446 cdrp->rsp = READ_REG32(ha, Q8_NX_CDRP_CMD_RSP);
447 cdrp->rsp_arg1 = READ_REG32(ha, Q8_NX_CDRP_ARG1);
448 cdrp->rsp_arg2 = READ_REG32(ha, Q8_NX_CDRP_ARG2);
449 cdrp->rsp_arg3 = READ_REG32(ha, Q8_NX_CDRP_ARG3);
1714 hw->txr_comp, hw->txr_free, hw->txr_next, READ_REG32(ha, (ha->hw.tx_prod_reg + 0x1b2000))));
1750 link_state = READ_REG32(ha, Q8_LINK_STATE);
/freebsd-current/sys/dev/qlxgbe/
H A Dql_inline.h55 if ((READ_REG32(ha, sem_reg) & BIT_0))
77 READ_REG32(ha, sem_reg);
91 link_speed = READ_REG32(ha, Q8_LINK_SPEED_0);
H A Dql_isr.c763 data = READ_REG32(ha, Q8_FW_MBOX_CNTRL);
769 data = READ_REG32(ha, Q8_FW_MBOX0);
779 ha->hw.cable_oui = READ_REG32(ha, (Q8_FW_MBOX0 + 4));
781 data = READ_REG32(ha, (Q8_FW_MBOX0 + 8));
787 data = READ_REG32(ha, (Q8_FW_MBOX0 + 12));
809 data = READ_REG32(ha, (Q8_FW_MBOX0 + 16));
824 ha->hw.aen_mb1 = READ_REG32(ha, (Q8_FW_MBOX0 + 4));
825 ha->hw.aen_mb2 = READ_REG32(ha, (Q8_FW_MBOX0 + 8));
826 ha->hw.aen_mb3 = READ_REG32(ha, (Q8_FW_MBOX0 + 12));
827 ha->hw.aen_mb4 = READ_REG32(h
[all...]
H A Dql_misc.c73 if (READ_REG32(ha, wnd_reg) == addr)
85 *val = READ_REG32(ha, Q8_WILD_CARD);
676 mem_off = (uint64_t)(READ_REG32(ha, Q8_BOOTLD_ADDR));
677 mem_size = READ_REG32(ha, Q8_BOOTLD_SIZE);
728 data = READ_REG32(ha, Q8_CMDPEG_STATE);
762 val = READ_REG32(ha, Q8_CMDPEG_STATE);
777 val = READ_REG32(ha, Q8_CMDPEG_STATE);
784 ha->fw_ver_major = READ_REG32(ha, Q8_FW_VER_MAJOR);
785 ha->fw_ver_minor = READ_REG32(ha, Q8_FW_VER_MINOR);
786 ha->fw_ver_sub = READ_REG32(h
[all...]
H A Dql_hw.c1412 data = READ_REG32(ha, Q8_HOST_MBOX_CNTRL);
1447 data = READ_REG32(ha, Q8_FW_MBOX_CNTRL);
1450 data = READ_REG32(ha, Q8_FW_MBOX0);
1477 *fw_mbox++ = READ_REG32(ha, (Q8_FW_MBOX0 + (i << 2)));
2860 ha->hw.mbx_intr_mask_offset = READ_REG32(ha, Q8_MBOX_INT_MASK_MSIX);
3788 link_state = READ_REG32(ha, Q8_LINK_STATE);
3821 val = READ_REG32(ha, Q8_ASIC_TEMPERATURE);
3836 val = READ_REG32(ha, Q8_FIRMWARE_HEARTBEAT);
3856 peg_halt_status1 = READ_REG32(ha, Q8_PEG_HALT_STATUS1);
3857 peg_halt_status2 = READ_REG32(h
[all...]
H A Dql_ioctl.c116 u.rv->val = READ_REG32(ha, u.rv->reg);
H A Dql_hw.h203 #define READ_REG32(ha, reg) bus_read_4((ha->pci_reg), reg) macro
/freebsd-current/sys/dev/qlxge/
H A Dqls_dump.c380 data = READ_REG32(ha, reg);
412 *data = READ_REG32(ha, Q81_CTL_PROC_DATA);
618 *data = READ_REG32(ha, Q81_CTL_XG_SERDES_DATA);
808 data = READ_REG32(ha, Q81_CTL_HOST_CMD_STATUS);
829 data = READ_REG32(ha, Q81_CTL_HOST_CMD_STATUS);
851 *buf = READ_REG32(ha, Q81_CTL_INTR_ENABLE);
872 *data = READ_REG32(ha, Q81_CTL_XGMAC_DATA);
1221 lo_val = READ_REG32(ha,\
1233 hi_val = READ_REG32(ha,\
1424 r_idx = READ_REG32(h
[all...]
H A Dqls_isr.c373 status = READ_REG32(ha, Q81_CTL_STATUS);
384 status = READ_REG32(ha, Q81_CTL_INTR_STATUS1);
H A Dqls_hw.c220 data32 = READ_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_INDEX);
359 data32 = READ_REG32(ha, Q81_CTL_ROUTING_INDEX);
901 ha->rev_id = READ_REG32(ha, Q81_CTL_REV_ID);
960 data32 = READ_REG32(ha, Q81_CTL_CONFIG);
1310 link_state = READ_REG32(ha, Q81_CTL_STATUS);
1760 data32 = READ_REG32(ha, Q81_CTL_FLASH_ADDR);
1798 *data = READ_REG32(ha, Q81_CTL_FLASH_DATA);
1889 data = READ_REG32(ha, Q81_CTL_SEMAPHORE);
1914 data32 = READ_REG32(ha, Q81_CTL_PROC_ADDR);
1953 *data = READ_REG32(h
[all...]
H A Dqls_hw.h898 #define READ_REG32(ha, reg) bus_read_4((ha->pci_reg), reg) macro

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