Searched refs:ProcModel (Results 1 - 4 of 4) sorted by relevance

/freebsd-current/contrib/llvm-project/llvm/utils/TableGen/
H A DSubtargetEmitter.cpp106 unsigned EmitRegisterFileTables(const CodeGenProcModel &ProcModel,
108 void EmitLoadStoreQueueInfo(const CodeGenProcModel &ProcModel,
110 void EmitExtraProcessorInfo(const CodeGenProcModel &ProcModel,
114 void EmitProcessorResourceSubUnits(const CodeGenProcModel &ProcModel,
116 void EmitProcessorResources(const CodeGenProcModel &ProcModel,
119 const CodeGenProcModel &ProcModel);
121 const CodeGenProcModel &ProcModel);
124 const CodeGenProcModel &ProcModel);
125 void GenSchedClassTables(const CodeGenProcModel &ProcModel,
433 for (const CodeGenProcModel &ProcModel
668 EmitProcessorResourceSubUnits( const CodeGenProcModel &ProcModel, raw_ostream &OS) argument
691 EmitRetireControlUnitInfo(const CodeGenProcModel &ProcModel, raw_ostream &OS) argument
705 EmitRegisterFileInfo(const CodeGenProcModel &ProcModel, unsigned NumRegisterFiles, unsigned NumCostEntries, raw_ostream &OS) argument
722 EmitRegisterFileTables(const CodeGenProcModel &ProcModel, raw_ostream &OS) argument
774 EmitLoadStoreQueueInfo(const CodeGenProcModel &ProcModel, raw_ostream &OS) argument
794 EmitExtraProcessorInfo(const CodeGenProcModel &ProcModel, raw_ostream &OS) argument
818 EmitProcessorResources(const CodeGenProcModel &ProcModel, raw_ostream &OS) argument
875 FindWriteResources( const CodeGenSchedRW &SchedWrite, const CodeGenProcModel &ProcModel) argument
928 FindReadAdvance(const CodeGenSchedRW &SchedRead, const CodeGenProcModel &ProcModel) argument
1029 GenSchedClassTables(const CodeGenProcModel &ProcModel, SchedClassTables &SchedTables) argument
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H A DDFAPacketizerEmitter.cpp219 for (const CodeGenProcModel &ProcModel : CGS.procModels()) {
220 if (ProcModel.hasItineraries()) {
221 auto NS = ProcModel.ItinsDef->getValueAsString("PacketizerNamespace");
222 ItinsByNamespace[std::string(NS)].push_back(&ProcModel);
H A DCodeGenSchedule.cpp756 for (auto& ProcModel : ProcModels) {
757 const RecVec &RADefs = ProcModel.ReadAdvanceDefs;
819 const CodeGenProcModel &ProcModel) const {
827 if (&getProcModel(ModelDef) != &ProcModel)
832 "defined for processor " + ProcModel.ModelName +
838 RWSeq, IsRead,ProcModel); local
849 expandRWSeqForProc(Idx, RWSeq, IsRead, ProcModel);
958 const CodeGenProcModel &ProcModel = local
960 ProcIndices.push_back(ProcModel.Index);
961 LLVM_DEBUG(dbgs() << "InstRW on " << ProcModel
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H A DCodeGenSchedule.h568 const CodeGenProcModel &ProcModel) const;

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