utils/TableGen/SubtargetEmitter.cpp

106   unsigned EmitRegisterFileTables(const CodeGenProcModel &ProcModel,
108   void EmitLoadStoreQueueInfo(const CodeGenProcModel &ProcModel,
110   void EmitExtraProcessorInfo(const CodeGenProcModel &ProcModel,
114   void EmitProcessorResourceSubUnits(const CodeGenProcModel &ProcModel,
116   void EmitProcessorResources(const CodeGenProcModel &ProcModel,
119                              const CodeGenProcModel &ProcModel);
121                           const CodeGenProcModel &ProcModel);
124                            const CodeGenProcModel &ProcModel);
125   void GenSchedClassTables(const CodeGenProcModel &ProcModel,
433   for (const CodeGenProcModel &ProcModel : SchedModels.procModels()) {
435     if (!ItinsDefSet.insert(ProcModel.ItinsDef).second)
438     RecVec FUs = ProcModel.ItinsDef->getValueAsListOfDefs("FU");
442     StringRef Name = ProcModel.ItinsDef->getName();
452     RecVec BPs = ProcModel.ItinsDef->getValueAsListOfDefs("BP");
486   for (const CodeGenProcModel &ProcModel : SchedModels.procModels()) {
493     if (!ProcModel.hasItineraries())
496     StringRef Name = ProcModel.ItinsDef->getName();
499     assert(ProcModel.ItinDefList.size() == ItinList.size() && "bad Itins");
505       Record *ItinData = ProcModel.ItinDefList[SchedClassIdx];
669     const CodeGenProcModel &ProcModel, raw_ostream &OS) {
670   OS << "\nstatic const unsigned " << ProcModel.ModelName
674   for (unsigned i = 0, e = ProcModel.ProcResourceDefs.size(); i < e; ++i) {
675     Record *PRDef = ProcModel.ProcResourceDefs[i];
681           SchedModels.findProcResUnits(RUDef, ProcModel, PRDef->getLoc());
683         OS << "  " << ProcModel.getProcResourceIdx(RU) << ", ";
691 static void EmitRetireControlUnitInfo(const CodeGenProcModel &ProcModel,
694   if (Record *RCU = ProcModel.RetireControlUnit) {
705 static void EmitRegisterFileInfo(const CodeGenProcModel &ProcModel,
709     OS << ProcModel.ModelName << "RegisterFiles,\n  " << (1 + NumRegisterFiles);
715     OS << ProcModel.ModelName << "RegisterCosts,\n  ";
722 SubtargetEmitter::EmitRegisterFileTables(const CodeGenProcModel &ProcModel,
724   if (llvm::all_of(ProcModel.RegisterFiles, [](const CodeGenRegisterFile &RF) {
731   OS << "static const llvm::MCRegisterCostEntry " << ProcModel.ModelName
735   for (const CodeGenRegisterFile &RF : ProcModel.RegisterFiles) {
754   OS << "static const llvm::MCRegisterFileDesc " << ProcModel.ModelName
760   for (const CodeGenRegisterFile &RD : ProcModel.RegisterFiles) {
774 void SubtargetEmitter::EmitLoadStoreQueueInfo(const CodeGenProcModel &ProcModel,
777   if (ProcModel.LoadQueue) {
778     const Record *Queue = ProcModel.LoadQueue->getValueAsDef("QueueDescriptor");
779     QueueID = 1 + std::distance(ProcModel.ProcResourceDefs.begin(),
780                                 find(ProcModel.ProcResourceDefs, Queue));
785   if (ProcModel.StoreQueue) {
787         ProcModel.StoreQueue->getValueAsDef("QueueDescriptor");
788     QueueID = 1 + std::distance(ProcModel.ProcResourceDefs.begin(),
789                                 find(ProcModel.ProcResourceDefs, Queue));
794 void SubtargetEmitter::EmitExtraProcessorInfo(const CodeGenProcModel &ProcModel,
798   unsigned NumCostEntries = EmitRegisterFileTables(ProcModel, OS);
801   OS << "\nstatic const llvm::MCExtraProcessorInfo " << ProcModel.ModelName
805   EmitRetireControlUnitInfo(ProcModel, OS);
809   EmitRegisterFileInfo(ProcModel, ProcModel.RegisterFiles.size(),
813   EmitLoadStoreQueueInfo(ProcModel, OS);
818 void SubtargetEmitter::EmitProcessorResources(const CodeGenProcModel &ProcModel,
820   EmitProcessorResourceSubUnits(ProcModel, OS);
823   OS << "static const llvm::MCProcResourceDesc " << ProcModel.ModelName
829   for (unsigned i = 0, e = ProcModel.ProcResourceDefs.size(); i < e; ++i) {
830     Record *PRDef = ProcModel.ProcResourceDefs[i];
849                                          ProcModel, PRDef->getLoc());
850         SuperIdx = ProcModel.getProcResourceIdx(SuperDef);
860       OS << ProcModel.ModelName << "ProcResourceSubUnits + "
876   const CodeGenSchedRW &SchedWrite, const CodeGenProcModel &ProcModel) {
889       if (&SchedModels.getProcModel(ModelDef) != &ProcModel)
894                     "defined for processor " + ProcModel.ModelName +
903   for (Record *WR : ProcModel.WriteResDefs) {
911                       ProcModel.ModelName);
916   // TODO: If ProcModel has a base model (previous generation processor),
919     PrintFatalError(ProcModel.ModelDef->getLoc(),
929                                           const CodeGenProcModel &ProcModel) {
941       if (&SchedModels.getProcModel(ModelDef) != &ProcModel)
946                     "defined for processor " + ProcModel.ModelName +
955   for (Record *RA : ProcModel.ReadAdvanceDefs) {
963                       ProcModel.ModelName);
968   // TODO: If ProcModel has a base model (previous generation processor),
971     PrintFatalError(ProcModel.ModelDef->getLoc(),
1029 void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel,
1032   if (!ProcModel.hasInstrSchedModel())
1055       if (CGT.ProcIndex == ProcModel.Index) {
1070       if (!is_contained(SC.ProcIndices, ProcModel.Index))
1081         if (&ProcModel == &SchedModels.getProcModel(RWModelDef)) {
1095       for (Record *I : ProcModel.ItinRWDefs) {
1104         LLVM_DEBUG(dbgs() << ProcModel.ModelName
1118                                      ProcModel);
1136           FindWriteResources(SchedModels.getSchedWrite(WS), ProcModel);
1197         ExpandProcResources(PRVec, ReleaseAtCycles, AcquireAtCycles, ProcModel);
1203           WPREntry.ProcResourceIdx = ProcModel.getProcResourceIdx(PRVec[PRIdx]);
1251         FindReadAdvance(SchedModels.getSchedRead(Reads[UseIdx]), ProcModel);
1519   for (const CodeGenProcModel &ProcModel : SchedModels.procModels()) {
1520     GenSchedClassTables(ProcModel, SchedTables);