Searched refs:InsInstrs (Results 1 - 11 of 11) sorted by relevance

/freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineCombiner.cpp96 unsigned getDepth(SmallVectorImpl<MachineInstr *> &InsInstrs,
105 SmallVectorImpl<MachineInstr *> &InsInstrs,
110 SmallVectorImpl<MachineInstr *> &InsInstrs,
115 SmallVectorImpl<MachineInstr *> &InsInstrs,
121 SmallVectorImpl<MachineInstr *> &InsInstrs,
203 /// \param InsInstrs is a vector of machine instructions
205 /// of defining machine instruction in \p InsInstrs
208 /// \returns Depth of last instruction in \InsInstrs ("NewRoot")
210 MachineCombiner::getDepth(SmallVectorImpl<MachineInstr *> &InsInstrs, argument
218 for (auto *InstrPtr : InsInstrs) { // fo
333 getLatenciesForInstrSequences( MachineInstr &MI, SmallVectorImpl<MachineInstr *> &InsInstrs, SmallVectorImpl<MachineInstr *> &DelInstrs, MachineTraceMetrics::Trace BlockTrace) argument
352 reduceRegisterPressure( MachineInstr &Root, MachineBasicBlock *MBB, SmallVectorImpl<MachineInstr *> &InsInstrs, SmallVectorImpl<MachineInstr *> &DelInstrs, MachineCombinerPattern Pattern) argument
369 improvesCriticalPathLen( MachineBasicBlock *MBB, MachineInstr *Root, MachineTraceMetrics::Trace BlockTrace, SmallVectorImpl<MachineInstr *> &InsInstrs, SmallVectorImpl<MachineInstr *> &DelInstrs, DenseMap<unsigned, unsigned> &InstrIdxForVirtReg, MachineCombinerPattern Pattern, bool SlackIsAccurate) argument
[all...]
H A DTargetInstrInfo.cpp1059 SmallVectorImpl<MachineInstr *> &InsInstrs,
1162 InsInstrs.push_back(MIB1);
1163 InsInstrs.push_back(MIB2);
1181 SmallVectorImpl<MachineInstr *> &InsInstrs,
1205 reassociateOps(Root, *Prev, Pattern, InsInstrs, DelInstrs, InstIdxForVirtReg);
1056 reassociateOps( MachineInstr &Root, MachineInstr &Prev, MachineCombinerPattern Pattern, SmallVectorImpl<MachineInstr *> &InsInstrs, SmallVectorImpl<MachineInstr *> &DelInstrs, DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const argument
1179 genAlternativeCodeSequence( MachineInstr &Root, MachineCombinerPattern Pattern, SmallVectorImpl<MachineInstr *> &InsInstrs, SmallVectorImpl<MachineInstr *> &DelInstrs, DenseMap<unsigned, unsigned> &InstIdxForVirtReg) const argument
/freebsd-current/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp6596 /// \param [out] InsInstrs is a vector of machine instructions and will
6608 SmallVectorImpl<MachineInstr *> &InsInstrs, unsigned IdxMulOpd,
6662 InsInstrs.push_back(MIB);
6669 SmallVectorImpl<MachineInstr *> &InsInstrs) {
6702 InsInstrs.push_back(MIB);
6710 SmallVectorImpl<MachineInstr *> &InsInstrs,
6742 InsInstrs.push_back(MIB);
6752 MachineInstr &Root, SmallVectorImpl<MachineInstr *> &InsInstrs,
6754 return genFusedMultiply(MF, MRI, TII, Root, InsInstrs, IdxMulOpd, MaddOpc, RC,
6762 SmallVectorImpl<MachineInstr *> &InsInstrs,
[all...]
H A DAArch64InstrInfo.h302 SmallVectorImpl<MachineInstr *> &InsInstrs,
/freebsd-current/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.h228 SmallVectorImpl<MachineInstr *> &InsInstrs,
233 SmallVectorImpl<MachineInstr *> &InsInstrs) const;
354 SmallVectorImpl<MachineInstr *> &InsInstrs,
384 SmallVectorImpl<MachineInstr *> &InsInstrs) const override;
H A DPPCInstrInfo.cpp528 SmallVectorImpl<MachineInstr *> &InsInstrs) const {
529 assert(!InsInstrs.empty() && "Instructions set to be inserted is empty!");
575 for (auto *Inst : InsInstrs) {
577 assert(Operand.isReg() && "Invalid instruction in InsInstrs!");
590 generateLoadForNewConst(ConstPoolIdx, &Root, C->getType(), InsInstrs);
668 SmallVectorImpl<MachineInstr *> &InsInstrs) const {
711 // Insert the toc load instructions into InsInstrs.
712 InsInstrs.insert(InsInstrs.begin(), Load);
713 InsInstrs
755 genAlternativeCodeSequence( MachineInstr &Root, MachineCombinerPattern Pattern, SmallVectorImpl<MachineInstr *> &InsInstrs, SmallVectorImpl<MachineInstr *> &DelInstrs, DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const argument
775 reassociateFMA( MachineInstr &Root, MachineCombinerPattern Pattern, SmallVectorImpl<MachineInstr *> &InsInstrs, SmallVectorImpl<MachineInstr *> &DelInstrs, DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const argument
[all...]
/freebsd-current/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.h246 SmallVectorImpl<MachineInstr *> &InsInstrs) const override;
250 SmallVectorImpl<MachineInstr *> &InsInstrs,
H A DRISCVInstrInfo.cpp1622 SmallVectorImpl<MachineInstr *> &InsInstrs) const {
1626 assert(all_of(InsInstrs,
1638 for (auto *NewMI : InsInstrs) {
1888 SmallVectorImpl<MachineInstr *> &InsInstrs,
1922 InsInstrs.push_back(MIB);
1930 SmallVectorImpl<MachineInstr *> &InsInstrs,
1936 TargetInstrInfo::genAlternativeCodeSequence(Root, Pattern, InsInstrs,
1942 combineFPFusedMultiply(Root, Prev, Pattern, InsInstrs, DelInstrs);
1948 combineFPFusedMultiply(Root, Prev, Pattern, InsInstrs, DelInstrs);
1886 combineFPFusedMultiply(MachineInstr &Root, MachineInstr &Prev, MachineCombinerPattern Pattern, SmallVectorImpl<MachineInstr *> &InsInstrs, SmallVectorImpl<MachineInstr *> &DelInstrs) argument
1928 genAlternativeCodeSequence( MachineInstr &Root, MachineCombinerPattern Pattern, SmallVectorImpl<MachineInstr *> &InsInstrs, SmallVectorImpl<MachineInstr *> &DelInstrs, DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const argument
/freebsd-current/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetInstrInfo.h1209 SmallVectorImpl<MachineInstr *> &InsInstrs) const {}
1252 /// \param InsInstrs - Vector of new instructions that implement P
1259 SmallVectorImpl<MachineInstr *> &InsInstrs,
1274 SmallVectorImpl<MachineInstr *> &InsInstrs,
/freebsd-current/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrInfo.h663 SmallVectorImpl<MachineInstr *> &InsInstrs,
H A DX86InstrInfo.cpp10620 SmallVectorImpl<MachineInstr *> &InsInstrs,
10703 InsInstrs.push_back(Madd);
10704 InsInstrs.push_back(Add);
10710 SmallVectorImpl<MachineInstr *> &InsInstrs,
10716 TargetInstrInfo::genAlternativeCodeSequence(Root, Pattern, InsInstrs,
10720 genAlternativeDpCodeSequence(Root, *this, InsInstrs, DelInstrs,

Completed in 313 milliseconds