Lines Matching refs:InsInstrs

96   unsigned getDepth(SmallVectorImpl<MachineInstr *> &InsInstrs,
105 SmallVectorImpl<MachineInstr *> &InsInstrs,
110 SmallVectorImpl<MachineInstr *> &InsInstrs,
115 SmallVectorImpl<MachineInstr *> &InsInstrs,
121 SmallVectorImpl<MachineInstr *> &InsInstrs,
203 /// \param InsInstrs is a vector of machine instructions
205 /// of defining machine instruction in \p InsInstrs
208 /// \returns Depth of last instruction in \InsInstrs ("NewRoot")
210 MachineCombiner::getDepth(SmallVectorImpl<MachineInstr *> &InsInstrs,
218 for (auto *InstrPtr : InsInstrs) { // for each Use
231 MachineInstr *DefInstr = InsInstrs[II->second];
255 unsigned NewRootIdx = InsInstrs.size() - 1;
334 MachineInstr &MI, SmallVectorImpl<MachineInstr *> &InsInstrs,
337 assert(!InsInstrs.empty() && "Only support sequences that insert instrs.");
339 // NewRoot is the last instruction in the \p InsInstrs vector.
340 MachineInstr *NewRoot = InsInstrs.back();
341 for (unsigned i = 0; i < InsInstrs.size() - 1; i++)
342 NewRootLatency += TSchedModel.computeInstrLatency(InsInstrs[i]);
354 SmallVectorImpl<MachineInstr *> &InsInstrs,
360 // accurate compare of register pressure with DelInstrs or InsInstrs.
372 SmallVectorImpl<MachineInstr *> &InsInstrs,
379 getDepth(InsInstrs, InstrIdxForVirtReg, BlockTrace, *MBB);
406 getLatenciesForInstrSequences(*Root, InsInstrs, DelInstrs, BlockTrace);
408 NewRootLatency = TSchedModel.computeInstrLatency(InsInstrs.back());
446 SmallVectorImpl<MachineInstr *> &InsInstrs,
462 instr2instrSC(InsInstrs, InsInstrsSC);
486 /// Inserts InsInstrs and deletes DelInstrs. Incrementally updates instruction
491 /// \param InsInstrs new instructions to insert in \p MBB
501 SmallVectorImpl<MachineInstr *> &InsInstrs,
508 // better pattern InsInstrs or DelInstrs, so we don't want generate some
510 // entry creation here after InsInstrs is selected as better pattern.
511 // Otherwise the constant pool entry created for InsInstrs will not be deleted
512 // even if InsInstrs is not the better pattern.
513 TII->finalizeInsInstrs(MI, Pattern, InsInstrs);
515 for (auto *InstrPtr : InsInstrs)
530 for (auto *InstrPtr : InsInstrs)
546 SmallVector<MachineInstr *, 16> InsInstrs;
549 TII->genAlternativeCodeSequence(Root, P, InsInstrs, DelInstrs,
554 if (InsInstrs.empty() || !TSchedModel.hasInstrSchedModelOrItineraries())
559 Root, InsInstrs, DelInstrs, TraceEnsemble->getTrace(MBB));
631 SmallVector<MachineInstr *, 16> InsInstrs;
634 TII->genAlternativeCodeSequence(MI, P, InsInstrs, DelInstrs,
639 if (InsInstrs.empty())
649 for (auto const *InstrPtr : InsInstrs)
668 if (reduceRegisterPressure(MI, MBB, InsInstrs, DelInstrs, P)) {
669 // Replace DelInstrs with InsInstrs.
670 insertDeleteInstructions(MBB, MI, InsInstrs, DelInstrs, TraceEnsemble,
683 insertDeleteInstructions(MBB, MI, InsInstrs, DelInstrs, TraceEnsemble,
688 } else if (OptForSize && InsInstrs.size() < DelInstrs.size()) {
690 << InsInstrs.size() << " < "
692 insertDeleteInstructions(MBB, MI, InsInstrs, DelInstrs, TraceEnsemble,
705 if (improvesCriticalPathLen(MBB, &MI, BlockTrace, InsInstrs, DelInstrs,
708 preservesResourceLen(MBB, BlockTrace, InsInstrs, DelInstrs)) {
715 insertDeleteInstructions(MBB, MI, InsInstrs, DelInstrs, TraceEnsemble,
725 for (auto *InstrPtr : InsInstrs)