Searched refs:ull (Results 1 - 25 of 92) sorted by relevance

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/freebsd-9.3-release/sys/contrib/octeon-sdk/
H A Dcvmx-csr-db.c3051 {"OVRFLW" , 0, 4, 0, "R/W", 0, 0, 0ull, 1ull},
3052 {"TXPOP" , 4, 4, 0, "R/W", 0, 0, 0ull, 1ull},
3053 {"TXPSH" , 8, 4, 0, "R/W", 0, 0, 0ull, 1ull},
3055 {"OVRFLW" , 0, 4, 1, "R/W1C", 0, 0, 0ull, 0ull},
3056 {"TXPOP" , 4, 4, 1, "R/W1C", 0, 0, 0ull, 0ull},
[all...]
H A Dcvmx-version.h47 #define OCTEON_SDK_VERSION_NUM 200000366ull
H A Dcvmx-csr-enums.h70 CVMX_PIP_PORT_CFG_MODE_NONE = 0ull, /**< Packet input doesn't perform any
72 CVMX_PIP_PORT_CFG_MODE_SKIPL2 = 1ull,/**< Full packet processing is performed
75 CVMX_PIP_PORT_CFG_MODE_SKIPIP = 2ull /**< Input packets are assumed to be IP.
90 CVMX_PIP_QOS_WATCH_DISABLE = 0ull, /**< QoS watcher is diabled */
91 CVMX_PIP_QOS_WATCH_PROTNH = 1ull, /**< QoS watcher will match based on the IP protocol */
92 CVMX_PIP_QOS_WATCH_TCP = 2ull, /**< QoS watcher will match TCP packets to a specific destination port */
93 CVMX_PIP_QOS_WATCH_UDP = 3ull /**< QoS watcher will match UDP packets to a specific destination port */
102 CVMX_PIP_TAG_MODE_TUPLE = 0ull, /**< Always use tuple tag algorithm. This is the only mode supported on Pass 1 */
103 CVMX_PIP_TAG_MODE_MASK = 1ull, /**< Always use mask tag algorithm */
104 CVMX_PIP_TAG_MODE_IP_OR_MASK = 2ull, /**< I
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H A Dcvmx-tra.h250 CVMX_TRA_FILT_NOP = 1ull<<0, /**< none */
251 CVMX_TRA_FILT_LDT = 1ull<<1, /**< don't allocate L2 or L1 */
252 CVMX_TRA_FILT_LDI = 1ull<<2, /**< don't allocate L1 */
253 CVMX_TRA_FILT_PL2 = 1ull<<3, /**< pref L2 */
254 CVMX_TRA_FILT_RPL2 = 1ull<<4, /**< mark for replacement in L2 */
255 CVMX_TRA_FILT_DWB = 1ull<<5, /**< clear L2 dirty bit (no writeback) + RPL2 */
256 CVMX_TRA_FILT_LDD = 1ull<<8, /**< normal load */
257 CVMX_TRA_FILT_PSL1 = 1ull<<9, /**< pref L1, bypass L2 */
258 CVMX_TRA_FILT_IOBDMA = 1ull<<15, /**< store reflection by IOB for prior load */
259 CVMX_TRA_FILT_STF = 1ull<<1
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H A Dcvmx-error-init-cn38xxp2.c186 info.status_mask = 1ull<<3 /* sec_err */;
188 info.enable_mask = 1ull<<1 /* sec_intena */;
194 info.parent.status_mask = 1ull<<16 /* l2c */;
202 info.status_mask = 1ull<<4 /* ded_err */;
204 info.enable_mask = 1ull<<2 /* ded_intena */;
210 info.parent.status_mask = 1ull<<16 /* l2c */;
219 info.status_mask = 1ull<<3 /* sec_err */;
221 info.enable_mask = 1ull<<1 /* sec_intena */;
227 info.parent.status_mask = 1ull<<16 /* l2c */;
240 info.status_mask = 1ull<<
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H A Dcvmx-error-init-cn56xx.c216 info.status_mask = 1ull<<0 /* odblovf */;
218 info.enable_mask = 1ull<<0 /* ovfena */;
224 info.parent.status_mask = 1ull<<62 /* mii */;
252 info.status_mask = 1ull<<1 /* idblovf */;
254 info.enable_mask = 1ull<<1 /* ivfena */;
260 info.parent.status_mask = 1ull<<62 /* mii */;
292 info.status_mask = 1ull<<4 /* data_drp */;
294 info.enable_mask = 1ull<<4 /* data_drpena */;
300 info.parent.status_mask = 1ull<<62 /* mii */;
313 info.status_mask = 1ull<<
[all...]
H A Dcvmx-error-init-cn31xx.c160 info.status_mask = 1ull<<0 /* fsyncmissed */;
162 info.enable_mask = 1ull<<0 /* fsyncmissed */;
168 info.parent.status_mask = 1ull<<57 /* pcm */;
176 info.status_mask = 1ull<<1 /* fsyncextra */;
178 info.enable_mask = 1ull<<1 /* fsyncextra */;
184 info.parent.status_mask = 1ull<<57 /* pcm */;
192 info.status_mask = 1ull<<6 /* txempty */;
194 info.enable_mask = 1ull<<6 /* txempty */;
200 info.parent.status_mask = 1ull<<57 /* pcm */;
208 info.status_mask = 1ull<<
[all...]
H A Dcvmx-error-init-cn56xxp1.c216 info.status_mask = 1ull<<0 /* odblovf */;
218 info.enable_mask = 1ull<<0 /* ovfena */;
224 info.parent.status_mask = 1ull<<62 /* mii */;
252 info.status_mask = 1ull<<1 /* idblovf */;
254 info.enable_mask = 1ull<<1 /* ivfena */;
260 info.parent.status_mask = 1ull<<62 /* mii */;
292 info.status_mask = 1ull<<4 /* data_drp */;
294 info.enable_mask = 1ull<<4 /* data_drpena */;
300 info.parent.status_mask = 1ull<<62 /* mii */;
313 info.status_mask = 1ull<<
[all...]
H A Dcvmx-error-init-cn50xx.c156 info.status_mask = 1ull<<0 /* fsyncmissed */;
158 info.enable_mask = 1ull<<0 /* fsyncmissed */;
164 info.parent.status_mask = 1ull<<57 /* pcm */;
172 info.status_mask = 1ull<<1 /* fsyncextra */;
174 info.enable_mask = 1ull<<1 /* fsyncextra */;
180 info.parent.status_mask = 1ull<<57 /* pcm */;
188 info.status_mask = 1ull<<6 /* txempty */;
190 info.enable_mask = 1ull<<6 /* txempty */;
196 info.parent.status_mask = 1ull<<57 /* pcm */;
204 info.status_mask = 1ull<<
[all...]
H A Dcvmx-error-init-cn58xx.c186 info.status_mask = 1ull<<3 /* sec_err */;
188 info.enable_mask = 1ull<<1 /* sec_intena */;
194 info.parent.status_mask = 1ull<<16 /* l2c */;
202 info.status_mask = 1ull<<4 /* ded_err */;
204 info.enable_mask = 1ull<<2 /* ded_intena */;
210 info.parent.status_mask = 1ull<<16 /* l2c */;
219 info.status_mask = 1ull<<3 /* sec_err */;
221 info.enable_mask = 1ull<<1 /* sec_intena */;
227 info.parent.status_mask = 1ull<<16 /* l2c */;
240 info.status_mask = 1ull<<
[all...]
H A Dcvmx-error-init-cn58xxp1.c186 info.status_mask = 1ull<<3 /* sec_err */;
188 info.enable_mask = 1ull<<1 /* sec_intena */;
194 info.parent.status_mask = 1ull<<16 /* l2c */;
202 info.status_mask = 1ull<<4 /* ded_err */;
204 info.enable_mask = 1ull<<2 /* ded_intena */;
210 info.parent.status_mask = 1ull<<16 /* l2c */;
219 info.status_mask = 1ull<<3 /* sec_err */;
221 info.enable_mask = 1ull<<1 /* sec_intena */;
227 info.parent.status_mask = 1ull<<16 /* l2c */;
240 info.status_mask = 1ull<<
[all...]
H A Dcvmx-error-init-cn63xx.c216 info.status_mask = 1ull<<0 /* odblovf */;
218 info.enable_mask = 1ull<<0 /* ovfena */;
224 info.parent.status_mask = 1ull<<62 /* mii */;
252 info.status_mask = 1ull<<1 /* idblovf */;
254 info.enable_mask = 1ull<<1 /* ivfena */;
260 info.parent.status_mask = 1ull<<62 /* mii */;
292 info.status_mask = 1ull<<4 /* data_drp */;
294 info.enable_mask = 1ull<<4 /* data_drpena */;
300 info.parent.status_mask = 1ull<<62 /* mii */;
313 info.status_mask = 1ull<<
[all...]
H A Dcvmx-error-init-cn30xx.c156 info.status_mask = 1ull<<0 /* fsyncmissed */;
158 info.enable_mask = 1ull<<0 /* fsyncmissed */;
164 info.parent.status_mask = 1ull<<57 /* pcm */;
172 info.status_mask = 1ull<<1 /* fsyncextra */;
174 info.enable_mask = 1ull<<1 /* fsyncextra */;
180 info.parent.status_mask = 1ull<<57 /* pcm */;
188 info.status_mask = 1ull<<6 /* txempty */;
190 info.enable_mask = 1ull<<6 /* txempty */;
196 info.parent.status_mask = 1ull<<57 /* pcm */;
204 info.status_mask = 1ull<<
[all...]
H A Dcvmx-error-init-cn38xx.c186 info.status_mask = 1ull<<3 /* sec_err */;
188 info.enable_mask = 1ull<<1 /* sec_intena */;
194 info.parent.status_mask = 1ull<<16 /* l2c */;
202 info.status_mask = 1ull<<4 /* ded_err */;
204 info.enable_mask = 1ull<<2 /* ded_intena */;
210 info.parent.status_mask = 1ull<<16 /* l2c */;
219 info.status_mask = 1ull<<3 /* sec_err */;
221 info.enable_mask = 1ull<<1 /* sec_intena */;
227 info.parent.status_mask = 1ull<<16 /* l2c */;
240 info.status_mask = 1ull<<
[all...]
H A Dcvmx-error-init-cn52xx.c188 info.status_mask = 1ull<<0 /* odblovf */;
190 info.enable_mask = 1ull<<0 /* ovfena */;
196 info.parent.status_mask = 1ull<<62 /* mii */;
224 info.status_mask = 1ull<<1 /* idblovf */;
226 info.enable_mask = 1ull<<1 /* ivfena */;
232 info.parent.status_mask = 1ull<<62 /* mii */;
264 info.status_mask = 1ull<<4 /* data_drp */;
266 info.enable_mask = 1ull<<4 /* data_drpena */;
272 info.parent.status_mask = 1ull<<62 /* mii */;
285 info.status_mask = 1ull<<
[all...]
H A Dcvmx-pip.h75 CVMX_PIP_L4_NO_ERR = 0ull,
77 CVMX_PIP_L4_MAL_ERR = 1ull,
79 CVMX_PIP_CHK_ERR = 2ull,
81 CVMX_PIP_L4_LENGTH_ERR = 3ull,
83 CVMX_PIP_BAD_PRT_ERR = 4ull,
85 CVMX_PIP_TCP_FLG8_ERR = 8ull,
87 CVMX_PIP_TCP_FLG9_ERR = 9ull,
89 CVMX_PIP_TCP_FLG10_ERR = 10ull,
91 CVMX_PIP_TCP_FLG11_ERR = 11ull,
93 CVMX_PIP_TCP_FLG12_ERR = 12ull,
[all...]
H A Dcvmx-error-init-cn52xxp1.c186 info.status_mask = 1ull<<0 /* odblovf */;
188 info.enable_mask = 1ull<<0 /* ovfena */;
194 info.parent.status_mask = 1ull<<62 /* mii */;
222 info.status_mask = 1ull<<1 /* idblovf */;
224 info.enable_mask = 1ull<<1 /* ivfena */;
230 info.parent.status_mask = 1ull<<62 /* mii */;
262 info.status_mask = 1ull<<4 /* data_drp */;
264 info.enable_mask = 1ull<<4 /* data_drpena */;
270 info.parent.status_mask = 1ull<<62 /* mii */;
283 info.status_mask = 1ull<<
[all...]
H A Dcvmx-error-init-cn63xxp1.c216 info.status_mask = 1ull<<0 /* odblovf */;
218 info.enable_mask = 1ull<<0 /* ovfena */;
224 info.parent.status_mask = 1ull<<62 /* mii */;
252 info.status_mask = 1ull<<1 /* idblovf */;
254 info.enable_mask = 1ull<<1 /* ivfena */;
260 info.parent.status_mask = 1ull<<62 /* mii */;
292 info.status_mask = 1ull<<4 /* data_drp */;
294 info.enable_mask = 1ull<<4 /* data_drpena */;
300 info.parent.status_mask = 1ull<<62 /* mii */;
313 info.status_mask = 1ull<<
[all...]
H A Dcvmx-tra.c252 if ((filter & CVMX_TRA_FILT_ALL) == -1ull)
260 cmd |= 1ull<<0;
262 cmd |= 1ull<<1;
264 cmd |= 1ull<<2;
266 cmd |= 1ull<<3;
268 cmd |= 1ull<<4;
270 cmd |= 1ull<<5;
272 cmd |= 1ull<<6;
274 cmd |= 1ull<<7;
276 cmd |= 1ull<<
[all...]
H A Dcvmx-pcie.h65 #define CVMX_PCIE_BAR1_PHYS_BASE ((1ull << 32) - (1ull << 28))
66 #define CVMX_PCIE_BAR1_PHYS_SIZE (1ull << 28)
72 #define CVMX_PCIE_BAR1_RC_BASE (1ull << 41)
/freebsd-9.3-release/contrib/libstdc++/include/ext/pb_ds/detail/resize_policy/
H A Dhash_prime_size_policy_imp.hpp91 /* 30 */ (std::size_t)8589934583ull,
92 /* 31 */ (std::size_t)17179869143ull,
93 /* 32 */ (std::size_t)34359738337ull,
94 /* 33 */ (std::size_t)68719476731ull,
95 /* 34 */ (std::size_t)137438953447ull,
96 /* 35 */ (std::size_t)274877906899ull,
97 /* 36 */ (std::size_t)549755813881ull,
98 /* 37 */ (std::size_t)1099511627689ull,
99 /* 38 */ (std::size_t)2199023255531ull,
100 /* 39 */ (std::size_t)4398046511093ull,
[all...]
/freebsd-9.3-release/contrib/ofed/management/libibmad/src/
H A Dsa.c88 #define IB_PR_COMPMASK_DGID (1ull<<2)
89 #define IB_PR_COMPMASK_SGID (1ull<<3)
90 #define IB_PR_COMPMASK_DLID (1ull<<4)
91 #define IB_PR_COMPMASK_SLID (1ull<<5)
92 #define IB_PR_COMPMASK_RAWTRAFIC (1ull<<6)
93 #define IB_PR_COMPMASK_RESV0 (1ull<<7)
94 #define IB_PR_COMPMASK_FLOWLABEL (1ull<<8)
95 #define IB_PR_COMPMASK_HOPLIMIT (1ull<<9)
96 #define IB_PR_COMPMASK_TCLASS (1ull<<10)
97 #define IB_PR_COMPMASK_REVERSIBLE (1ull<<1
[all...]
/freebsd-9.3-release/contrib/libpcap/
H A Dpcap-int.h69 #define SWAPLL(ull) ((ull & 0xff00000000000000) >> 56) | \
70 ((ull & 0x00ff000000000000) >> 40) | \
71 ((ull & 0x0000ff0000000000) >> 24) | \
72 ((ull & 0x000000ff00000000) >> 8) | \
73 ((ull & 0x00000000ff000000) << 8) | \
74 ((ull & 0x0000000000ff0000) << 24) | \
75 ((ull & 0x000000000000ff00) << 40) | \
76 ((ull & 0x00000000000000ff) << 56)
84 #define SWAPLL(ull) ((ul
[all...]
/freebsd-9.3-release/contrib/sendmail/libsm/
H A Dt-types.c26 ULONGLONG_T ull; local
88 ull = ULLONG_MAX;
89 SM_TEST(ull + 1 == 0);
90 sm_snprintf(buf, sizeof(buf), "%llx", ull);
/freebsd-9.3-release/contrib/libstdc++/include/tr1/
H A Dhashtable_policy.h138 __ulongsize != 8 ? 4294967291ul : (unsigned long)6442450933ull,
139 (unsigned long)8589934583ull,
140 (unsigned long)12884901857ull, (unsigned long)17179869143ull,
141 (unsigned long)25769803693ull, (unsigned long)34359738337ull,
142 (unsigned long)51539607367ull, (unsigned long)68719476731ull,
143 (unsigned long)103079215087ull, (unsigned long)137438953447ull,
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