1215976Sjmallett/***********************license start*************** 2215976Sjmallett * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18215976Sjmallett * * Neither the name of Cavium Networks nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29215976Sjmallett * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * @file 43215976Sjmallett * 44215976Sjmallett * Automatically generated error messages for cn63xxp1. 45215976Sjmallett * 46215976Sjmallett * This file is auto generated. Do not edit. 47215976Sjmallett * 48215976Sjmallett * <hr>$Revision$<hr> 49215976Sjmallett * 50215976Sjmallett * <hr><h2>Error tree for CN63XXP1</h2> 51215976Sjmallett * @dot 52215976Sjmallett * digraph cn63xxp1 53215976Sjmallett * { 54215976Sjmallett * rankdir=LR; 55215976Sjmallett * node [shape=record, width=.1, height=.1, fontsize=8, font=helvitica]; 56215976Sjmallett * edge [fontsize=7, font=helvitica]; 57215976Sjmallett * cvmx_root [label="ROOT|<root>root"]; 58215976Sjmallett * cvmx_ciu_int0_sum0 [label="CIU_INTX_SUM0(0)|<mii>mii"]; 59215976Sjmallett * cvmx_mix0_isr [label="MIXX_ISR(0)|<odblovf>odblovf|<idblovf>idblovf|<data_drp>data_drp|<irun>irun|<orun>orun"]; 60215976Sjmallett * cvmx_ciu_int0_sum0:mii:e -> cvmx_mix0_isr [label="mii"]; 61215976Sjmallett * cvmx_root:root:e -> cvmx_ciu_int0_sum0 [label="root"]; 62215976Sjmallett * cvmx_ciu_int_sum1 [label="CIU_INT_SUM1|<mii1>mii1|<nand>nand"]; 63215976Sjmallett * cvmx_mix1_isr [label="MIXX_ISR(1)|<odblovf>odblovf|<idblovf>idblovf|<data_drp>data_drp|<irun>irun|<orun>orun"]; 64215976Sjmallett * cvmx_ciu_int_sum1:mii1:e -> cvmx_mix1_isr [label="mii1"]; 65215976Sjmallett * cvmx_ndf_int [label="NDF_INT|<wdog>wdog|<sm_bad>sm_bad|<ecc_1bit>ecc_1bit|<ecc_mult>ecc_mult|<ovrf>ovrf"]; 66215976Sjmallett * cvmx_ciu_int_sum1:nand:e -> cvmx_ndf_int [label="nand"]; 67215976Sjmallett * cvmx_root:root:e -> cvmx_ciu_int_sum1 [label="root"]; 68215976Sjmallett * cvmx_ciu_block_int [label="CIU_BLOCK_INT|<l2c>l2c|<ipd>ipd|<pow>pow|<rad>rad|<asxpcs0>asxpcs0|<pip>pip|<pko>pko|<pem0>pem0|<pem1>pem1|<fpa>fpa|<usb>usb|<mio>mio|<dfm>dfm|<tim>tim|<lmc0>lmc0|<key>key|<gmx0>gmx0|<iob>iob|<agl>agl|<zip>zip|<dfa>dfa|<srio0>srio0|<srio1>srio1|<sli>sli|<dpi>dpi"]; 69215976Sjmallett * cvmx_l2c_int_reg [label="L2C_INT_REG|<holerd>holerd|<holewr>holewr|<vrtwr>vrtwr|<vrtidrng>vrtidrng|<vrtadrng>vrtadrng|<vrtpe>vrtpe|<tad0>tad0"]; 70215976Sjmallett * cvmx_l2c_err_tdt0 [label="L2C_ERR_TDTX(0)|<vsbe>vsbe|<vdbe>vdbe|<sbe>sbe|<dbe>dbe"]; 71215976Sjmallett * cvmx_l2c_int_reg:tad0:e -> cvmx_l2c_err_tdt0 [label="tad0"]; 72215976Sjmallett * cvmx_l2c_err_ttg0 [label="L2C_ERR_TTGX(0)|<noway>noway|<sbe>sbe|<dbe>dbe"]; 73215976Sjmallett * cvmx_l2c_int_reg:tad0:e -> cvmx_l2c_err_ttg0 [label="tad0"]; 74215976Sjmallett * cvmx_ciu_block_int:l2c:e -> cvmx_l2c_int_reg [label="l2c"]; 75215976Sjmallett * cvmx_ipd_int_sum [label="IPD_INT_SUM|<prc_par0>prc_par0|<prc_par1>prc_par1|<prc_par2>prc_par2|<prc_par3>prc_par3|<bp_sub>bp_sub|<dc_ovr>dc_ovr|<cc_ovr>cc_ovr|<c_coll>c_coll|<d_coll>d_coll|<bc_ovr>bc_ovr"]; 76215976Sjmallett * cvmx_ciu_block_int:ipd:e -> cvmx_ipd_int_sum [label="ipd"]; 77215976Sjmallett * cvmx_pow_ecc_err [label="POW_ECC_ERR|<sbe>sbe|<dbe>dbe|<rpe>rpe|<iop>iop"]; 78215976Sjmallett * cvmx_ciu_block_int:pow:e -> cvmx_pow_ecc_err [label="pow"]; 79215976Sjmallett * cvmx_rad_reg_error [label="RAD_REG_ERROR|<doorbell>doorbell"]; 80215976Sjmallett * cvmx_ciu_block_int:rad:e -> cvmx_rad_reg_error [label="rad"]; 81215976Sjmallett * cvmx_pcs0_int0_reg [label="PCSX_INTX_REG(0,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"]; 82215976Sjmallett * cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int0_reg [label="asxpcs0"]; 83215976Sjmallett * cvmx_pcs0_int1_reg [label="PCSX_INTX_REG(1,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"]; 84215976Sjmallett * cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int1_reg [label="asxpcs0"]; 85215976Sjmallett * cvmx_pcs0_int2_reg [label="PCSX_INTX_REG(2,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"]; 86215976Sjmallett * cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int2_reg [label="asxpcs0"]; 87215976Sjmallett * cvmx_pcs0_int3_reg [label="PCSX_INTX_REG(3,0)|<an_err>an_err|<txfifu>txfifu|<txfifo>txfifo|<txbad>txbad|<rxbad>rxbad|<rxlock>rxlock|<an_bad>an_bad|<sync_bad>sync_bad|<dbg_sync>dbg_sync"]; 88215976Sjmallett * cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcs0_int3_reg [label="asxpcs0"]; 89215976Sjmallett * cvmx_pcsx0_int_reg [label="PCSXX_INT_REG(0)|<txflt>txflt|<rxbad>rxbad|<rxsynbad>rxsynbad|<synlos>synlos|<algnlos>algnlos|<dbg_sync>dbg_sync"]; 90215976Sjmallett * cvmx_ciu_block_int:asxpcs0:e -> cvmx_pcsx0_int_reg [label="asxpcs0"]; 91215976Sjmallett * cvmx_pip_int_reg [label="PIP_INT_REG|<prtnxa>prtnxa|<badtag>badtag|<skprunt>skprunt|<todoovr>todoovr|<feperr>feperr|<beperr>beperr|<punyerr>punyerr"]; 92215976Sjmallett * cvmx_ciu_block_int:pip:e -> cvmx_pip_int_reg [label="pip"]; 93215976Sjmallett * cvmx_pko_reg_error [label="PKO_REG_ERROR|<parity>parity|<doorbell>doorbell|<currzero>currzero"]; 94215976Sjmallett * cvmx_ciu_block_int:pko:e -> cvmx_pko_reg_error [label="pko"]; 95215976Sjmallett * cvmx_pem0_int_sum [label="PEMX_INT_SUM(0)|<se>se|<up_b1>up_b1|<up_b2>up_b2|<up_bx>up_bx|<un_b1>un_b1|<un_b2>un_b2|<un_bx>un_bx|<rdlk>rdlk|<crs_er>crs_er|<crs_dr>crs_dr|<exc>exc"]; 96215976Sjmallett * cvmx_pem0_dbg_info [label="PEMX_DBG_INFO(0)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"]; 97215976Sjmallett * cvmx_pem0_int_sum:exc:e -> cvmx_pem0_dbg_info [label="exc"]; 98215976Sjmallett * cvmx_ciu_block_int:pem0:e -> cvmx_pem0_int_sum [label="pem0"]; 99215976Sjmallett * cvmx_pem1_int_sum [label="PEMX_INT_SUM(1)|<se>se|<up_b1>up_b1|<up_b2>up_b2|<up_bx>up_bx|<un_b1>un_b1|<un_b2>un_b2|<un_bx>un_bx|<rdlk>rdlk|<crs_er>crs_er|<crs_dr>crs_dr|<exc>exc"]; 100215976Sjmallett * cvmx_pem1_dbg_info [label="PEMX_DBG_INFO(1)|<spoison>spoison|<rtlplle>rtlplle|<recrce>recrce|<rpoison>rpoison|<rcemrc>rcemrc|<rnfemrc>rnfemrc|<rfemrc>rfemrc|<rpmerc>rpmerc|<rptamrc>rptamrc|<rumep>rumep|<rvdm>rvdm|<acto>acto|<rte>rte|<mre>mre|<rdwdle>rdwdle|<rtwdle>rtwdle|<dpeoosd>dpeoosd|<fcpvwt>fcpvwt|<rpe>rpe|<fcuv>fcuv|<rqo>rqo|<rauc>rauc|<racur>racur|<racca>racca|<caar>caar|<rarwdns>rarwdns|<ramtlp>ramtlp|<racpp>racpp|<rawwpp>rawwpp|<ecrc_e>ecrc_e"]; 101215976Sjmallett * cvmx_pem1_int_sum:exc:e -> cvmx_pem1_dbg_info [label="exc"]; 102215976Sjmallett * cvmx_ciu_block_int:pem1:e -> cvmx_pem1_int_sum [label="pem1"]; 103215976Sjmallett * cvmx_fpa_int_sum [label="FPA_INT_SUM|<fed0_sbe>fed0_sbe|<fed0_dbe>fed0_dbe|<fed1_sbe>fed1_sbe|<fed1_dbe>fed1_dbe|<q0_und>q0_und|<q0_coff>q0_coff|<q0_perr>q0_perr|<q1_und>q1_und|<q1_coff>q1_coff|<q1_perr>q1_perr|<q2_und>q2_und|<q2_coff>q2_coff|<q2_perr>q2_perr|<q3_und>q3_und|<q3_coff>q3_coff|<q3_perr>q3_perr|<q4_und>q4_und|<q4_coff>q4_coff|<q4_perr>q4_perr|<q5_und>q5_und|<q5_coff>q5_coff|<q5_perr>q5_perr|<q6_und>q6_und|<q6_coff>q6_coff|<q6_perr>q6_perr|<q7_und>q7_und|<q7_coff>q7_coff|<q7_perr>q7_perr"]; 104215976Sjmallett * cvmx_ciu_block_int:fpa:e -> cvmx_fpa_int_sum [label="fpa"]; 105215976Sjmallett * cvmx_uctl0_int_reg [label="UCTLX_INT_REG(0)|<pp_psh_f>pp_psh_f|<er_psh_f>er_psh_f|<or_psh_f>or_psh_f|<cf_psh_f>cf_psh_f|<wb_psh_f>wb_psh_f|<wb_pop_e>wb_pop_e|<oc_ovf_e>oc_ovf_e|<ec_ovf_e>ec_ovf_e"]; 106215976Sjmallett * cvmx_ciu_block_int:usb:e -> cvmx_uctl0_int_reg [label="usb"]; 107215976Sjmallett * cvmx_mio_boot_err [label="MIO_BOOT_ERR|<adr_err>adr_err|<wait_err>wait_err"]; 108215976Sjmallett * cvmx_ciu_block_int:mio:e -> cvmx_mio_boot_err [label="mio"]; 109215976Sjmallett * cvmx_mio_rst_int [label="MIO_RST_INT|<rst_link0>rst_link0|<rst_link1>rst_link1|<perst0>perst0|<perst1>perst1"]; 110215976Sjmallett * cvmx_ciu_block_int:mio:e -> cvmx_mio_rst_int [label="mio"]; 111215976Sjmallett * cvmx_dfm_fnt_stat [label="DFM_FNT_STAT|<sbe_err>sbe_err|<dbe_err>dbe_err"]; 112215976Sjmallett * cvmx_ciu_block_int:dfm:e -> cvmx_dfm_fnt_stat [label="dfm"]; 113215976Sjmallett * cvmx_tim_reg_error [label="TIM_REG_ERROR|<mask>mask"]; 114215976Sjmallett * cvmx_ciu_block_int:tim:e -> cvmx_tim_reg_error [label="tim"]; 115215976Sjmallett * cvmx_lmc0_int [label="LMCX_INT(0)|<sec_err>sec_err|<nxm_wr_err>nxm_wr_err|<ded_err>ded_err"]; 116215976Sjmallett * cvmx_ciu_block_int:lmc0:e -> cvmx_lmc0_int [label="lmc0"]; 117215976Sjmallett * cvmx_key_int_sum [label="KEY_INT_SUM|<ked0_sbe>ked0_sbe|<ked0_dbe>ked0_dbe|<ked1_sbe>ked1_sbe|<ked1_dbe>ked1_dbe"]; 118215976Sjmallett * cvmx_ciu_block_int:key:e -> cvmx_key_int_sum [label="key"]; 119215976Sjmallett * cvmx_gmx0_bad_reg [label="GMXX_BAD_REG(0)|<out_ovr>out_ovr|<loststat>loststat|<statovr>statovr|<inb_nxa>inb_nxa"]; 120215976Sjmallett * cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_bad_reg [label="gmx0"]; 121215976Sjmallett * cvmx_gmx0_rx0_int_reg [label="GMXX_RXX_INT_REG(0,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"]; 122215976Sjmallett * cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_rx0_int_reg [label="gmx0"]; 123215976Sjmallett * cvmx_gmx0_rx1_int_reg [label="GMXX_RXX_INT_REG(1,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"]; 124215976Sjmallett * cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_rx1_int_reg [label="gmx0"]; 125215976Sjmallett * cvmx_gmx0_rx2_int_reg [label="GMXX_RXX_INT_REG(2,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"]; 126215976Sjmallett * cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_rx2_int_reg [label="gmx0"]; 127215976Sjmallett * cvmx_gmx0_rx3_int_reg [label="GMXX_RXX_INT_REG(3,0)|<carext>carext|<skperr>skperr|<ovrerr>ovrerr|<loc_fault>loc_fault|<rem_fault>rem_fault|<bad_seq>bad_seq|<bad_term>bad_term|<unsop>unsop|<uneop>uneop|<undat>undat|<hg2fld>hg2fld|<hg2cc>hg2cc"]; 128215976Sjmallett * cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_rx3_int_reg [label="gmx0"]; 129215976Sjmallett * cvmx_gmx0_tx_int_reg [label="GMXX_TX_INT_REG(0)|<pko_nxa>pko_nxa|<undflw>undflw|<ptp_lost>ptp_lost"]; 130215976Sjmallett * cvmx_ciu_block_int:gmx0:e -> cvmx_gmx0_tx_int_reg [label="gmx0"]; 131215976Sjmallett * cvmx_iob_int_sum [label="IOB_INT_SUM|<np_sop>np_sop|<np_eop>np_eop|<p_sop>p_sop|<p_eop>p_eop|<np_dat>np_dat|<p_dat>p_dat"]; 132215976Sjmallett * cvmx_ciu_block_int:iob:e -> cvmx_iob_int_sum [label="iob"]; 133215976Sjmallett * cvmx_agl_gmx_bad_reg [label="AGL_GMX_BAD_REG|<ovrflw>ovrflw|<txpop>txpop|<txpsh>txpsh|<ovrflw1>ovrflw1|<txpop1>txpop1|<txpsh1>txpsh1|<out_ovr>out_ovr|<loststat>loststat"]; 134215976Sjmallett * cvmx_ciu_block_int:agl:e -> cvmx_agl_gmx_bad_reg [label="agl"]; 135215976Sjmallett * cvmx_agl_gmx_rx0_int_reg [label="AGL_GMX_RXX_INT_REG(0)|<skperr>skperr|<ovrerr>ovrerr"]; 136215976Sjmallett * cvmx_ciu_block_int:agl:e -> cvmx_agl_gmx_rx0_int_reg [label="agl"]; 137215976Sjmallett * cvmx_agl_gmx_rx1_int_reg [label="AGL_GMX_RXX_INT_REG(1)|<skperr>skperr|<ovrerr>ovrerr"]; 138215976Sjmallett * cvmx_ciu_block_int:agl:e -> cvmx_agl_gmx_rx1_int_reg [label="agl"]; 139215976Sjmallett * cvmx_agl_gmx_tx_int_reg [label="AGL_GMX_TX_INT_REG|<pko_nxa>pko_nxa|<undflw>undflw"]; 140215976Sjmallett * cvmx_ciu_block_int:agl:e -> cvmx_agl_gmx_tx_int_reg [label="agl"]; 141215976Sjmallett * cvmx_zip_error [label="ZIP_ERROR|<doorbell>doorbell"]; 142215976Sjmallett * cvmx_ciu_block_int:zip:e -> cvmx_zip_error [label="zip"]; 143215976Sjmallett * cvmx_dfa_error [label="DFA_ERROR|<dblovf>dblovf|<dc0perr>dc0perr"]; 144215976Sjmallett * cvmx_ciu_block_int:dfa:e -> cvmx_dfa_error [label="dfa"]; 145215976Sjmallett * cvmx_srio0_int_reg [label="SRIOX_INT_REG(0)|<bar_err>bar_err|<deny_wr>deny_wr|<sli_err>sli_err|<mce_rx>mce_rx|<log_erb>log_erb|<phy_erb>phy_erb|<omsg_err>omsg_err|<pko_err>pko_err|<rtry_err>rtry_err|<f_error>f_error"]; 146215976Sjmallett * cvmx_ciu_block_int:srio0:e -> cvmx_srio0_int_reg [label="srio0"]; 147215976Sjmallett * cvmx_srio1_int_reg [label="SRIOX_INT_REG(1)|<bar_err>bar_err|<deny_wr>deny_wr|<sli_err>sli_err|<mce_rx>mce_rx|<log_erb>log_erb|<phy_erb>phy_erb|<omsg_err>omsg_err|<pko_err>pko_err|<rtry_err>rtry_err|<f_error>f_error"]; 148215976Sjmallett * cvmx_ciu_block_int:srio1:e -> cvmx_srio1_int_reg [label="srio1"]; 149215976Sjmallett * cvmx_sli_int_sum [label="PEXP_SLI_INT_SUM|<rml_to>rml_to|<reserved_1_1>reserved_1_1|<bar0_to>bar0_to|<iob2big>iob2big|<reserved_6_7>reserved_6_7|<m0_up_b0>m0_up_b0|<m0_up_wi>m0_up_wi|<m0_un_b0>m0_un_b0|<m0_un_wi>m0_un_wi|<m1_up_b0>m1_up_b0|<m1_up_wi>m1_up_wi|<m1_un_b0>m1_un_b0|<m1_un_wi>m1_un_wi|<pidbof>pidbof|<psldbof>psldbof|<pout_err>pout_err|<pin_bp>pin_bp|<pgl_err>pgl_err|<pdi_err>pdi_err|<pop_err>pop_err|<pins_err>pins_err|<sprt0_err>sprt0_err|<sprt1_err>sprt1_err|<ill_pad>ill_pad"]; 150215976Sjmallett * cvmx_ciu_block_int:sli:e -> cvmx_sli_int_sum [label="sli"]; 151215976Sjmallett * cvmx_dpi_int_reg [label="DPI_INT_REG|<nderr>nderr|<nfovr>nfovr|<dmadbo>dmadbo|<req_badadr>req_badadr|<req_badlen>req_badlen|<req_ovrflw>req_ovrflw|<req_undflw>req_undflw|<req_anull>req_anull|<req_inull>req_inull|<req_badfil>req_badfil|<sprt0_rst>sprt0_rst|<sprt1_rst>sprt1_rst"]; 152215976Sjmallett * cvmx_ciu_block_int:dpi:e -> cvmx_dpi_int_reg [label="dpi"]; 153215976Sjmallett * cvmx_dpi_pkt_err_rsp [label="DPI_PKT_ERR_RSP|<pkterr>pkterr"]; 154215976Sjmallett * cvmx_ciu_block_int:dpi:e -> cvmx_dpi_pkt_err_rsp [label="dpi"]; 155215976Sjmallett * cvmx_dpi_req_err_rsp [label="DPI_REQ_ERR_RSP|<qerr>qerr"]; 156215976Sjmallett * cvmx_ciu_block_int:dpi:e -> cvmx_dpi_req_err_rsp [label="dpi"]; 157215976Sjmallett * cvmx_dpi_req_err_rst [label="DPI_REQ_ERR_RST|<qerr>qerr"]; 158215976Sjmallett * cvmx_ciu_block_int:dpi:e -> cvmx_dpi_req_err_rst [label="dpi"]; 159215976Sjmallett * cvmx_pcs0_int0_reg -> cvmx_pcs0_int1_reg [style=invis]; 160215976Sjmallett * cvmx_pcs0_int1_reg -> cvmx_pcs0_int2_reg [style=invis]; 161215976Sjmallett * cvmx_pcs0_int2_reg -> cvmx_pcs0_int3_reg [style=invis]; 162215976Sjmallett * cvmx_pcs0_int3_reg -> cvmx_pcsx0_int_reg [style=invis]; 163215976Sjmallett * cvmx_mio_boot_err -> cvmx_mio_rst_int [style=invis]; 164215976Sjmallett * cvmx_gmx0_bad_reg -> cvmx_gmx0_rx0_int_reg [style=invis]; 165215976Sjmallett * cvmx_gmx0_rx0_int_reg -> cvmx_gmx0_rx1_int_reg [style=invis]; 166215976Sjmallett * cvmx_gmx0_rx1_int_reg -> cvmx_gmx0_rx2_int_reg [style=invis]; 167215976Sjmallett * cvmx_gmx0_rx2_int_reg -> cvmx_gmx0_rx3_int_reg [style=invis]; 168215976Sjmallett * cvmx_gmx0_rx3_int_reg -> cvmx_gmx0_tx_int_reg [style=invis]; 169215976Sjmallett * cvmx_agl_gmx_bad_reg -> cvmx_agl_gmx_rx0_int_reg [style=invis]; 170215976Sjmallett * cvmx_agl_gmx_rx0_int_reg -> cvmx_agl_gmx_rx1_int_reg [style=invis]; 171215976Sjmallett * cvmx_agl_gmx_rx1_int_reg -> cvmx_agl_gmx_tx_int_reg [style=invis]; 172215976Sjmallett * cvmx_dpi_int_reg -> cvmx_dpi_pkt_err_rsp [style=invis]; 173215976Sjmallett * cvmx_dpi_pkt_err_rsp -> cvmx_dpi_req_err_rsp [style=invis]; 174215976Sjmallett * cvmx_dpi_req_err_rsp -> cvmx_dpi_req_err_rst [style=invis]; 175215976Sjmallett * cvmx_root:root:e -> cvmx_ciu_block_int [label="root"]; 176215976Sjmallett * } 177215976Sjmallett * @enddot 178215976Sjmallett */ 179215976Sjmallett#ifdef CVMX_BUILD_FOR_LINUX_KERNEL 180215976Sjmallett#include <asm/octeon/cvmx.h> 181215976Sjmallett#include <asm/octeon/cvmx-error.h> 182215976Sjmallett#include <asm/octeon/cvmx-error-custom.h> 183215976Sjmallett#include <asm/octeon/cvmx-csr-typedefs.h> 184215976Sjmallett#else 185215976Sjmallett#include "cvmx.h" 186215976Sjmallett#include "cvmx-error.h" 187215976Sjmallett#include "cvmx-error-custom.h" 188215976Sjmallett#endif 189215976Sjmallett 190215990Sjmallettint cvmx_error_initialize_cn63xxp1(void); 191215990Sjmallett 192215976Sjmallettint cvmx_error_initialize_cn63xxp1(void) 193215976Sjmallett{ 194215976Sjmallett cvmx_error_info_t info; 195215976Sjmallett int fail = 0; 196215976Sjmallett 197215976Sjmallett /* CVMX_CIU_INTX_SUM0(0) */ 198215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 199215976Sjmallett info.status_addr = CVMX_CIU_INTX_SUM0(0); 200215976Sjmallett info.status_mask = 0; 201215976Sjmallett info.enable_addr = 0; 202215976Sjmallett info.enable_mask = 0; 203215976Sjmallett info.flags = 0; 204215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 205215976Sjmallett info.group_index = 0; 206215976Sjmallett info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE; 207215976Sjmallett info.parent.status_addr = 0; 208215976Sjmallett info.parent.status_mask = 0; 209215976Sjmallett info.func = __cvmx_error_decode; 210215976Sjmallett info.user_info = 0; 211215976Sjmallett fail |= cvmx_error_add(&info); 212215976Sjmallett 213215976Sjmallett /* CVMX_MIXX_ISR(0) */ 214215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 215215976Sjmallett info.status_addr = CVMX_MIXX_ISR(0); 216215976Sjmallett info.status_mask = 1ull<<0 /* odblovf */; 217215976Sjmallett info.enable_addr = CVMX_MIXX_INTENA(0); 218215976Sjmallett info.enable_mask = 1ull<<0 /* ovfena */; 219215976Sjmallett info.flags = 0; 220215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 221215976Sjmallett info.group_index = 0; 222215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 223215976Sjmallett info.parent.status_addr = CVMX_CIU_INTX_SUM0(0); 224215976Sjmallett info.parent.status_mask = 1ull<<62 /* mii */; 225215976Sjmallett info.func = __cvmx_error_display; 226215976Sjmallett info.user_info = (long) 227215976Sjmallett "ERROR MIXX_ISR(0)[ODBLOVF]: Outbound DoorBell(ODBELL) Overflow Detected\n" 228215976Sjmallett " If SW attempts to write to the MIX_ORING2[ODBELL]\n" 229215976Sjmallett " with a value greater than the remaining #of\n" 230215976Sjmallett " O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then\n" 231215976Sjmallett " the following occurs:\n" 232215976Sjmallett " 1) The MIX_ORING2[ODBELL] write is IGNORED\n" 233215976Sjmallett " 2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n" 234215976Sjmallett " bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n" 235215976Sjmallett " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n" 236215976Sjmallett " and the local interrupt mask bit(OVFENA) is set, than an\n" 237215976Sjmallett " interrupt is reported for this event.\n" 238215976Sjmallett " SW should keep track of the #I-Ring Entries in use\n" 239215976Sjmallett " (ie: cumulative # of ODBELL writes), and ensure that\n" 240215976Sjmallett " future ODBELL writes don't exceed the size of the\n" 241215976Sjmallett " O-Ring Buffer (MIX_ORING2[OSIZE]).\n" 242215976Sjmallett " SW must reclaim O-Ring Entries by writing to the\n" 243215976Sjmallett " MIX_ORCNT[ORCNT]. .\n" 244215976Sjmallett " NOTE: There is no recovery from an ODBLOVF Interrupt.\n" 245215976Sjmallett " If it occurs, it's an indication that SW has\n" 246215976Sjmallett " overwritten the O-Ring buffer, and the only recourse\n" 247215976Sjmallett " is a HW reset.\n"; 248215976Sjmallett fail |= cvmx_error_add(&info); 249215976Sjmallett 250215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 251215976Sjmallett info.status_addr = CVMX_MIXX_ISR(0); 252215976Sjmallett info.status_mask = 1ull<<1 /* idblovf */; 253215976Sjmallett info.enable_addr = CVMX_MIXX_INTENA(0); 254215976Sjmallett info.enable_mask = 1ull<<1 /* ivfena */; 255215976Sjmallett info.flags = 0; 256215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 257215976Sjmallett info.group_index = 0; 258215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 259215976Sjmallett info.parent.status_addr = CVMX_CIU_INTX_SUM0(0); 260215976Sjmallett info.parent.status_mask = 1ull<<62 /* mii */; 261215976Sjmallett info.func = __cvmx_error_display; 262215976Sjmallett info.user_info = (long) 263215976Sjmallett "ERROR MIXX_ISR(0)[IDBLOVF]: Inbound DoorBell(IDBELL) Overflow Detected\n" 264215976Sjmallett " If SW attempts to write to the MIX_IRING2[IDBELL]\n" 265215976Sjmallett " with a value greater than the remaining #of\n" 266215976Sjmallett " I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then\n" 267215976Sjmallett " the following occurs:\n" 268215976Sjmallett " 1) The MIX_IRING2[IDBELL] write is IGNORED\n" 269215976Sjmallett " 2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n" 270215976Sjmallett " bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n" 271215976Sjmallett " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n" 272215976Sjmallett " and the local interrupt mask bit(IVFENA) is set, than an\n" 273215976Sjmallett " interrupt is reported for this event.\n" 274215976Sjmallett " SW should keep track of the #I-Ring Entries in use\n" 275215976Sjmallett " (ie: cumulative # of IDBELL writes), and ensure that\n" 276215976Sjmallett " future IDBELL writes don't exceed the size of the\n" 277215976Sjmallett " I-Ring Buffer (MIX_IRING2[ISIZE]).\n" 278215976Sjmallett " SW must reclaim I-Ring Entries by keeping track of the\n" 279215976Sjmallett " #IRing-Entries, and writing to the MIX_IRCNT[IRCNT].\n" 280215976Sjmallett " NOTE: The MIX_IRCNT[IRCNT] register represents the\n" 281215976Sjmallett " total #packets(not IRing Entries) and SW must further\n" 282215976Sjmallett " keep track of the # of I-Ring Entries associated with\n" 283215976Sjmallett " each packet as they are processed.\n" 284215976Sjmallett " NOTE: There is no recovery from an IDBLOVF Interrupt.\n" 285215976Sjmallett " If it occurs, it's an indication that SW has\n" 286215976Sjmallett " overwritten the I-Ring buffer, and the only recourse\n" 287215976Sjmallett " is a HW reset.\n"; 288215976Sjmallett fail |= cvmx_error_add(&info); 289215976Sjmallett 290215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 291215976Sjmallett info.status_addr = CVMX_MIXX_ISR(0); 292215976Sjmallett info.status_mask = 1ull<<4 /* data_drp */; 293215976Sjmallett info.enable_addr = CVMX_MIXX_INTENA(0); 294215976Sjmallett info.enable_mask = 1ull<<4 /* data_drpena */; 295215976Sjmallett info.flags = 0; 296215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 297215976Sjmallett info.group_index = 0; 298215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 299215976Sjmallett info.parent.status_addr = CVMX_CIU_INTX_SUM0(0); 300215976Sjmallett info.parent.status_mask = 1ull<<62 /* mii */; 301215976Sjmallett info.func = __cvmx_error_display; 302215976Sjmallett info.user_info = (long) 303215976Sjmallett "ERROR MIXX_ISR(0)[DATA_DRP]: Data was dropped due to RX FIFO full\n" 304215976Sjmallett " If this does occur, the DATA_DRP is set and the\n" 305215976Sjmallett " CIU_INTx_SUM0,4[MII] bits are set.\n" 306215976Sjmallett " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n" 307215976Sjmallett " and the local interrupt mask bit(DATA_DRPENA) is set, than an\n" 308215976Sjmallett " interrupt is reported for this event.\n"; 309215976Sjmallett fail |= cvmx_error_add(&info); 310215976Sjmallett 311215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 312215976Sjmallett info.status_addr = CVMX_MIXX_ISR(0); 313215976Sjmallett info.status_mask = 1ull<<5 /* irun */; 314215976Sjmallett info.enable_addr = CVMX_MIXX_INTENA(0); 315215976Sjmallett info.enable_mask = 1ull<<5 /* irunena */; 316215976Sjmallett info.flags = 0; 317215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 318215976Sjmallett info.group_index = 0; 319215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 320215976Sjmallett info.parent.status_addr = CVMX_CIU_INTX_SUM0(0); 321215976Sjmallett info.parent.status_mask = 1ull<<62 /* mii */; 322215976Sjmallett info.func = __cvmx_error_display; 323215976Sjmallett info.user_info = (long) 324215976Sjmallett "ERROR MIXX_ISR(0)[IRUN]: IRCNT UnderFlow Detected\n" 325215976Sjmallett " If SW writes a larger value than what is currently\n" 326215976Sjmallett " in the MIX_IRCNT[IRCNT], then HW will report the\n" 327215976Sjmallett " underflow condition.\n" 328215976Sjmallett " NOTE: The MIX_IRCNT[IRCNT] will clamp to to zero.\n" 329215976Sjmallett " NOTE: If an IRUN underflow condition is detected,\n" 330215976Sjmallett " the integrity of the MIX/AGL HW state has\n" 331215976Sjmallett " been compromised. To recover, SW must issue a\n" 332215976Sjmallett " software reset sequence (see: MIX_CTL[RESET]\n"; 333215976Sjmallett fail |= cvmx_error_add(&info); 334215976Sjmallett 335215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 336215976Sjmallett info.status_addr = CVMX_MIXX_ISR(0); 337215976Sjmallett info.status_mask = 1ull<<6 /* orun */; 338215976Sjmallett info.enable_addr = CVMX_MIXX_INTENA(0); 339215976Sjmallett info.enable_mask = 1ull<<6 /* orunena */; 340215976Sjmallett info.flags = 0; 341215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 342215976Sjmallett info.group_index = 0; 343215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 344215976Sjmallett info.parent.status_addr = CVMX_CIU_INTX_SUM0(0); 345215976Sjmallett info.parent.status_mask = 1ull<<62 /* mii */; 346215976Sjmallett info.func = __cvmx_error_display; 347215976Sjmallett info.user_info = (long) 348215976Sjmallett "ERROR MIXX_ISR(0)[ORUN]: ORCNT UnderFlow Detected\n" 349215976Sjmallett " If SW writes a larger value than what is currently\n" 350215976Sjmallett " in the MIX_ORCNT[ORCNT], then HW will report the\n" 351215976Sjmallett " underflow condition.\n" 352215976Sjmallett " NOTE: The MIX_ORCNT[IOCNT] will clamp to to zero.\n" 353215976Sjmallett " NOTE: If an ORUN underflow condition is detected,\n" 354215976Sjmallett " the integrity of the MIX/AGL HW state has\n" 355215976Sjmallett " been compromised. To recover, SW must issue a\n" 356215976Sjmallett " software reset sequence (see: MIX_CTL[RESET]\n"; 357215976Sjmallett fail |= cvmx_error_add(&info); 358215976Sjmallett 359215976Sjmallett /* CVMX_CIU_INT_SUM1 */ 360215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 361215976Sjmallett info.status_addr = CVMX_CIU_INT_SUM1; 362215976Sjmallett info.status_mask = 0; 363215976Sjmallett info.enable_addr = 0; 364215976Sjmallett info.enable_mask = 0; 365215976Sjmallett info.flags = 0; 366215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 367215976Sjmallett info.group_index = 0; 368215976Sjmallett info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE; 369215976Sjmallett info.parent.status_addr = 0; 370215976Sjmallett info.parent.status_mask = 0; 371215976Sjmallett info.func = __cvmx_error_decode; 372215976Sjmallett info.user_info = 0; 373215976Sjmallett fail |= cvmx_error_add(&info); 374215976Sjmallett 375215976Sjmallett /* CVMX_MIXX_ISR(1) */ 376215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 377215976Sjmallett info.status_addr = CVMX_MIXX_ISR(1); 378215976Sjmallett info.status_mask = 1ull<<0 /* odblovf */; 379215976Sjmallett info.enable_addr = CVMX_MIXX_INTENA(1); 380215976Sjmallett info.enable_mask = 1ull<<0 /* ovfena */; 381215976Sjmallett info.flags = 0; 382215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 383215976Sjmallett info.group_index = 1; 384215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 385215976Sjmallett info.parent.status_addr = CVMX_CIU_INT_SUM1; 386215976Sjmallett info.parent.status_mask = 1ull<<18 /* mii1 */; 387215976Sjmallett info.func = __cvmx_error_display; 388215976Sjmallett info.user_info = (long) 389215976Sjmallett "ERROR MIXX_ISR(1)[ODBLOVF]: Outbound DoorBell(ODBELL) Overflow Detected\n" 390215976Sjmallett " If SW attempts to write to the MIX_ORING2[ODBELL]\n" 391215976Sjmallett " with a value greater than the remaining #of\n" 392215976Sjmallett " O-Ring Buffer Entries (MIX_REMCNT[OREMCNT]), then\n" 393215976Sjmallett " the following occurs:\n" 394215976Sjmallett " 1) The MIX_ORING2[ODBELL] write is IGNORED\n" 395215976Sjmallett " 2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n" 396215976Sjmallett " bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n" 397215976Sjmallett " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n" 398215976Sjmallett " and the local interrupt mask bit(OVFENA) is set, than an\n" 399215976Sjmallett " interrupt is reported for this event.\n" 400215976Sjmallett " SW should keep track of the #I-Ring Entries in use\n" 401215976Sjmallett " (ie: cumulative # of ODBELL writes), and ensure that\n" 402215976Sjmallett " future ODBELL writes don't exceed the size of the\n" 403215976Sjmallett " O-Ring Buffer (MIX_ORING2[OSIZE]).\n" 404215976Sjmallett " SW must reclaim O-Ring Entries by writing to the\n" 405215976Sjmallett " MIX_ORCNT[ORCNT]. .\n" 406215976Sjmallett " NOTE: There is no recovery from an ODBLOVF Interrupt.\n" 407215976Sjmallett " If it occurs, it's an indication that SW has\n" 408215976Sjmallett " overwritten the O-Ring buffer, and the only recourse\n" 409215976Sjmallett " is a HW reset.\n"; 410215976Sjmallett fail |= cvmx_error_add(&info); 411215976Sjmallett 412215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 413215976Sjmallett info.status_addr = CVMX_MIXX_ISR(1); 414215976Sjmallett info.status_mask = 1ull<<1 /* idblovf */; 415215976Sjmallett info.enable_addr = CVMX_MIXX_INTENA(1); 416215976Sjmallett info.enable_mask = 1ull<<1 /* ivfena */; 417215976Sjmallett info.flags = 0; 418215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 419215976Sjmallett info.group_index = 1; 420215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 421215976Sjmallett info.parent.status_addr = CVMX_CIU_INT_SUM1; 422215976Sjmallett info.parent.status_mask = 1ull<<18 /* mii1 */; 423215976Sjmallett info.func = __cvmx_error_display; 424215976Sjmallett info.user_info = (long) 425215976Sjmallett "ERROR MIXX_ISR(1)[IDBLOVF]: Inbound DoorBell(IDBELL) Overflow Detected\n" 426215976Sjmallett " If SW attempts to write to the MIX_IRING2[IDBELL]\n" 427215976Sjmallett " with a value greater than the remaining #of\n" 428215976Sjmallett " I-Ring Buffer Entries (MIX_REMCNT[IREMCNT]), then\n" 429215976Sjmallett " the following occurs:\n" 430215976Sjmallett " 1) The MIX_IRING2[IDBELL] write is IGNORED\n" 431215976Sjmallett " 2) The ODBLOVF is set and the CIU_INTx_SUM0,4[MII]\n" 432215976Sjmallett " bits are set if ((MIX_ISR & MIX_INTENA) != 0)).\n" 433215976Sjmallett " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n" 434215976Sjmallett " and the local interrupt mask bit(IVFENA) is set, than an\n" 435215976Sjmallett " interrupt is reported for this event.\n" 436215976Sjmallett " SW should keep track of the #I-Ring Entries in use\n" 437215976Sjmallett " (ie: cumulative # of IDBELL writes), and ensure that\n" 438215976Sjmallett " future IDBELL writes don't exceed the size of the\n" 439215976Sjmallett " I-Ring Buffer (MIX_IRING2[ISIZE]).\n" 440215976Sjmallett " SW must reclaim I-Ring Entries by keeping track of the\n" 441215976Sjmallett " #IRing-Entries, and writing to the MIX_IRCNT[IRCNT].\n" 442215976Sjmallett " NOTE: The MIX_IRCNT[IRCNT] register represents the\n" 443215976Sjmallett " total #packets(not IRing Entries) and SW must further\n" 444215976Sjmallett " keep track of the # of I-Ring Entries associated with\n" 445215976Sjmallett " each packet as they are processed.\n" 446215976Sjmallett " NOTE: There is no recovery from an IDBLOVF Interrupt.\n" 447215976Sjmallett " If it occurs, it's an indication that SW has\n" 448215976Sjmallett " overwritten the I-Ring buffer, and the only recourse\n" 449215976Sjmallett " is a HW reset.\n"; 450215976Sjmallett fail |= cvmx_error_add(&info); 451215976Sjmallett 452215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 453215976Sjmallett info.status_addr = CVMX_MIXX_ISR(1); 454215976Sjmallett info.status_mask = 1ull<<4 /* data_drp */; 455215976Sjmallett info.enable_addr = CVMX_MIXX_INTENA(1); 456215976Sjmallett info.enable_mask = 1ull<<4 /* data_drpena */; 457215976Sjmallett info.flags = 0; 458215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 459215976Sjmallett info.group_index = 1; 460215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 461215976Sjmallett info.parent.status_addr = CVMX_CIU_INT_SUM1; 462215976Sjmallett info.parent.status_mask = 1ull<<18 /* mii1 */; 463215976Sjmallett info.func = __cvmx_error_display; 464215976Sjmallett info.user_info = (long) 465215976Sjmallett "ERROR MIXX_ISR(1)[DATA_DRP]: Data was dropped due to RX FIFO full\n" 466215976Sjmallett " If this does occur, the DATA_DRP is set and the\n" 467215976Sjmallett " CIU_INTx_SUM0,4[MII] bits are set.\n" 468215976Sjmallett " If both the global interrupt mask bits (CIU_INTx_EN*[MII])\n" 469215976Sjmallett " and the local interrupt mask bit(DATA_DRPENA) is set, than an\n" 470215976Sjmallett " interrupt is reported for this event.\n"; 471215976Sjmallett fail |= cvmx_error_add(&info); 472215976Sjmallett 473215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 474215976Sjmallett info.status_addr = CVMX_MIXX_ISR(1); 475215976Sjmallett info.status_mask = 1ull<<5 /* irun */; 476215976Sjmallett info.enable_addr = CVMX_MIXX_INTENA(1); 477215976Sjmallett info.enable_mask = 1ull<<5 /* irunena */; 478215976Sjmallett info.flags = 0; 479215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 480215976Sjmallett info.group_index = 1; 481215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 482215976Sjmallett info.parent.status_addr = CVMX_CIU_INT_SUM1; 483215976Sjmallett info.parent.status_mask = 1ull<<18 /* mii1 */; 484215976Sjmallett info.func = __cvmx_error_display; 485215976Sjmallett info.user_info = (long) 486215976Sjmallett "ERROR MIXX_ISR(1)[IRUN]: IRCNT UnderFlow Detected\n" 487215976Sjmallett " If SW writes a larger value than what is currently\n" 488215976Sjmallett " in the MIX_IRCNT[IRCNT], then HW will report the\n" 489215976Sjmallett " underflow condition.\n" 490215976Sjmallett " NOTE: The MIX_IRCNT[IRCNT] will clamp to to zero.\n" 491215976Sjmallett " NOTE: If an IRUN underflow condition is detected,\n" 492215976Sjmallett " the integrity of the MIX/AGL HW state has\n" 493215976Sjmallett " been compromised. To recover, SW must issue a\n" 494215976Sjmallett " software reset sequence (see: MIX_CTL[RESET]\n"; 495215976Sjmallett fail |= cvmx_error_add(&info); 496215976Sjmallett 497215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 498215976Sjmallett info.status_addr = CVMX_MIXX_ISR(1); 499215976Sjmallett info.status_mask = 1ull<<6 /* orun */; 500215976Sjmallett info.enable_addr = CVMX_MIXX_INTENA(1); 501215976Sjmallett info.enable_mask = 1ull<<6 /* orunena */; 502215976Sjmallett info.flags = 0; 503215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 504215976Sjmallett info.group_index = 1; 505215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 506215976Sjmallett info.parent.status_addr = CVMX_CIU_INT_SUM1; 507215976Sjmallett info.parent.status_mask = 1ull<<18 /* mii1 */; 508215976Sjmallett info.func = __cvmx_error_display; 509215976Sjmallett info.user_info = (long) 510215976Sjmallett "ERROR MIXX_ISR(1)[ORUN]: ORCNT UnderFlow Detected\n" 511215976Sjmallett " If SW writes a larger value than what is currently\n" 512215976Sjmallett " in the MIX_ORCNT[ORCNT], then HW will report the\n" 513215976Sjmallett " underflow condition.\n" 514215976Sjmallett " NOTE: The MIX_ORCNT[IOCNT] will clamp to to zero.\n" 515215976Sjmallett " NOTE: If an ORUN underflow condition is detected,\n" 516215976Sjmallett " the integrity of the MIX/AGL HW state has\n" 517215976Sjmallett " been compromised. To recover, SW must issue a\n" 518215976Sjmallett " software reset sequence (see: MIX_CTL[RESET]\n"; 519215976Sjmallett fail |= cvmx_error_add(&info); 520215976Sjmallett 521215976Sjmallett /* CVMX_NDF_INT */ 522215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 523215976Sjmallett info.status_addr = CVMX_NDF_INT; 524215976Sjmallett info.status_mask = 1ull<<2 /* wdog */; 525215976Sjmallett info.enable_addr = CVMX_NDF_INT_EN; 526215976Sjmallett info.enable_mask = 1ull<<2 /* wdog */; 527215976Sjmallett info.flags = 0; 528215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 529215976Sjmallett info.group_index = 0; 530215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 531215976Sjmallett info.parent.status_addr = CVMX_CIU_INT_SUM1; 532215976Sjmallett info.parent.status_mask = 1ull<<19 /* nand */; 533215976Sjmallett info.func = __cvmx_error_display; 534215976Sjmallett info.user_info = (long) 535215976Sjmallett "ERROR NDF_INT[WDOG]: Watch Dog timer expired during command execution\n"; 536215976Sjmallett fail |= cvmx_error_add(&info); 537215976Sjmallett 538215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 539215976Sjmallett info.status_addr = CVMX_NDF_INT; 540215976Sjmallett info.status_mask = 1ull<<3 /* sm_bad */; 541215976Sjmallett info.enable_addr = CVMX_NDF_INT_EN; 542215976Sjmallett info.enable_mask = 1ull<<3 /* sm_bad */; 543215976Sjmallett info.flags = 0; 544215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 545215976Sjmallett info.group_index = 0; 546215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 547215976Sjmallett info.parent.status_addr = CVMX_CIU_INT_SUM1; 548215976Sjmallett info.parent.status_mask = 1ull<<19 /* nand */; 549215976Sjmallett info.func = __cvmx_error_display; 550215976Sjmallett info.user_info = (long) 551215976Sjmallett "ERROR NDF_INT[SM_BAD]: One of the state machines in a bad state\n"; 552215976Sjmallett fail |= cvmx_error_add(&info); 553215976Sjmallett 554215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 555215976Sjmallett info.status_addr = CVMX_NDF_INT; 556215976Sjmallett info.status_mask = 1ull<<4 /* ecc_1bit */; 557215976Sjmallett info.enable_addr = CVMX_NDF_INT_EN; 558215976Sjmallett info.enable_mask = 1ull<<4 /* ecc_1bit */; 559215976Sjmallett info.flags = 0; 560215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 561215976Sjmallett info.group_index = 0; 562215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 563215976Sjmallett info.parent.status_addr = CVMX_CIU_INT_SUM1; 564215976Sjmallett info.parent.status_mask = 1ull<<19 /* nand */; 565215976Sjmallett info.func = __cvmx_error_display; 566215976Sjmallett info.user_info = (long) 567215976Sjmallett "ERROR NDF_INT[ECC_1BIT]: Single bit ECC error detected and fixed during boot\n"; 568215976Sjmallett fail |= cvmx_error_add(&info); 569215976Sjmallett 570215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 571215976Sjmallett info.status_addr = CVMX_NDF_INT; 572215976Sjmallett info.status_mask = 1ull<<5 /* ecc_mult */; 573215976Sjmallett info.enable_addr = CVMX_NDF_INT_EN; 574215976Sjmallett info.enable_mask = 1ull<<5 /* ecc_mult */; 575215976Sjmallett info.flags = 0; 576215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 577215976Sjmallett info.group_index = 0; 578215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 579215976Sjmallett info.parent.status_addr = CVMX_CIU_INT_SUM1; 580215976Sjmallett info.parent.status_mask = 1ull<<19 /* nand */; 581215976Sjmallett info.func = __cvmx_error_display; 582215976Sjmallett info.user_info = (long) 583215976Sjmallett "ERROR NDF_INT[ECC_MULT]: Multi bit ECC error detected during boot\n"; 584215976Sjmallett fail |= cvmx_error_add(&info); 585215976Sjmallett 586215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 587215976Sjmallett info.status_addr = CVMX_NDF_INT; 588215976Sjmallett info.status_mask = 1ull<<6 /* ovrf */; 589215976Sjmallett info.enable_addr = CVMX_NDF_INT_EN; 590215976Sjmallett info.enable_mask = 1ull<<6 /* ovrf */; 591215976Sjmallett info.flags = 0; 592215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 593215976Sjmallett info.group_index = 0; 594215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 595215976Sjmallett info.parent.status_addr = CVMX_CIU_INT_SUM1; 596215976Sjmallett info.parent.status_mask = 1ull<<19 /* nand */; 597215976Sjmallett info.func = __cvmx_error_display; 598215976Sjmallett info.user_info = (long) 599215976Sjmallett "ERROR NDF_INT[OVRF]: NDF_CMD write when fifo is full. Generally a\n" 600215976Sjmallett " fatal error.\n"; 601215976Sjmallett fail |= cvmx_error_add(&info); 602215976Sjmallett 603215976Sjmallett /* CVMX_CIU_BLOCK_INT */ 604215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 605215976Sjmallett info.status_addr = CVMX_CIU_BLOCK_INT; 606215976Sjmallett info.status_mask = 0; 607215976Sjmallett info.enable_addr = 0; 608215976Sjmallett info.enable_mask = 0; 609215976Sjmallett info.flags = 0; 610215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 611215976Sjmallett info.group_index = 0; 612215976Sjmallett info.parent.reg_type = __CVMX_ERROR_REGISTER_NONE; 613215976Sjmallett info.parent.status_addr = 0; 614215976Sjmallett info.parent.status_mask = 0; 615215976Sjmallett info.func = __cvmx_error_decode; 616215976Sjmallett info.user_info = 0; 617215976Sjmallett fail |= cvmx_error_add(&info); 618215976Sjmallett 619215976Sjmallett /* CVMX_L2C_INT_REG */ 620215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 621215976Sjmallett info.status_addr = CVMX_L2C_INT_REG; 622215976Sjmallett info.status_mask = 1ull<<0 /* holerd */; 623215976Sjmallett info.enable_addr = CVMX_L2C_INT_ENA; 624215976Sjmallett info.enable_mask = 1ull<<0 /* holerd */; 625215976Sjmallett info.flags = 0; 626215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 627215976Sjmallett info.group_index = 0; 628215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 629215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 630215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 631215976Sjmallett info.func = __cvmx_error_display; 632215976Sjmallett info.user_info = (long) 633215976Sjmallett "ERROR L2C_INT_REG[HOLERD]: Read reference to 256MB hole occurred\n"; 634215976Sjmallett fail |= cvmx_error_add(&info); 635215976Sjmallett 636215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 637215976Sjmallett info.status_addr = CVMX_L2C_INT_REG; 638215976Sjmallett info.status_mask = 1ull<<1 /* holewr */; 639215976Sjmallett info.enable_addr = CVMX_L2C_INT_ENA; 640215976Sjmallett info.enable_mask = 1ull<<1 /* holewr */; 641215976Sjmallett info.flags = 0; 642215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 643215976Sjmallett info.group_index = 0; 644215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 645215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 646215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 647215976Sjmallett info.func = __cvmx_error_display; 648215976Sjmallett info.user_info = (long) 649215976Sjmallett "ERROR L2C_INT_REG[HOLEWR]: Write reference to 256MB hole occurred\n"; 650215976Sjmallett fail |= cvmx_error_add(&info); 651215976Sjmallett 652215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 653215976Sjmallett info.status_addr = CVMX_L2C_INT_REG; 654215976Sjmallett info.status_mask = 1ull<<2 /* vrtwr */; 655215976Sjmallett info.enable_addr = CVMX_L2C_INT_ENA; 656215976Sjmallett info.enable_mask = 1ull<<2 /* vrtwr */; 657215976Sjmallett info.flags = 0; 658215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 659215976Sjmallett info.group_index = 0; 660215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 661215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 662215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 663215976Sjmallett info.func = __cvmx_error_display; 664215976Sjmallett info.user_info = (long) 665215976Sjmallett "ERROR L2C_INT_REG[VRTWR]: Virtualization ID prevented a write\n" 666215976Sjmallett " Set when L2C_VRT_MEM blocked a store.\n"; 667215976Sjmallett fail |= cvmx_error_add(&info); 668215976Sjmallett 669215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 670215976Sjmallett info.status_addr = CVMX_L2C_INT_REG; 671215976Sjmallett info.status_mask = 1ull<<3 /* vrtidrng */; 672215976Sjmallett info.enable_addr = CVMX_L2C_INT_ENA; 673215976Sjmallett info.enable_mask = 1ull<<3 /* vrtidrng */; 674215976Sjmallett info.flags = 0; 675215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 676215976Sjmallett info.group_index = 0; 677215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 678215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 679215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 680215976Sjmallett info.func = __cvmx_error_display; 681215976Sjmallett info.user_info = (long) 682215976Sjmallett "ERROR L2C_INT_REG[VRTIDRNG]: Virtualization ID out of range\n" 683215976Sjmallett " Set when a L2C_VRT_CTL[NUMID] violation blocked a\n" 684215976Sjmallett " store.\n"; 685215976Sjmallett fail |= cvmx_error_add(&info); 686215976Sjmallett 687215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 688215976Sjmallett info.status_addr = CVMX_L2C_INT_REG; 689215976Sjmallett info.status_mask = 1ull<<4 /* vrtadrng */; 690215976Sjmallett info.enable_addr = CVMX_L2C_INT_ENA; 691215976Sjmallett info.enable_mask = 1ull<<4 /* vrtadrng */; 692215976Sjmallett info.flags = 0; 693215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 694215976Sjmallett info.group_index = 0; 695215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 696215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 697215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 698215976Sjmallett info.func = __cvmx_error_display; 699215976Sjmallett info.user_info = (long) 700215976Sjmallett "ERROR L2C_INT_REG[VRTADRNG]: Address outside of virtualization range\n" 701215976Sjmallett " Set when a L2C_VRT_CTL[MEMSZ] violation blocked a\n" 702215976Sjmallett " store.\n" 703215976Sjmallett " L2C_VRT_CTL[OOBERR] must be set for L2C to set this.\n"; 704215976Sjmallett fail |= cvmx_error_add(&info); 705215976Sjmallett 706215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 707215976Sjmallett info.status_addr = CVMX_L2C_INT_REG; 708215976Sjmallett info.status_mask = 1ull<<5 /* vrtpe */; 709215976Sjmallett info.enable_addr = CVMX_L2C_INT_ENA; 710215976Sjmallett info.enable_mask = 1ull<<5 /* vrtpe */; 711215976Sjmallett info.flags = 0; 712215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 713215976Sjmallett info.group_index = 0; 714215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 715215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 716215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 717215976Sjmallett info.func = __cvmx_error_display; 718215976Sjmallett info.user_info = (long) 719215976Sjmallett "ERROR L2C_INT_REG[VRTPE]: L2C_VRT_MEM read found a parity error\n" 720215976Sjmallett " Whenever an L2C_VRT_MEM read finds a parity error,\n" 721215976Sjmallett " that L2C_VRT_MEM cannot cause stores to be blocked.\n" 722215976Sjmallett " Software should correct the error.\n"; 723215976Sjmallett fail |= cvmx_error_add(&info); 724215976Sjmallett 725215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 726215976Sjmallett info.status_addr = CVMX_L2C_INT_REG; 727215976Sjmallett info.status_mask = 0; 728215976Sjmallett info.enable_addr = 0; 729215976Sjmallett info.enable_mask = 0; 730215976Sjmallett info.flags = 0; 731215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 732215976Sjmallett info.group_index = 0; 733215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 734215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 735215976Sjmallett info.parent.status_mask = 1ull<<16 /* l2c */; 736215976Sjmallett info.func = __cvmx_error_decode; 737215976Sjmallett info.user_info = 0; 738215976Sjmallett fail |= cvmx_error_add(&info); 739215976Sjmallett 740215976Sjmallett /* CVMX_L2C_ERR_TDTX(0) */ 741215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 742215976Sjmallett info.status_addr = CVMX_L2C_ERR_TDTX(0); 743215976Sjmallett info.status_mask = 1ull<<60 /* vsbe */; 744215976Sjmallett info.enable_addr = 0; 745215976Sjmallett info.enable_mask = 0; 746215976Sjmallett info.flags = 0; 747215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 748215976Sjmallett info.group_index = 0; 749215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 750215976Sjmallett info.parent.status_addr = CVMX_L2C_INT_REG; 751215976Sjmallett info.parent.status_mask = 1ull<<16 /* tad0 */; 752215976Sjmallett info.func = __cvmx_error_display; 753215976Sjmallett info.user_info = (long) 754215976Sjmallett "ERROR L2C_ERR_TDTX(0)[VSBE]: VBF Single-Bit error has occurred\n"; 755215976Sjmallett fail |= cvmx_error_add(&info); 756215976Sjmallett 757215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 758215976Sjmallett info.status_addr = CVMX_L2C_ERR_TDTX(0); 759215976Sjmallett info.status_mask = 1ull<<61 /* vdbe */; 760215976Sjmallett info.enable_addr = 0; 761215976Sjmallett info.enable_mask = 0; 762215976Sjmallett info.flags = 0; 763215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 764215976Sjmallett info.group_index = 0; 765215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 766215976Sjmallett info.parent.status_addr = CVMX_L2C_INT_REG; 767215976Sjmallett info.parent.status_mask = 1ull<<16 /* tad0 */; 768215976Sjmallett info.func = __cvmx_error_display; 769215976Sjmallett info.user_info = (long) 770215976Sjmallett "ERROR L2C_ERR_TDTX(0)[VDBE]: VBF Double-Bit error has occurred\n"; 771215976Sjmallett fail |= cvmx_error_add(&info); 772215976Sjmallett 773215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 774215976Sjmallett info.status_addr = CVMX_L2C_ERR_TDTX(0); 775215976Sjmallett info.status_mask = 1ull<<62 /* sbe */; 776215976Sjmallett info.enable_addr = 0; 777215976Sjmallett info.enable_mask = 0; 778215976Sjmallett info.flags = 0; 779215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 780215976Sjmallett info.group_index = 0; 781215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 782215976Sjmallett info.parent.status_addr = CVMX_L2C_INT_REG; 783215976Sjmallett info.parent.status_mask = 1ull<<16 /* tad0 */; 784215976Sjmallett info.func = __cvmx_error_display; 785215976Sjmallett info.user_info = (long) 786215976Sjmallett "ERROR L2C_ERR_TDTX(0)[SBE]: L2D Single-Bit error has occurred\n"; 787215976Sjmallett fail |= cvmx_error_add(&info); 788215976Sjmallett 789215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 790215976Sjmallett info.status_addr = CVMX_L2C_ERR_TDTX(0); 791215976Sjmallett info.status_mask = 1ull<<63 /* dbe */; 792215976Sjmallett info.enable_addr = 0; 793215976Sjmallett info.enable_mask = 0; 794215976Sjmallett info.flags = 0; 795215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 796215976Sjmallett info.group_index = 0; 797215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 798215976Sjmallett info.parent.status_addr = CVMX_L2C_INT_REG; 799215976Sjmallett info.parent.status_mask = 1ull<<16 /* tad0 */; 800215976Sjmallett info.func = __cvmx_error_display; 801215976Sjmallett info.user_info = (long) 802215976Sjmallett "ERROR L2C_ERR_TDTX(0)[DBE]: L2D Double-Bit error has occurred\n"; 803215976Sjmallett fail |= cvmx_error_add(&info); 804215976Sjmallett 805215976Sjmallett /* CVMX_L2C_ERR_TTGX(0) */ 806215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 807215976Sjmallett info.status_addr = CVMX_L2C_ERR_TTGX(0); 808215976Sjmallett info.status_mask = 1ull<<61 /* noway */; 809215976Sjmallett info.enable_addr = 0; 810215976Sjmallett info.enable_mask = 0; 811215976Sjmallett info.flags = 0; 812215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 813215976Sjmallett info.group_index = 0; 814215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 815215976Sjmallett info.parent.status_addr = CVMX_L2C_INT_REG; 816215976Sjmallett info.parent.status_mask = 1ull<<16 /* tad0 */; 817215976Sjmallett info.func = __cvmx_error_display; 818215976Sjmallett info.user_info = (long) 819215976Sjmallett "ERROR L2C_ERR_TTGX(0)[NOWAY]: No way was available for allocation.\n" 820215976Sjmallett " L2C sets NOWAY during its processing of a\n" 821215976Sjmallett " transaction whenever it needed/wanted to allocate\n" 822215976Sjmallett " a WAY in the L2 cache, but was unable to. NOWAY==1\n" 823215976Sjmallett " is (generally) not an indication that L2C failed to\n" 824215976Sjmallett " complete transactions. Rather, it is a hint of\n" 825215976Sjmallett " possible performance degradation. (For example, L2C\n" 826215976Sjmallett " must read-modify-write DRAM for every transaction\n" 827215976Sjmallett " that updates some, but not all, of the bytes in a\n" 828215976Sjmallett " cache block, misses in the L2 cache, and cannot\n" 829215976Sjmallett " allocate a WAY.) There is one \"failure\" case where\n" 830215976Sjmallett " L2C will set NOWAY: when it cannot leave a block\n" 831215976Sjmallett " locked in the L2 cache as part of a LCKL2\n" 832215976Sjmallett " transaction.\n"; 833215976Sjmallett fail |= cvmx_error_add(&info); 834215976Sjmallett 835215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 836215976Sjmallett info.status_addr = CVMX_L2C_ERR_TTGX(0); 837215976Sjmallett info.status_mask = 1ull<<62 /* sbe */; 838215976Sjmallett info.enable_addr = 0; 839215976Sjmallett info.enable_mask = 0; 840215976Sjmallett info.flags = 0; 841215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 842215976Sjmallett info.group_index = 0; 843215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 844215976Sjmallett info.parent.status_addr = CVMX_L2C_INT_REG; 845215976Sjmallett info.parent.status_mask = 1ull<<16 /* tad0 */; 846215976Sjmallett info.func = __cvmx_error_display; 847215976Sjmallett info.user_info = (long) 848215976Sjmallett "ERROR L2C_ERR_TTGX(0)[SBE]: Single-Bit ECC error\n"; 849215976Sjmallett fail |= cvmx_error_add(&info); 850215976Sjmallett 851215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 852215976Sjmallett info.status_addr = CVMX_L2C_ERR_TTGX(0); 853215976Sjmallett info.status_mask = 1ull<<63 /* dbe */; 854215976Sjmallett info.enable_addr = 0; 855215976Sjmallett info.enable_mask = 0; 856215976Sjmallett info.flags = 0; 857215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 858215976Sjmallett info.group_index = 0; 859215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 860215976Sjmallett info.parent.status_addr = CVMX_L2C_INT_REG; 861215976Sjmallett info.parent.status_mask = 1ull<<16 /* tad0 */; 862215976Sjmallett info.func = __cvmx_error_display; 863215976Sjmallett info.user_info = (long) 864215976Sjmallett "ERROR L2C_ERR_TTGX(0)[DBE]: Double-Bit ECC error\n"; 865215976Sjmallett fail |= cvmx_error_add(&info); 866215976Sjmallett 867215976Sjmallett /* CVMX_IPD_INT_SUM */ 868215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 869215976Sjmallett info.status_addr = CVMX_IPD_INT_SUM; 870215976Sjmallett info.status_mask = 1ull<<0 /* prc_par0 */; 871215976Sjmallett info.enable_addr = CVMX_IPD_INT_ENB; 872215976Sjmallett info.enable_mask = 1ull<<0 /* prc_par0 */; 873215976Sjmallett info.flags = 0; 874215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 875215976Sjmallett info.group_index = 0; 876215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 877215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 878215976Sjmallett info.parent.status_mask = 1ull<<9 /* ipd */; 879215976Sjmallett info.func = __cvmx_error_display; 880215976Sjmallett info.user_info = (long) 881215976Sjmallett "ERROR IPD_INT_SUM[PRC_PAR0]: Set when a parity error is dected for bits\n" 882215976Sjmallett " [31:0] of the PBM memory.\n"; 883215976Sjmallett fail |= cvmx_error_add(&info); 884215976Sjmallett 885215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 886215976Sjmallett info.status_addr = CVMX_IPD_INT_SUM; 887215976Sjmallett info.status_mask = 1ull<<1 /* prc_par1 */; 888215976Sjmallett info.enable_addr = CVMX_IPD_INT_ENB; 889215976Sjmallett info.enable_mask = 1ull<<1 /* prc_par1 */; 890215976Sjmallett info.flags = 0; 891215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 892215976Sjmallett info.group_index = 0; 893215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 894215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 895215976Sjmallett info.parent.status_mask = 1ull<<9 /* ipd */; 896215976Sjmallett info.func = __cvmx_error_display; 897215976Sjmallett info.user_info = (long) 898215976Sjmallett "ERROR IPD_INT_SUM[PRC_PAR1]: Set when a parity error is dected for bits\n" 899215976Sjmallett " [63:32] of the PBM memory.\n"; 900215976Sjmallett fail |= cvmx_error_add(&info); 901215976Sjmallett 902215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 903215976Sjmallett info.status_addr = CVMX_IPD_INT_SUM; 904215976Sjmallett info.status_mask = 1ull<<2 /* prc_par2 */; 905215976Sjmallett info.enable_addr = CVMX_IPD_INT_ENB; 906215976Sjmallett info.enable_mask = 1ull<<2 /* prc_par2 */; 907215976Sjmallett info.flags = 0; 908215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 909215976Sjmallett info.group_index = 0; 910215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 911215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 912215976Sjmallett info.parent.status_mask = 1ull<<9 /* ipd */; 913215976Sjmallett info.func = __cvmx_error_display; 914215976Sjmallett info.user_info = (long) 915215976Sjmallett "ERROR IPD_INT_SUM[PRC_PAR2]: Set when a parity error is dected for bits\n" 916215976Sjmallett " [95:64] of the PBM memory.\n"; 917215976Sjmallett fail |= cvmx_error_add(&info); 918215976Sjmallett 919215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 920215976Sjmallett info.status_addr = CVMX_IPD_INT_SUM; 921215976Sjmallett info.status_mask = 1ull<<3 /* prc_par3 */; 922215976Sjmallett info.enable_addr = CVMX_IPD_INT_ENB; 923215976Sjmallett info.enable_mask = 1ull<<3 /* prc_par3 */; 924215976Sjmallett info.flags = 0; 925215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 926215976Sjmallett info.group_index = 0; 927215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 928215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 929215976Sjmallett info.parent.status_mask = 1ull<<9 /* ipd */; 930215976Sjmallett info.func = __cvmx_error_display; 931215976Sjmallett info.user_info = (long) 932215976Sjmallett "ERROR IPD_INT_SUM[PRC_PAR3]: Set when a parity error is dected for bits\n" 933215976Sjmallett " [127:96] of the PBM memory.\n"; 934215976Sjmallett fail |= cvmx_error_add(&info); 935215976Sjmallett 936215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 937215976Sjmallett info.status_addr = CVMX_IPD_INT_SUM; 938215976Sjmallett info.status_mask = 1ull<<4 /* bp_sub */; 939215976Sjmallett info.enable_addr = CVMX_IPD_INT_ENB; 940215976Sjmallett info.enable_mask = 1ull<<4 /* bp_sub */; 941215976Sjmallett info.flags = 0; 942215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 943215976Sjmallett info.group_index = 0; 944215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 945215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 946215976Sjmallett info.parent.status_mask = 1ull<<9 /* ipd */; 947215976Sjmallett info.func = __cvmx_error_display; 948215976Sjmallett info.user_info = (long) 949215976Sjmallett "ERROR IPD_INT_SUM[BP_SUB]: Set when a backpressure subtract is done with a\n" 950215976Sjmallett " supplied illegal value.\n"; 951215976Sjmallett fail |= cvmx_error_add(&info); 952215976Sjmallett 953215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 954215976Sjmallett info.status_addr = CVMX_IPD_INT_SUM; 955215976Sjmallett info.status_mask = 1ull<<5 /* dc_ovr */; 956215976Sjmallett info.enable_addr = CVMX_IPD_INT_ENB; 957215976Sjmallett info.enable_mask = 1ull<<5 /* dc_ovr */; 958215976Sjmallett info.flags = 0; 959215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 960215976Sjmallett info.group_index = 0; 961215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 962215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 963215976Sjmallett info.parent.status_mask = 1ull<<9 /* ipd */; 964215976Sjmallett info.func = __cvmx_error_display; 965215976Sjmallett info.user_info = (long) 966215976Sjmallett "ERROR IPD_INT_SUM[DC_OVR]: Set when the data credits to the IOB overflow.\n"; 967215976Sjmallett fail |= cvmx_error_add(&info); 968215976Sjmallett 969215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 970215976Sjmallett info.status_addr = CVMX_IPD_INT_SUM; 971215976Sjmallett info.status_mask = 1ull<<6 /* cc_ovr */; 972215976Sjmallett info.enable_addr = CVMX_IPD_INT_ENB; 973215976Sjmallett info.enable_mask = 1ull<<6 /* cc_ovr */; 974215976Sjmallett info.flags = 0; 975215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 976215976Sjmallett info.group_index = 0; 977215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 978215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 979215976Sjmallett info.parent.status_mask = 1ull<<9 /* ipd */; 980215976Sjmallett info.func = __cvmx_error_display; 981215976Sjmallett info.user_info = (long) 982215976Sjmallett "ERROR IPD_INT_SUM[CC_OVR]: Set when the command credits to the IOB overflow.\n"; 983215976Sjmallett fail |= cvmx_error_add(&info); 984215976Sjmallett 985215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 986215976Sjmallett info.status_addr = CVMX_IPD_INT_SUM; 987215976Sjmallett info.status_mask = 1ull<<7 /* c_coll */; 988215976Sjmallett info.enable_addr = CVMX_IPD_INT_ENB; 989215976Sjmallett info.enable_mask = 1ull<<7 /* c_coll */; 990215976Sjmallett info.flags = 0; 991215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 992215976Sjmallett info.group_index = 0; 993215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 994215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 995215976Sjmallett info.parent.status_mask = 1ull<<9 /* ipd */; 996215976Sjmallett info.func = __cvmx_error_display; 997215976Sjmallett info.user_info = (long) 998215976Sjmallett "ERROR IPD_INT_SUM[C_COLL]: Set when the packet/WQE commands to be sent to IOB\n" 999215976Sjmallett " collides.\n"; 1000215976Sjmallett fail |= cvmx_error_add(&info); 1001215976Sjmallett 1002215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1003215976Sjmallett info.status_addr = CVMX_IPD_INT_SUM; 1004215976Sjmallett info.status_mask = 1ull<<8 /* d_coll */; 1005215976Sjmallett info.enable_addr = CVMX_IPD_INT_ENB; 1006215976Sjmallett info.enable_mask = 1ull<<8 /* d_coll */; 1007215976Sjmallett info.flags = 0; 1008215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 1009215976Sjmallett info.group_index = 0; 1010215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1011215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 1012215976Sjmallett info.parent.status_mask = 1ull<<9 /* ipd */; 1013215976Sjmallett info.func = __cvmx_error_display; 1014215976Sjmallett info.user_info = (long) 1015215976Sjmallett "ERROR IPD_INT_SUM[D_COLL]: Set when the packet/WQE data to be sent to IOB\n" 1016215976Sjmallett " collides.\n"; 1017215976Sjmallett fail |= cvmx_error_add(&info); 1018215976Sjmallett 1019215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1020215976Sjmallett info.status_addr = CVMX_IPD_INT_SUM; 1021215976Sjmallett info.status_mask = 1ull<<9 /* bc_ovr */; 1022215976Sjmallett info.enable_addr = CVMX_IPD_INT_ENB; 1023215976Sjmallett info.enable_mask = 1ull<<9 /* bc_ovr */; 1024215976Sjmallett info.flags = 0; 1025215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 1026215976Sjmallett info.group_index = 0; 1027215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1028215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 1029215976Sjmallett info.parent.status_mask = 1ull<<9 /* ipd */; 1030215976Sjmallett info.func = __cvmx_error_display; 1031215976Sjmallett info.user_info = (long) 1032215976Sjmallett "ERROR IPD_INT_SUM[BC_OVR]: Set when the byte-count to send to IOB overflows.\n"; 1033215976Sjmallett fail |= cvmx_error_add(&info); 1034215976Sjmallett 1035215976Sjmallett /* CVMX_POW_ECC_ERR */ 1036215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1037215976Sjmallett info.status_addr = CVMX_POW_ECC_ERR; 1038215976Sjmallett info.status_mask = 1ull<<0 /* sbe */; 1039215976Sjmallett info.enable_addr = CVMX_POW_ECC_ERR; 1040215976Sjmallett info.enable_mask = 1ull<<2 /* sbe_ie */; 1041215976Sjmallett info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT; 1042215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 1043215976Sjmallett info.group_index = 0; 1044215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1045215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 1046215976Sjmallett info.parent.status_mask = 1ull<<12 /* pow */; 1047215976Sjmallett info.func = __cvmx_error_handle_pow_ecc_err_sbe; 1048215976Sjmallett info.user_info = (long) 1049215976Sjmallett "ERROR POW_ECC_ERR[SBE]: Single bit error\n"; 1050215976Sjmallett fail |= cvmx_error_add(&info); 1051215976Sjmallett 1052215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1053215976Sjmallett info.status_addr = CVMX_POW_ECC_ERR; 1054215976Sjmallett info.status_mask = 1ull<<1 /* dbe */; 1055215976Sjmallett info.enable_addr = CVMX_POW_ECC_ERR; 1056215976Sjmallett info.enable_mask = 1ull<<3 /* dbe_ie */; 1057215976Sjmallett info.flags = 0; 1058215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 1059215976Sjmallett info.group_index = 0; 1060215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1061215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 1062215976Sjmallett info.parent.status_mask = 1ull<<12 /* pow */; 1063215976Sjmallett info.func = __cvmx_error_handle_pow_ecc_err_dbe; 1064215976Sjmallett info.user_info = (long) 1065215976Sjmallett "ERROR POW_ECC_ERR[DBE]: Double bit error\n"; 1066215976Sjmallett fail |= cvmx_error_add(&info); 1067215976Sjmallett 1068215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1069215976Sjmallett info.status_addr = CVMX_POW_ECC_ERR; 1070215976Sjmallett info.status_mask = 1ull<<12 /* rpe */; 1071215976Sjmallett info.enable_addr = CVMX_POW_ECC_ERR; 1072215976Sjmallett info.enable_mask = 1ull<<13 /* rpe_ie */; 1073215976Sjmallett info.flags = 0; 1074215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 1075215976Sjmallett info.group_index = 0; 1076215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1077215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 1078215976Sjmallett info.parent.status_mask = 1ull<<12 /* pow */; 1079215976Sjmallett info.func = __cvmx_error_handle_pow_ecc_err_rpe; 1080215976Sjmallett info.user_info = (long) 1081215976Sjmallett "ERROR POW_ECC_ERR[RPE]: Remote pointer error\n"; 1082215976Sjmallett fail |= cvmx_error_add(&info); 1083215976Sjmallett 1084215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1085215976Sjmallett info.status_addr = CVMX_POW_ECC_ERR; 1086215976Sjmallett info.status_mask = 0x1fffull<<16 /* iop */; 1087215976Sjmallett info.enable_addr = CVMX_POW_ECC_ERR; 1088215976Sjmallett info.enable_mask = 0x1fffull<<32 /* iop_ie */; 1089215976Sjmallett info.flags = 0; 1090215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 1091215976Sjmallett info.group_index = 0; 1092215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1093215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 1094215976Sjmallett info.parent.status_mask = 1ull<<12 /* pow */; 1095215976Sjmallett info.func = __cvmx_error_handle_pow_ecc_err_iop; 1096215976Sjmallett info.user_info = (long) 1097215976Sjmallett "ERROR POW_ECC_ERR[IOP]: Illegal operation errors\n"; 1098215976Sjmallett fail |= cvmx_error_add(&info); 1099215976Sjmallett 1100215976Sjmallett /* CVMX_RAD_REG_ERROR */ 1101215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1102215976Sjmallett info.status_addr = CVMX_RAD_REG_ERROR; 1103215976Sjmallett info.status_mask = 1ull<<0 /* doorbell */; 1104215976Sjmallett info.enable_addr = CVMX_RAD_REG_INT_MASK; 1105215976Sjmallett info.enable_mask = 1ull<<0 /* doorbell */; 1106215976Sjmallett info.flags = 0; 1107215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 1108215976Sjmallett info.group_index = 0; 1109215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1110215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 1111215976Sjmallett info.parent.status_mask = 1ull<<14 /* rad */; 1112215976Sjmallett info.func = __cvmx_error_display; 1113215976Sjmallett info.user_info = (long) 1114215976Sjmallett "ERROR RAD_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n"; 1115215976Sjmallett fail |= cvmx_error_add(&info); 1116215976Sjmallett 1117215976Sjmallett /* CVMX_PCSX_INTX_REG(0,0) */ 1118215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1119215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(0,0); 1120215976Sjmallett info.status_mask = 1ull<<2 /* an_err */; 1121215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0); 1122215976Sjmallett info.enable_mask = 1ull<<2 /* an_err_en */; 1123215976Sjmallett info.flags = 0; 1124215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1125215976Sjmallett info.group_index = 0; 1126215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1127215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 1128215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 1129215976Sjmallett info.func = __cvmx_error_display; 1130215976Sjmallett info.user_info = (long) 1131215976Sjmallett "ERROR PCSX_INTX_REG(0,0)[AN_ERR]: AN Error, AN resolution function failed\n"; 1132215976Sjmallett fail |= cvmx_error_add(&info); 1133215976Sjmallett 1134215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1135215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(0,0); 1136215976Sjmallett info.status_mask = 1ull<<3 /* txfifu */; 1137215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0); 1138215976Sjmallett info.enable_mask = 1ull<<3 /* txfifu_en */; 1139215976Sjmallett info.flags = 0; 1140215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1141215976Sjmallett info.group_index = 0; 1142215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1143215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 1144215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 1145215976Sjmallett info.func = __cvmx_error_display; 1146215976Sjmallett info.user_info = (long) 1147215976Sjmallett "ERROR PCSX_INTX_REG(0,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n" 1148215976Sjmallett " condition\n"; 1149215976Sjmallett fail |= cvmx_error_add(&info); 1150215976Sjmallett 1151215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1152215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(0,0); 1153215976Sjmallett info.status_mask = 1ull<<4 /* txfifo */; 1154215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0); 1155215976Sjmallett info.enable_mask = 1ull<<4 /* txfifo_en */; 1156215976Sjmallett info.flags = 0; 1157215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1158215976Sjmallett info.group_index = 0; 1159215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1160215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 1161215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 1162215976Sjmallett info.func = __cvmx_error_display; 1163215976Sjmallett info.user_info = (long) 1164215976Sjmallett "ERROR PCSX_INTX_REG(0,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n" 1165215976Sjmallett " condition\n"; 1166215976Sjmallett fail |= cvmx_error_add(&info); 1167215976Sjmallett 1168215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1169215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(0,0); 1170215976Sjmallett info.status_mask = 1ull<<5 /* txbad */; 1171215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0); 1172215976Sjmallett info.enable_mask = 1ull<<5 /* txbad_en */; 1173215976Sjmallett info.flags = 0; 1174215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1175215976Sjmallett info.group_index = 0; 1176215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1177215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 1178215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 1179215976Sjmallett info.func = __cvmx_error_display; 1180215976Sjmallett info.user_info = (long) 1181215976Sjmallett "ERROR PCSX_INTX_REG(0,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n" 1182215976Sjmallett " state. Should never be set during normal operation\n"; 1183215976Sjmallett fail |= cvmx_error_add(&info); 1184215976Sjmallett 1185215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1186215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(0,0); 1187215976Sjmallett info.status_mask = 1ull<<7 /* rxbad */; 1188215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0); 1189215976Sjmallett info.enable_mask = 1ull<<7 /* rxbad_en */; 1190215976Sjmallett info.flags = 0; 1191215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1192215976Sjmallett info.group_index = 0; 1193215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1194215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 1195215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 1196215976Sjmallett info.func = __cvmx_error_display; 1197215976Sjmallett info.user_info = (long) 1198215976Sjmallett "ERROR PCSX_INTX_REG(0,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n" 1199215976Sjmallett " state. Should never be set during normal operation\n"; 1200215976Sjmallett fail |= cvmx_error_add(&info); 1201215976Sjmallett 1202215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1203215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(0,0); 1204215976Sjmallett info.status_mask = 1ull<<8 /* rxlock */; 1205215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0); 1206215976Sjmallett info.enable_mask = 1ull<<8 /* rxlock_en */; 1207215976Sjmallett info.flags = 0; 1208215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1209215976Sjmallett info.group_index = 0; 1210215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1211215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 1212215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 1213215976Sjmallett info.func = __cvmx_error_display; 1214215976Sjmallett info.user_info = (long) 1215215976Sjmallett "ERROR PCSX_INTX_REG(0,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n" 1216215976Sjmallett " failure occurs\n" 1217215976Sjmallett " Cannot fire in loopback1 mode\n"; 1218215976Sjmallett fail |= cvmx_error_add(&info); 1219215976Sjmallett 1220215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1221215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(0,0); 1222215976Sjmallett info.status_mask = 1ull<<9 /* an_bad */; 1223215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0); 1224215976Sjmallett info.enable_mask = 1ull<<9 /* an_bad_en */; 1225215976Sjmallett info.flags = 0; 1226215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1227215976Sjmallett info.group_index = 0; 1228215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1229215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 1230215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 1231215976Sjmallett info.func = __cvmx_error_display; 1232215976Sjmallett info.user_info = (long) 1233215976Sjmallett "ERROR PCSX_INTX_REG(0,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n" 1234215976Sjmallett " state. Should never be set during normal operation\n"; 1235215976Sjmallett fail |= cvmx_error_add(&info); 1236215976Sjmallett 1237215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1238215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(0,0); 1239215976Sjmallett info.status_mask = 1ull<<10 /* sync_bad */; 1240215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0); 1241215976Sjmallett info.enable_mask = 1ull<<10 /* sync_bad_en */; 1242215976Sjmallett info.flags = 0; 1243215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1244215976Sjmallett info.group_index = 0; 1245215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1246215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 1247215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 1248215976Sjmallett info.func = __cvmx_error_display; 1249215976Sjmallett info.user_info = (long) 1250215976Sjmallett "ERROR PCSX_INTX_REG(0,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n" 1251215976Sjmallett " state. Should never be set during normal operation\n"; 1252215976Sjmallett fail |= cvmx_error_add(&info); 1253215976Sjmallett 1254215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1255215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(0,0); 1256215976Sjmallett info.status_mask = 1ull<<12 /* dbg_sync */; 1257215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(0,0); 1258215976Sjmallett info.enable_mask = 1ull<<12 /* dbg_sync_en */; 1259215976Sjmallett info.flags = 0; 1260215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1261215976Sjmallett info.group_index = 0; 1262215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1263215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 1264215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 1265215976Sjmallett info.func = __cvmx_error_display; 1266215976Sjmallett info.user_info = (long) 1267215976Sjmallett "ERROR PCSX_INTX_REG(0,0)[DBG_SYNC]: Code Group sync failure debug help\n"; 1268215976Sjmallett fail |= cvmx_error_add(&info); 1269215976Sjmallett 1270215976Sjmallett /* CVMX_PCSX_INTX_REG(1,0) */ 1271215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1272215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(1,0); 1273215976Sjmallett info.status_mask = 1ull<<2 /* an_err */; 1274215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0); 1275215976Sjmallett info.enable_mask = 1ull<<2 /* an_err_en */; 1276215976Sjmallett info.flags = 0; 1277215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1278215976Sjmallett info.group_index = 1; 1279215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1280215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 1281215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 1282215976Sjmallett info.func = __cvmx_error_display; 1283215976Sjmallett info.user_info = (long) 1284215976Sjmallett "ERROR PCSX_INTX_REG(1,0)[AN_ERR]: AN Error, AN resolution function failed\n"; 1285215976Sjmallett fail |= cvmx_error_add(&info); 1286215976Sjmallett 1287215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1288215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(1,0); 1289215976Sjmallett info.status_mask = 1ull<<3 /* txfifu */; 1290215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0); 1291215976Sjmallett info.enable_mask = 1ull<<3 /* txfifu_en */; 1292215976Sjmallett info.flags = 0; 1293215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1294215976Sjmallett info.group_index = 1; 1295215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1296215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 1297215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 1298215976Sjmallett info.func = __cvmx_error_display; 1299215976Sjmallett info.user_info = (long) 1300215976Sjmallett "ERROR PCSX_INTX_REG(1,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n" 1301215976Sjmallett " condition\n"; 1302215976Sjmallett fail |= cvmx_error_add(&info); 1303215976Sjmallett 1304215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1305215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(1,0); 1306215976Sjmallett info.status_mask = 1ull<<4 /* txfifo */; 1307215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0); 1308215976Sjmallett info.enable_mask = 1ull<<4 /* txfifo_en */; 1309215976Sjmallett info.flags = 0; 1310215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1311215976Sjmallett info.group_index = 1; 1312215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1313215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 1314215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 1315215976Sjmallett info.func = __cvmx_error_display; 1316215976Sjmallett info.user_info = (long) 1317215976Sjmallett "ERROR PCSX_INTX_REG(1,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n" 1318215976Sjmallett " condition\n"; 1319215976Sjmallett fail |= cvmx_error_add(&info); 1320215976Sjmallett 1321215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1322215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(1,0); 1323215976Sjmallett info.status_mask = 1ull<<5 /* txbad */; 1324215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0); 1325215976Sjmallett info.enable_mask = 1ull<<5 /* txbad_en */; 1326215976Sjmallett info.flags = 0; 1327215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1328215976Sjmallett info.group_index = 1; 1329215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1330215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 1331215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 1332215976Sjmallett info.func = __cvmx_error_display; 1333215976Sjmallett info.user_info = (long) 1334215976Sjmallett "ERROR PCSX_INTX_REG(1,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n" 1335215976Sjmallett " state. Should never be set during normal operation\n"; 1336215976Sjmallett fail |= cvmx_error_add(&info); 1337215976Sjmallett 1338215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1339215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(1,0); 1340215976Sjmallett info.status_mask = 1ull<<7 /* rxbad */; 1341215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0); 1342215976Sjmallett info.enable_mask = 1ull<<7 /* rxbad_en */; 1343215976Sjmallett info.flags = 0; 1344215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1345215976Sjmallett info.group_index = 1; 1346215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1347215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 1348215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 1349215976Sjmallett info.func = __cvmx_error_display; 1350215976Sjmallett info.user_info = (long) 1351215976Sjmallett "ERROR PCSX_INTX_REG(1,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n" 1352215976Sjmallett " state. Should never be set during normal operation\n"; 1353215976Sjmallett fail |= cvmx_error_add(&info); 1354215976Sjmallett 1355215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1356215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(1,0); 1357215976Sjmallett info.status_mask = 1ull<<8 /* rxlock */; 1358215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0); 1359215976Sjmallett info.enable_mask = 1ull<<8 /* rxlock_en */; 1360215976Sjmallett info.flags = 0; 1361215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1362215976Sjmallett info.group_index = 1; 1363215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1364215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 1365215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 1366215976Sjmallett info.func = __cvmx_error_display; 1367215976Sjmallett info.user_info = (long) 1368215976Sjmallett "ERROR PCSX_INTX_REG(1,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n" 1369215976Sjmallett " failure occurs\n" 1370215976Sjmallett " Cannot fire in loopback1 mode\n"; 1371215976Sjmallett fail |= cvmx_error_add(&info); 1372215976Sjmallett 1373215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1374215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(1,0); 1375215976Sjmallett info.status_mask = 1ull<<9 /* an_bad */; 1376215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0); 1377215976Sjmallett info.enable_mask = 1ull<<9 /* an_bad_en */; 1378215976Sjmallett info.flags = 0; 1379215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1380215976Sjmallett info.group_index = 1; 1381215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1382215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 1383215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 1384215976Sjmallett info.func = __cvmx_error_display; 1385215976Sjmallett info.user_info = (long) 1386215976Sjmallett "ERROR PCSX_INTX_REG(1,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n" 1387215976Sjmallett " state. Should never be set during normal operation\n"; 1388215976Sjmallett fail |= cvmx_error_add(&info); 1389215976Sjmallett 1390215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1391215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(1,0); 1392215976Sjmallett info.status_mask = 1ull<<10 /* sync_bad */; 1393215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0); 1394215976Sjmallett info.enable_mask = 1ull<<10 /* sync_bad_en */; 1395215976Sjmallett info.flags = 0; 1396215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1397215976Sjmallett info.group_index = 1; 1398215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1399215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 1400215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 1401215976Sjmallett info.func = __cvmx_error_display; 1402215976Sjmallett info.user_info = (long) 1403215976Sjmallett "ERROR PCSX_INTX_REG(1,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n" 1404215976Sjmallett " state. Should never be set during normal operation\n"; 1405215976Sjmallett fail |= cvmx_error_add(&info); 1406215976Sjmallett 1407215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1408215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(1,0); 1409215976Sjmallett info.status_mask = 1ull<<12 /* dbg_sync */; 1410215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(1,0); 1411215976Sjmallett info.enable_mask = 1ull<<12 /* dbg_sync_en */; 1412215976Sjmallett info.flags = 0; 1413215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1414215976Sjmallett info.group_index = 1; 1415215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1416215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 1417215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 1418215976Sjmallett info.func = __cvmx_error_display; 1419215976Sjmallett info.user_info = (long) 1420215976Sjmallett "ERROR PCSX_INTX_REG(1,0)[DBG_SYNC]: Code Group sync failure debug help\n"; 1421215976Sjmallett fail |= cvmx_error_add(&info); 1422215976Sjmallett 1423215976Sjmallett /* CVMX_PCSX_INTX_REG(2,0) */ 1424215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1425215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(2,0); 1426215976Sjmallett info.status_mask = 1ull<<2 /* an_err */; 1427215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0); 1428215976Sjmallett info.enable_mask = 1ull<<2 /* an_err_en */; 1429215976Sjmallett info.flags = 0; 1430215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1431215976Sjmallett info.group_index = 2; 1432215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1433215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 1434215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 1435215976Sjmallett info.func = __cvmx_error_display; 1436215976Sjmallett info.user_info = (long) 1437215976Sjmallett "ERROR PCSX_INTX_REG(2,0)[AN_ERR]: AN Error, AN resolution function failed\n"; 1438215976Sjmallett fail |= cvmx_error_add(&info); 1439215976Sjmallett 1440215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1441215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(2,0); 1442215976Sjmallett info.status_mask = 1ull<<3 /* txfifu */; 1443215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0); 1444215976Sjmallett info.enable_mask = 1ull<<3 /* txfifu_en */; 1445215976Sjmallett info.flags = 0; 1446215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1447215976Sjmallett info.group_index = 2; 1448215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1449215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 1450215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 1451215976Sjmallett info.func = __cvmx_error_display; 1452215976Sjmallett info.user_info = (long) 1453215976Sjmallett "ERROR PCSX_INTX_REG(2,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n" 1454215976Sjmallett " condition\n"; 1455215976Sjmallett fail |= cvmx_error_add(&info); 1456215976Sjmallett 1457215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1458215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(2,0); 1459215976Sjmallett info.status_mask = 1ull<<4 /* txfifo */; 1460215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0); 1461215976Sjmallett info.enable_mask = 1ull<<4 /* txfifo_en */; 1462215976Sjmallett info.flags = 0; 1463215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1464215976Sjmallett info.group_index = 2; 1465215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1466215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 1467215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 1468215976Sjmallett info.func = __cvmx_error_display; 1469215976Sjmallett info.user_info = (long) 1470215976Sjmallett "ERROR PCSX_INTX_REG(2,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n" 1471215976Sjmallett " condition\n"; 1472215976Sjmallett fail |= cvmx_error_add(&info); 1473215976Sjmallett 1474215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1475215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(2,0); 1476215976Sjmallett info.status_mask = 1ull<<5 /* txbad */; 1477215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0); 1478215976Sjmallett info.enable_mask = 1ull<<5 /* txbad_en */; 1479215976Sjmallett info.flags = 0; 1480215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1481215976Sjmallett info.group_index = 2; 1482215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1483215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 1484215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 1485215976Sjmallett info.func = __cvmx_error_display; 1486215976Sjmallett info.user_info = (long) 1487215976Sjmallett "ERROR PCSX_INTX_REG(2,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n" 1488215976Sjmallett " state. Should never be set during normal operation\n"; 1489215976Sjmallett fail |= cvmx_error_add(&info); 1490215976Sjmallett 1491215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1492215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(2,0); 1493215976Sjmallett info.status_mask = 1ull<<7 /* rxbad */; 1494215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0); 1495215976Sjmallett info.enable_mask = 1ull<<7 /* rxbad_en */; 1496215976Sjmallett info.flags = 0; 1497215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1498215976Sjmallett info.group_index = 2; 1499215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1500215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 1501215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 1502215976Sjmallett info.func = __cvmx_error_display; 1503215976Sjmallett info.user_info = (long) 1504215976Sjmallett "ERROR PCSX_INTX_REG(2,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n" 1505215976Sjmallett " state. Should never be set during normal operation\n"; 1506215976Sjmallett fail |= cvmx_error_add(&info); 1507215976Sjmallett 1508215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1509215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(2,0); 1510215976Sjmallett info.status_mask = 1ull<<8 /* rxlock */; 1511215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0); 1512215976Sjmallett info.enable_mask = 1ull<<8 /* rxlock_en */; 1513215976Sjmallett info.flags = 0; 1514215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1515215976Sjmallett info.group_index = 2; 1516215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1517215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 1518215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 1519215976Sjmallett info.func = __cvmx_error_display; 1520215976Sjmallett info.user_info = (long) 1521215976Sjmallett "ERROR PCSX_INTX_REG(2,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n" 1522215976Sjmallett " failure occurs\n" 1523215976Sjmallett " Cannot fire in loopback1 mode\n"; 1524215976Sjmallett fail |= cvmx_error_add(&info); 1525215976Sjmallett 1526215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1527215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(2,0); 1528215976Sjmallett info.status_mask = 1ull<<9 /* an_bad */; 1529215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0); 1530215976Sjmallett info.enable_mask = 1ull<<9 /* an_bad_en */; 1531215976Sjmallett info.flags = 0; 1532215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1533215976Sjmallett info.group_index = 2; 1534215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1535215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 1536215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 1537215976Sjmallett info.func = __cvmx_error_display; 1538215976Sjmallett info.user_info = (long) 1539215976Sjmallett "ERROR PCSX_INTX_REG(2,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n" 1540215976Sjmallett " state. Should never be set during normal operation\n"; 1541215976Sjmallett fail |= cvmx_error_add(&info); 1542215976Sjmallett 1543215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1544215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(2,0); 1545215976Sjmallett info.status_mask = 1ull<<10 /* sync_bad */; 1546215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0); 1547215976Sjmallett info.enable_mask = 1ull<<10 /* sync_bad_en */; 1548215976Sjmallett info.flags = 0; 1549215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1550215976Sjmallett info.group_index = 2; 1551215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1552215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 1553215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 1554215976Sjmallett info.func = __cvmx_error_display; 1555215976Sjmallett info.user_info = (long) 1556215976Sjmallett "ERROR PCSX_INTX_REG(2,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n" 1557215976Sjmallett " state. Should never be set during normal operation\n"; 1558215976Sjmallett fail |= cvmx_error_add(&info); 1559215976Sjmallett 1560215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1561215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(2,0); 1562215976Sjmallett info.status_mask = 1ull<<12 /* dbg_sync */; 1563215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(2,0); 1564215976Sjmallett info.enable_mask = 1ull<<12 /* dbg_sync_en */; 1565215976Sjmallett info.flags = 0; 1566215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1567215976Sjmallett info.group_index = 2; 1568215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1569215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 1570215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 1571215976Sjmallett info.func = __cvmx_error_display; 1572215976Sjmallett info.user_info = (long) 1573215976Sjmallett "ERROR PCSX_INTX_REG(2,0)[DBG_SYNC]: Code Group sync failure debug help\n"; 1574215976Sjmallett fail |= cvmx_error_add(&info); 1575215976Sjmallett 1576215976Sjmallett /* CVMX_PCSX_INTX_REG(3,0) */ 1577215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1578215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(3,0); 1579215976Sjmallett info.status_mask = 1ull<<2 /* an_err */; 1580215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0); 1581215976Sjmallett info.enable_mask = 1ull<<2 /* an_err_en */; 1582215976Sjmallett info.flags = 0; 1583215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1584215976Sjmallett info.group_index = 3; 1585215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1586215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 1587215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 1588215976Sjmallett info.func = __cvmx_error_display; 1589215976Sjmallett info.user_info = (long) 1590215976Sjmallett "ERROR PCSX_INTX_REG(3,0)[AN_ERR]: AN Error, AN resolution function failed\n"; 1591215976Sjmallett fail |= cvmx_error_add(&info); 1592215976Sjmallett 1593215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1594215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(3,0); 1595215976Sjmallett info.status_mask = 1ull<<3 /* txfifu */; 1596215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0); 1597215976Sjmallett info.enable_mask = 1ull<<3 /* txfifu_en */; 1598215976Sjmallett info.flags = 0; 1599215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1600215976Sjmallett info.group_index = 3; 1601215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1602215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 1603215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 1604215976Sjmallett info.func = __cvmx_error_display; 1605215976Sjmallett info.user_info = (long) 1606215976Sjmallett "ERROR PCSX_INTX_REG(3,0)[TXFIFU]: Set whenever HW detects a TX fifo underflowflow\n" 1607215976Sjmallett " condition\n"; 1608215976Sjmallett fail |= cvmx_error_add(&info); 1609215976Sjmallett 1610215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1611215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(3,0); 1612215976Sjmallett info.status_mask = 1ull<<4 /* txfifo */; 1613215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0); 1614215976Sjmallett info.enable_mask = 1ull<<4 /* txfifo_en */; 1615215976Sjmallett info.flags = 0; 1616215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1617215976Sjmallett info.group_index = 3; 1618215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1619215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 1620215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 1621215976Sjmallett info.func = __cvmx_error_display; 1622215976Sjmallett info.user_info = (long) 1623215976Sjmallett "ERROR PCSX_INTX_REG(3,0)[TXFIFO]: Set whenever HW detects a TX fifo overflow\n" 1624215976Sjmallett " condition\n"; 1625215976Sjmallett fail |= cvmx_error_add(&info); 1626215976Sjmallett 1627215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1628215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(3,0); 1629215976Sjmallett info.status_mask = 1ull<<5 /* txbad */; 1630215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0); 1631215976Sjmallett info.enable_mask = 1ull<<5 /* txbad_en */; 1632215976Sjmallett info.flags = 0; 1633215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1634215976Sjmallett info.group_index = 3; 1635215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1636215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 1637215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 1638215976Sjmallett info.func = __cvmx_error_display; 1639215976Sjmallett info.user_info = (long) 1640215976Sjmallett "ERROR PCSX_INTX_REG(3,0)[TXBAD]: Set by HW whenever tx st machine reaches a bad\n" 1641215976Sjmallett " state. Should never be set during normal operation\n"; 1642215976Sjmallett fail |= cvmx_error_add(&info); 1643215976Sjmallett 1644215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1645215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(3,0); 1646215976Sjmallett info.status_mask = 1ull<<7 /* rxbad */; 1647215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0); 1648215976Sjmallett info.enable_mask = 1ull<<7 /* rxbad_en */; 1649215976Sjmallett info.flags = 0; 1650215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1651215976Sjmallett info.group_index = 3; 1652215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1653215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 1654215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 1655215976Sjmallett info.func = __cvmx_error_display; 1656215976Sjmallett info.user_info = (long) 1657215976Sjmallett "ERROR PCSX_INTX_REG(3,0)[RXBAD]: Set by HW whenever rx st machine reaches a bad\n" 1658215976Sjmallett " state. Should never be set during normal operation\n"; 1659215976Sjmallett fail |= cvmx_error_add(&info); 1660215976Sjmallett 1661215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1662215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(3,0); 1663215976Sjmallett info.status_mask = 1ull<<8 /* rxlock */; 1664215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0); 1665215976Sjmallett info.enable_mask = 1ull<<8 /* rxlock_en */; 1666215976Sjmallett info.flags = 0; 1667215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1668215976Sjmallett info.group_index = 3; 1669215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1670215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 1671215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 1672215976Sjmallett info.func = __cvmx_error_display; 1673215976Sjmallett info.user_info = (long) 1674215976Sjmallett "ERROR PCSX_INTX_REG(3,0)[RXLOCK]: Set by HW whenever code group Sync or bit lock\n" 1675215976Sjmallett " failure occurs\n" 1676215976Sjmallett " Cannot fire in loopback1 mode\n"; 1677215976Sjmallett fail |= cvmx_error_add(&info); 1678215976Sjmallett 1679215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1680215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(3,0); 1681215976Sjmallett info.status_mask = 1ull<<9 /* an_bad */; 1682215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0); 1683215976Sjmallett info.enable_mask = 1ull<<9 /* an_bad_en */; 1684215976Sjmallett info.flags = 0; 1685215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1686215976Sjmallett info.group_index = 3; 1687215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1688215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 1689215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 1690215976Sjmallett info.func = __cvmx_error_display; 1691215976Sjmallett info.user_info = (long) 1692215976Sjmallett "ERROR PCSX_INTX_REG(3,0)[AN_BAD]: Set by HW whenever AN st machine reaches a bad\n" 1693215976Sjmallett " state. Should never be set during normal operation\n"; 1694215976Sjmallett fail |= cvmx_error_add(&info); 1695215976Sjmallett 1696215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1697215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(3,0); 1698215976Sjmallett info.status_mask = 1ull<<10 /* sync_bad */; 1699215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0); 1700215976Sjmallett info.enable_mask = 1ull<<10 /* sync_bad_en */; 1701215976Sjmallett info.flags = 0; 1702215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1703215976Sjmallett info.group_index = 3; 1704215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1705215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 1706215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 1707215976Sjmallett info.func = __cvmx_error_display; 1708215976Sjmallett info.user_info = (long) 1709215976Sjmallett "ERROR PCSX_INTX_REG(3,0)[SYNC_BAD]: Set by HW whenever rx sync st machine reaches a bad\n" 1710215976Sjmallett " state. Should never be set during normal operation\n"; 1711215976Sjmallett fail |= cvmx_error_add(&info); 1712215976Sjmallett 1713215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1714215976Sjmallett info.status_addr = CVMX_PCSX_INTX_REG(3,0); 1715215976Sjmallett info.status_mask = 1ull<<12 /* dbg_sync */; 1716215976Sjmallett info.enable_addr = CVMX_PCSX_INTX_EN_REG(3,0); 1717215976Sjmallett info.enable_mask = 1ull<<12 /* dbg_sync_en */; 1718215976Sjmallett info.flags = 0; 1719215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1720215976Sjmallett info.group_index = 3; 1721215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1722215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 1723215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 1724215976Sjmallett info.func = __cvmx_error_display; 1725215976Sjmallett info.user_info = (long) 1726215976Sjmallett "ERROR PCSX_INTX_REG(3,0)[DBG_SYNC]: Code Group sync failure debug help\n"; 1727215976Sjmallett fail |= cvmx_error_add(&info); 1728215976Sjmallett 1729215976Sjmallett /* CVMX_PCSXX_INT_REG(0) */ 1730215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1731215976Sjmallett info.status_addr = CVMX_PCSXX_INT_REG(0); 1732215976Sjmallett info.status_mask = 1ull<<0 /* txflt */; 1733215976Sjmallett info.enable_addr = CVMX_PCSXX_INT_EN_REG(0); 1734215976Sjmallett info.enable_mask = 1ull<<0 /* txflt_en */; 1735215976Sjmallett info.flags = 0; 1736215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1737215976Sjmallett info.group_index = 0; 1738215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1739215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 1740215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 1741215976Sjmallett info.func = __cvmx_error_display; 1742215976Sjmallett info.user_info = (long) 1743215976Sjmallett "ERROR PCSXX_INT_REG(0)[TXFLT]: None defined at this time, always 0x0\n"; 1744215976Sjmallett fail |= cvmx_error_add(&info); 1745215976Sjmallett 1746215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1747215976Sjmallett info.status_addr = CVMX_PCSXX_INT_REG(0); 1748215976Sjmallett info.status_mask = 1ull<<1 /* rxbad */; 1749215976Sjmallett info.enable_addr = CVMX_PCSXX_INT_EN_REG(0); 1750215976Sjmallett info.enable_mask = 1ull<<1 /* rxbad_en */; 1751215976Sjmallett info.flags = 0; 1752215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1753215976Sjmallett info.group_index = 0; 1754215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1755215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 1756215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 1757215976Sjmallett info.func = __cvmx_error_display; 1758215976Sjmallett info.user_info = (long) 1759215976Sjmallett "ERROR PCSXX_INT_REG(0)[RXBAD]: Set when RX state machine in bad state\n"; 1760215976Sjmallett fail |= cvmx_error_add(&info); 1761215976Sjmallett 1762215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1763215976Sjmallett info.status_addr = CVMX_PCSXX_INT_REG(0); 1764215976Sjmallett info.status_mask = 1ull<<2 /* rxsynbad */; 1765215976Sjmallett info.enable_addr = CVMX_PCSXX_INT_EN_REG(0); 1766215976Sjmallett info.enable_mask = 1ull<<2 /* rxsynbad_en */; 1767215976Sjmallett info.flags = 0; 1768215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1769215976Sjmallett info.group_index = 0; 1770215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1771215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 1772215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 1773215976Sjmallett info.func = __cvmx_error_display; 1774215976Sjmallett info.user_info = (long) 1775215976Sjmallett "ERROR PCSXX_INT_REG(0)[RXSYNBAD]: Set when RX code grp sync st machine in bad state\n" 1776215976Sjmallett " in one of the 4 xaui lanes\n"; 1777215976Sjmallett fail |= cvmx_error_add(&info); 1778215976Sjmallett 1779215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1780215976Sjmallett info.status_addr = CVMX_PCSXX_INT_REG(0); 1781215976Sjmallett info.status_mask = 1ull<<4 /* synlos */; 1782215976Sjmallett info.enable_addr = CVMX_PCSXX_INT_EN_REG(0); 1783215976Sjmallett info.enable_mask = 1ull<<4 /* synlos_en */; 1784215976Sjmallett info.flags = 0; 1785215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1786215976Sjmallett info.group_index = 0; 1787215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1788215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 1789215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 1790215976Sjmallett info.func = __cvmx_error_display; 1791215976Sjmallett info.user_info = (long) 1792215976Sjmallett "ERROR PCSXX_INT_REG(0)[SYNLOS]: Set when Code group sync lost on 1 or more lanes\n"; 1793215976Sjmallett fail |= cvmx_error_add(&info); 1794215976Sjmallett 1795215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1796215976Sjmallett info.status_addr = CVMX_PCSXX_INT_REG(0); 1797215976Sjmallett info.status_mask = 1ull<<5 /* algnlos */; 1798215976Sjmallett info.enable_addr = CVMX_PCSXX_INT_EN_REG(0); 1799215976Sjmallett info.enable_mask = 1ull<<5 /* algnlos_en */; 1800215976Sjmallett info.flags = 0; 1801215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1802215976Sjmallett info.group_index = 0; 1803215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1804215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 1805215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 1806215976Sjmallett info.func = __cvmx_error_display; 1807215976Sjmallett info.user_info = (long) 1808215976Sjmallett "ERROR PCSXX_INT_REG(0)[ALGNLOS]: Set when XAUI lanes lose alignment\n"; 1809215976Sjmallett fail |= cvmx_error_add(&info); 1810215976Sjmallett 1811215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1812215976Sjmallett info.status_addr = CVMX_PCSXX_INT_REG(0); 1813215976Sjmallett info.status_mask = 1ull<<6 /* dbg_sync */; 1814215976Sjmallett info.enable_addr = CVMX_PCSXX_INT_EN_REG(0); 1815215976Sjmallett info.enable_mask = 1ull<<6 /* dbg_sync_en */; 1816215976Sjmallett info.flags = 0; 1817215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 1818215976Sjmallett info.group_index = 0; 1819215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1820215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 1821215976Sjmallett info.parent.status_mask = 1ull<<22 /* asxpcs0 */; 1822215976Sjmallett info.func = __cvmx_error_display; 1823215976Sjmallett info.user_info = (long) 1824215976Sjmallett "ERROR PCSXX_INT_REG(0)[DBG_SYNC]: Code Group sync failure debug help, see Note below\n"; 1825215976Sjmallett fail |= cvmx_error_add(&info); 1826215976Sjmallett 1827215976Sjmallett /* CVMX_PIP_INT_REG */ 1828215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1829215976Sjmallett info.status_addr = CVMX_PIP_INT_REG; 1830215976Sjmallett info.status_mask = 1ull<<3 /* prtnxa */; 1831215976Sjmallett info.enable_addr = CVMX_PIP_INT_EN; 1832215976Sjmallett info.enable_mask = 1ull<<3 /* prtnxa */; 1833215976Sjmallett info.flags = 0; 1834215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 1835215976Sjmallett info.group_index = 0; 1836215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1837215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 1838215976Sjmallett info.parent.status_mask = 1ull<<20 /* pip */; 1839215976Sjmallett info.func = __cvmx_error_display; 1840215976Sjmallett info.user_info = (long) 1841215976Sjmallett "ERROR PIP_INT_REG[PRTNXA]: Non-existent port\n"; 1842215976Sjmallett fail |= cvmx_error_add(&info); 1843215976Sjmallett 1844215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1845215976Sjmallett info.status_addr = CVMX_PIP_INT_REG; 1846215976Sjmallett info.status_mask = 1ull<<4 /* badtag */; 1847215976Sjmallett info.enable_addr = CVMX_PIP_INT_EN; 1848215976Sjmallett info.enable_mask = 1ull<<4 /* badtag */; 1849215976Sjmallett info.flags = 0; 1850215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 1851215976Sjmallett info.group_index = 0; 1852215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1853215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 1854215976Sjmallett info.parent.status_mask = 1ull<<20 /* pip */; 1855215976Sjmallett info.func = __cvmx_error_display; 1856215976Sjmallett info.user_info = (long) 1857215976Sjmallett "ERROR PIP_INT_REG[BADTAG]: A bad tag was sent from IPD\n"; 1858215976Sjmallett fail |= cvmx_error_add(&info); 1859215976Sjmallett 1860215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1861215976Sjmallett info.status_addr = CVMX_PIP_INT_REG; 1862215976Sjmallett info.status_mask = 1ull<<5 /* skprunt */; 1863215976Sjmallett info.enable_addr = CVMX_PIP_INT_EN; 1864215976Sjmallett info.enable_mask = 1ull<<5 /* skprunt */; 1865215976Sjmallett info.flags = 0; 1866215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 1867215976Sjmallett info.group_index = 0; 1868215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1869215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 1870215976Sjmallett info.parent.status_mask = 1ull<<20 /* pip */; 1871215976Sjmallett info.func = __cvmx_error_display; 1872215976Sjmallett info.user_info = (long) 1873215976Sjmallett "ERROR PIP_INT_REG[SKPRUNT]: Packet was engulfed by skipper\n" 1874215976Sjmallett " This interrupt can occur with received PARTIAL\n" 1875215976Sjmallett " packets that are truncated to SKIP bytes or\n" 1876215976Sjmallett " smaller.\n"; 1877215976Sjmallett fail |= cvmx_error_add(&info); 1878215976Sjmallett 1879215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1880215976Sjmallett info.status_addr = CVMX_PIP_INT_REG; 1881215976Sjmallett info.status_mask = 1ull<<6 /* todoovr */; 1882215976Sjmallett info.enable_addr = CVMX_PIP_INT_EN; 1883215976Sjmallett info.enable_mask = 1ull<<6 /* todoovr */; 1884215976Sjmallett info.flags = 0; 1885215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 1886215976Sjmallett info.group_index = 0; 1887215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1888215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 1889215976Sjmallett info.parent.status_mask = 1ull<<20 /* pip */; 1890215976Sjmallett info.func = __cvmx_error_display; 1891215976Sjmallett info.user_info = (long) 1892215976Sjmallett "ERROR PIP_INT_REG[TODOOVR]: Todo list overflow (see PIP_BCK_PRS[HIWATER])\n"; 1893215976Sjmallett fail |= cvmx_error_add(&info); 1894215976Sjmallett 1895215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1896215976Sjmallett info.status_addr = CVMX_PIP_INT_REG; 1897215976Sjmallett info.status_mask = 1ull<<7 /* feperr */; 1898215976Sjmallett info.enable_addr = CVMX_PIP_INT_EN; 1899215976Sjmallett info.enable_mask = 1ull<<7 /* feperr */; 1900215976Sjmallett info.flags = 0; 1901215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 1902215976Sjmallett info.group_index = 0; 1903215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1904215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 1905215976Sjmallett info.parent.status_mask = 1ull<<20 /* pip */; 1906215976Sjmallett info.func = __cvmx_error_display; 1907215976Sjmallett info.user_info = (long) 1908215976Sjmallett "ERROR PIP_INT_REG[FEPERR]: Parity Error in front end memory\n"; 1909215976Sjmallett fail |= cvmx_error_add(&info); 1910215976Sjmallett 1911215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1912215976Sjmallett info.status_addr = CVMX_PIP_INT_REG; 1913215976Sjmallett info.status_mask = 1ull<<8 /* beperr */; 1914215976Sjmallett info.enable_addr = CVMX_PIP_INT_EN; 1915215976Sjmallett info.enable_mask = 1ull<<8 /* beperr */; 1916215976Sjmallett info.flags = 0; 1917215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 1918215976Sjmallett info.group_index = 0; 1919215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1920215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 1921215976Sjmallett info.parent.status_mask = 1ull<<20 /* pip */; 1922215976Sjmallett info.func = __cvmx_error_display; 1923215976Sjmallett info.user_info = (long) 1924215976Sjmallett "ERROR PIP_INT_REG[BEPERR]: Parity Error in back end memory\n"; 1925215976Sjmallett fail |= cvmx_error_add(&info); 1926215976Sjmallett 1927215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1928215976Sjmallett info.status_addr = CVMX_PIP_INT_REG; 1929215976Sjmallett info.status_mask = 1ull<<12 /* punyerr */; 1930215976Sjmallett info.enable_addr = CVMX_PIP_INT_EN; 1931215976Sjmallett info.enable_mask = 1ull<<12 /* punyerr */; 1932215976Sjmallett info.flags = 0; 1933215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 1934215976Sjmallett info.group_index = 0; 1935215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1936215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 1937215976Sjmallett info.parent.status_mask = 1ull<<20 /* pip */; 1938215976Sjmallett info.func = __cvmx_error_display; 1939215976Sjmallett info.user_info = (long) 1940215976Sjmallett "ERROR PIP_INT_REG[PUNYERR]: Frame was received with length <=4B when CRC\n" 1941215976Sjmallett " stripping in IPD is enable\n"; 1942215976Sjmallett fail |= cvmx_error_add(&info); 1943215976Sjmallett 1944215976Sjmallett /* CVMX_PKO_REG_ERROR */ 1945215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1946215976Sjmallett info.status_addr = CVMX_PKO_REG_ERROR; 1947215976Sjmallett info.status_mask = 1ull<<0 /* parity */; 1948215976Sjmallett info.enable_addr = CVMX_PKO_REG_INT_MASK; 1949215976Sjmallett info.enable_mask = 1ull<<0 /* parity */; 1950215976Sjmallett info.flags = 0; 1951215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 1952215976Sjmallett info.group_index = 0; 1953215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1954215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 1955215976Sjmallett info.parent.status_mask = 1ull<<10 /* pko */; 1956215976Sjmallett info.func = __cvmx_error_display; 1957215976Sjmallett info.user_info = (long) 1958215976Sjmallett "ERROR PKO_REG_ERROR[PARITY]: Read parity error at port data buffer\n"; 1959215976Sjmallett fail |= cvmx_error_add(&info); 1960215976Sjmallett 1961215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1962215976Sjmallett info.status_addr = CVMX_PKO_REG_ERROR; 1963215976Sjmallett info.status_mask = 1ull<<1 /* doorbell */; 1964215976Sjmallett info.enable_addr = CVMX_PKO_REG_INT_MASK; 1965215976Sjmallett info.enable_mask = 1ull<<1 /* doorbell */; 1966215976Sjmallett info.flags = 0; 1967215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 1968215976Sjmallett info.group_index = 0; 1969215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1970215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 1971215976Sjmallett info.parent.status_mask = 1ull<<10 /* pko */; 1972215976Sjmallett info.func = __cvmx_error_display; 1973215976Sjmallett info.user_info = (long) 1974215976Sjmallett "ERROR PKO_REG_ERROR[DOORBELL]: A doorbell count has overflowed\n"; 1975215976Sjmallett fail |= cvmx_error_add(&info); 1976215976Sjmallett 1977215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1978215976Sjmallett info.status_addr = CVMX_PKO_REG_ERROR; 1979215976Sjmallett info.status_mask = 1ull<<2 /* currzero */; 1980215976Sjmallett info.enable_addr = CVMX_PKO_REG_INT_MASK; 1981215976Sjmallett info.enable_mask = 1ull<<2 /* currzero */; 1982215976Sjmallett info.flags = 0; 1983215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 1984215976Sjmallett info.group_index = 0; 1985215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 1986215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 1987215976Sjmallett info.parent.status_mask = 1ull<<10 /* pko */; 1988215976Sjmallett info.func = __cvmx_error_display; 1989215976Sjmallett info.user_info = (long) 1990215976Sjmallett "ERROR PKO_REG_ERROR[CURRZERO]: A packet data pointer has size=0\n"; 1991215976Sjmallett fail |= cvmx_error_add(&info); 1992215976Sjmallett 1993215976Sjmallett /* CVMX_PEMX_INT_SUM(0) */ 1994215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 1995215976Sjmallett info.status_addr = CVMX_PEMX_INT_SUM(0); 1996215976Sjmallett info.status_mask = 1ull<<1 /* se */; 1997215976Sjmallett info.enable_addr = CVMX_PEMX_INT_ENB(0); 1998215976Sjmallett info.enable_mask = 1ull<<1 /* se */; 1999215976Sjmallett info.flags = 0; 2000215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2001215976Sjmallett info.group_index = 0; 2002215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2003215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 2004215976Sjmallett info.parent.status_mask = 1ull<<25 /* pem0 */; 2005215976Sjmallett info.func = __cvmx_error_display; 2006215976Sjmallett info.user_info = (long) 2007215976Sjmallett "ERROR PEMX_INT_SUM(0)[SE]: System Error, RC Mode Only.\n" 2008215976Sjmallett " (cfg_sys_err_rc)\n"; 2009215976Sjmallett fail |= cvmx_error_add(&info); 2010215976Sjmallett 2011215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2012215976Sjmallett info.status_addr = CVMX_PEMX_INT_SUM(0); 2013215976Sjmallett info.status_mask = 1ull<<4 /* up_b1 */; 2014215976Sjmallett info.enable_addr = CVMX_PEMX_INT_ENB(0); 2015215976Sjmallett info.enable_mask = 1ull<<4 /* up_b1 */; 2016215976Sjmallett info.flags = 0; 2017215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2018215976Sjmallett info.group_index = 0; 2019215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2020215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 2021215976Sjmallett info.parent.status_mask = 1ull<<25 /* pem0 */; 2022215976Sjmallett info.func = __cvmx_error_display; 2023215976Sjmallett info.user_info = (long) 2024215976Sjmallett "ERROR PEMX_INT_SUM(0)[UP_B1]: Received P-TLP for Bar1 when bar1 index valid\n" 2025215976Sjmallett " is not set.\n"; 2026215976Sjmallett fail |= cvmx_error_add(&info); 2027215976Sjmallett 2028215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2029215976Sjmallett info.status_addr = CVMX_PEMX_INT_SUM(0); 2030215976Sjmallett info.status_mask = 1ull<<5 /* up_b2 */; 2031215976Sjmallett info.enable_addr = CVMX_PEMX_INT_ENB(0); 2032215976Sjmallett info.enable_mask = 1ull<<5 /* up_b2 */; 2033215976Sjmallett info.flags = 0; 2034215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2035215976Sjmallett info.group_index = 0; 2036215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2037215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 2038215976Sjmallett info.parent.status_mask = 1ull<<25 /* pem0 */; 2039215976Sjmallett info.func = __cvmx_error_display; 2040215976Sjmallett info.user_info = (long) 2041215976Sjmallett "ERROR PEMX_INT_SUM(0)[UP_B2]: Received P-TLP for Bar2 when bar2 is disabeld.\n"; 2042215976Sjmallett fail |= cvmx_error_add(&info); 2043215976Sjmallett 2044215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2045215976Sjmallett info.status_addr = CVMX_PEMX_INT_SUM(0); 2046215976Sjmallett info.status_mask = 1ull<<6 /* up_bx */; 2047215976Sjmallett info.enable_addr = CVMX_PEMX_INT_ENB(0); 2048215976Sjmallett info.enable_mask = 1ull<<6 /* up_bx */; 2049215976Sjmallett info.flags = 0; 2050215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2051215976Sjmallett info.group_index = 0; 2052215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2053215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 2054215976Sjmallett info.parent.status_mask = 1ull<<25 /* pem0 */; 2055215976Sjmallett info.func = __cvmx_error_display; 2056215976Sjmallett info.user_info = (long) 2057215976Sjmallett "ERROR PEMX_INT_SUM(0)[UP_BX]: Received P-TLP for an unknown Bar.\n"; 2058215976Sjmallett fail |= cvmx_error_add(&info); 2059215976Sjmallett 2060215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2061215976Sjmallett info.status_addr = CVMX_PEMX_INT_SUM(0); 2062215976Sjmallett info.status_mask = 1ull<<7 /* un_b1 */; 2063215976Sjmallett info.enable_addr = CVMX_PEMX_INT_ENB(0); 2064215976Sjmallett info.enable_mask = 1ull<<7 /* un_b1 */; 2065215976Sjmallett info.flags = 0; 2066215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2067215976Sjmallett info.group_index = 0; 2068215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2069215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 2070215976Sjmallett info.parent.status_mask = 1ull<<25 /* pem0 */; 2071215976Sjmallett info.func = __cvmx_error_display; 2072215976Sjmallett info.user_info = (long) 2073215976Sjmallett "ERROR PEMX_INT_SUM(0)[UN_B1]: Received N-TLP for Bar1 when bar1 index valid\n" 2074215976Sjmallett " is not set.\n"; 2075215976Sjmallett fail |= cvmx_error_add(&info); 2076215976Sjmallett 2077215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2078215976Sjmallett info.status_addr = CVMX_PEMX_INT_SUM(0); 2079215976Sjmallett info.status_mask = 1ull<<8 /* un_b2 */; 2080215976Sjmallett info.enable_addr = CVMX_PEMX_INT_ENB(0); 2081215976Sjmallett info.enable_mask = 1ull<<8 /* un_b2 */; 2082215976Sjmallett info.flags = 0; 2083215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2084215976Sjmallett info.group_index = 0; 2085215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2086215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 2087215976Sjmallett info.parent.status_mask = 1ull<<25 /* pem0 */; 2088215976Sjmallett info.func = __cvmx_error_display; 2089215976Sjmallett info.user_info = (long) 2090215976Sjmallett "ERROR PEMX_INT_SUM(0)[UN_B2]: Received N-TLP for Bar2 when bar2 is disabled.\n"; 2091215976Sjmallett fail |= cvmx_error_add(&info); 2092215976Sjmallett 2093215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2094215976Sjmallett info.status_addr = CVMX_PEMX_INT_SUM(0); 2095215976Sjmallett info.status_mask = 1ull<<9 /* un_bx */; 2096215976Sjmallett info.enable_addr = CVMX_PEMX_INT_ENB(0); 2097215976Sjmallett info.enable_mask = 1ull<<9 /* un_bx */; 2098215976Sjmallett info.flags = 0; 2099215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2100215976Sjmallett info.group_index = 0; 2101215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2102215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 2103215976Sjmallett info.parent.status_mask = 1ull<<25 /* pem0 */; 2104215976Sjmallett info.func = __cvmx_error_display; 2105215976Sjmallett info.user_info = (long) 2106215976Sjmallett "ERROR PEMX_INT_SUM(0)[UN_BX]: Received N-TLP for an unknown Bar.\n"; 2107215976Sjmallett fail |= cvmx_error_add(&info); 2108215976Sjmallett 2109215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2110215976Sjmallett info.status_addr = CVMX_PEMX_INT_SUM(0); 2111215976Sjmallett info.status_mask = 1ull<<11 /* rdlk */; 2112215976Sjmallett info.enable_addr = CVMX_PEMX_INT_ENB(0); 2113215976Sjmallett info.enable_mask = 1ull<<11 /* rdlk */; 2114215976Sjmallett info.flags = 0; 2115215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2116215976Sjmallett info.group_index = 0; 2117215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2118215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 2119215976Sjmallett info.parent.status_mask = 1ull<<25 /* pem0 */; 2120215976Sjmallett info.func = __cvmx_error_display; 2121215976Sjmallett info.user_info = (long) 2122215976Sjmallett "ERROR PEMX_INT_SUM(0)[RDLK]: Received Read Lock TLP.\n"; 2123215976Sjmallett fail |= cvmx_error_add(&info); 2124215976Sjmallett 2125215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2126215976Sjmallett info.status_addr = CVMX_PEMX_INT_SUM(0); 2127215976Sjmallett info.status_mask = 1ull<<12 /* crs_er */; 2128215976Sjmallett info.enable_addr = CVMX_PEMX_INT_ENB(0); 2129215976Sjmallett info.enable_mask = 1ull<<12 /* crs_er */; 2130215976Sjmallett info.flags = 0; 2131215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2132215976Sjmallett info.group_index = 0; 2133215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2134215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 2135215976Sjmallett info.parent.status_mask = 1ull<<25 /* pem0 */; 2136215976Sjmallett info.func = __cvmx_error_display; 2137215976Sjmallett info.user_info = (long) 2138215976Sjmallett "ERROR PEMX_INT_SUM(0)[CRS_ER]: Had a CRS Timeout when Retries were enabled.\n"; 2139215976Sjmallett fail |= cvmx_error_add(&info); 2140215976Sjmallett 2141215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2142215976Sjmallett info.status_addr = CVMX_PEMX_INT_SUM(0); 2143215976Sjmallett info.status_mask = 1ull<<13 /* crs_dr */; 2144215976Sjmallett info.enable_addr = CVMX_PEMX_INT_ENB(0); 2145215976Sjmallett info.enable_mask = 1ull<<13 /* crs_dr */; 2146215976Sjmallett info.flags = 0; 2147215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2148215976Sjmallett info.group_index = 0; 2149215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2150215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 2151215976Sjmallett info.parent.status_mask = 1ull<<25 /* pem0 */; 2152215976Sjmallett info.func = __cvmx_error_display; 2153215976Sjmallett info.user_info = (long) 2154215976Sjmallett "ERROR PEMX_INT_SUM(0)[CRS_DR]: Had a CRS Timeout when Retries were disabled.\n"; 2155215976Sjmallett fail |= cvmx_error_add(&info); 2156215976Sjmallett 2157215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2158215976Sjmallett info.status_addr = CVMX_PEMX_INT_SUM(0); 2159215976Sjmallett info.status_mask = 0; 2160215976Sjmallett info.enable_addr = 0; 2161215976Sjmallett info.enable_mask = 0; 2162215976Sjmallett info.flags = 0; 2163215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2164215976Sjmallett info.group_index = 0; 2165215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2166215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 2167215976Sjmallett info.parent.status_mask = 1ull<<25 /* pem0 */; 2168215976Sjmallett info.func = __cvmx_error_decode; 2169215976Sjmallett info.user_info = 0; 2170215976Sjmallett fail |= cvmx_error_add(&info); 2171215976Sjmallett 2172215976Sjmallett /* CVMX_PEMX_DBG_INFO(0) */ 2173215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2174215976Sjmallett info.status_addr = CVMX_PEMX_DBG_INFO(0); 2175215976Sjmallett info.status_mask = 1ull<<0 /* spoison */; 2176215976Sjmallett info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0); 2177215976Sjmallett info.enable_mask = 1ull<<0 /* spoison */; 2178215976Sjmallett info.flags = 0; 2179215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2180215976Sjmallett info.group_index = 0; 2181215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2182215976Sjmallett info.parent.status_addr = CVMX_PEMX_INT_SUM(0); 2183215976Sjmallett info.parent.status_mask = 1ull<<10 /* exc */; 2184215976Sjmallett info.func = __cvmx_error_display; 2185215976Sjmallett info.user_info = (long) 2186215976Sjmallett "ERROR PEMX_DBG_INFO(0)[SPOISON]: Poisoned TLP sent\n" 2187215976Sjmallett " peai__client0_tlp_ep & peai__client0_tlp_hv\n"; 2188215976Sjmallett fail |= cvmx_error_add(&info); 2189215976Sjmallett 2190215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2191215976Sjmallett info.status_addr = CVMX_PEMX_DBG_INFO(0); 2192215976Sjmallett info.status_mask = 1ull<<2 /* rtlplle */; 2193215976Sjmallett info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0); 2194215976Sjmallett info.enable_mask = 1ull<<2 /* rtlplle */; 2195215976Sjmallett info.flags = 0; 2196215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2197215976Sjmallett info.group_index = 0; 2198215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2199215976Sjmallett info.parent.status_addr = CVMX_PEMX_INT_SUM(0); 2200215976Sjmallett info.parent.status_mask = 1ull<<10 /* exc */; 2201215976Sjmallett info.func = __cvmx_error_display; 2202215976Sjmallett info.user_info = (long) 2203215976Sjmallett "ERROR PEMX_DBG_INFO(0)[RTLPLLE]: Received TLP has link layer error\n" 2204215976Sjmallett " pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot\n"; 2205215976Sjmallett fail |= cvmx_error_add(&info); 2206215976Sjmallett 2207215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2208215976Sjmallett info.status_addr = CVMX_PEMX_DBG_INFO(0); 2209215976Sjmallett info.status_mask = 1ull<<3 /* recrce */; 2210215976Sjmallett info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0); 2211215976Sjmallett info.enable_mask = 1ull<<3 /* recrce */; 2212215976Sjmallett info.flags = 0; 2213215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2214215976Sjmallett info.group_index = 0; 2215215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2216215976Sjmallett info.parent.status_addr = CVMX_PEMX_INT_SUM(0); 2217215976Sjmallett info.parent.status_mask = 1ull<<10 /* exc */; 2218215976Sjmallett info.func = __cvmx_error_display; 2219215976Sjmallett info.user_info = (long) 2220215976Sjmallett "ERROR PEMX_DBG_INFO(0)[RECRCE]: Received ECRC Error\n" 2221215976Sjmallett " pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot\n"; 2222215976Sjmallett fail |= cvmx_error_add(&info); 2223215976Sjmallett 2224215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2225215976Sjmallett info.status_addr = CVMX_PEMX_DBG_INFO(0); 2226215976Sjmallett info.status_mask = 1ull<<4 /* rpoison */; 2227215976Sjmallett info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0); 2228215976Sjmallett info.enable_mask = 1ull<<4 /* rpoison */; 2229215976Sjmallett info.flags = 0; 2230215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2231215976Sjmallett info.group_index = 0; 2232215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2233215976Sjmallett info.parent.status_addr = CVMX_PEMX_INT_SUM(0); 2234215976Sjmallett info.parent.status_mask = 1ull<<10 /* exc */; 2235215976Sjmallett info.func = __cvmx_error_display; 2236215976Sjmallett info.user_info = (long) 2237215976Sjmallett "ERROR PEMX_DBG_INFO(0)[RPOISON]: Received Poisoned TLP\n" 2238215976Sjmallett " pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv\n"; 2239215976Sjmallett fail |= cvmx_error_add(&info); 2240215976Sjmallett 2241215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2242215976Sjmallett info.status_addr = CVMX_PEMX_DBG_INFO(0); 2243215976Sjmallett info.status_mask = 1ull<<5 /* rcemrc */; 2244215976Sjmallett info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0); 2245215976Sjmallett info.enable_mask = 1ull<<5 /* rcemrc */; 2246215976Sjmallett info.flags = 0; 2247215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2248215976Sjmallett info.group_index = 0; 2249215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2250215976Sjmallett info.parent.status_addr = CVMX_PEMX_INT_SUM(0); 2251215976Sjmallett info.parent.status_mask = 1ull<<10 /* exc */; 2252215976Sjmallett info.func = __cvmx_error_display; 2253215976Sjmallett info.user_info = (long) 2254215976Sjmallett "ERROR PEMX_DBG_INFO(0)[RCEMRC]: Received Correctable Error Message (RC Mode only)\n" 2255215976Sjmallett " pedc_radm_correctable_err\n"; 2256215976Sjmallett fail |= cvmx_error_add(&info); 2257215976Sjmallett 2258215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2259215976Sjmallett info.status_addr = CVMX_PEMX_DBG_INFO(0); 2260215976Sjmallett info.status_mask = 1ull<<6 /* rnfemrc */; 2261215976Sjmallett info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0); 2262215976Sjmallett info.enable_mask = 1ull<<6 /* rnfemrc */; 2263215976Sjmallett info.flags = 0; 2264215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2265215976Sjmallett info.group_index = 0; 2266215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2267215976Sjmallett info.parent.status_addr = CVMX_PEMX_INT_SUM(0); 2268215976Sjmallett info.parent.status_mask = 1ull<<10 /* exc */; 2269215976Sjmallett info.func = __cvmx_error_display; 2270215976Sjmallett info.user_info = (long) 2271215976Sjmallett "ERROR PEMX_DBG_INFO(0)[RNFEMRC]: Received Non-Fatal Error Message (RC Mode only)\n" 2272215976Sjmallett " pedc_radm_nonfatal_err\n"; 2273215976Sjmallett fail |= cvmx_error_add(&info); 2274215976Sjmallett 2275215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2276215976Sjmallett info.status_addr = CVMX_PEMX_DBG_INFO(0); 2277215976Sjmallett info.status_mask = 1ull<<7 /* rfemrc */; 2278215976Sjmallett info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0); 2279215976Sjmallett info.enable_mask = 1ull<<7 /* rfemrc */; 2280215976Sjmallett info.flags = 0; 2281215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2282215976Sjmallett info.group_index = 0; 2283215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2284215976Sjmallett info.parent.status_addr = CVMX_PEMX_INT_SUM(0); 2285215976Sjmallett info.parent.status_mask = 1ull<<10 /* exc */; 2286215976Sjmallett info.func = __cvmx_error_display; 2287215976Sjmallett info.user_info = (long) 2288215976Sjmallett "ERROR PEMX_DBG_INFO(0)[RFEMRC]: Received Fatal Error Message (RC Mode only)\n" 2289215976Sjmallett " pedc_radm_fatal_err\n" 2290215976Sjmallett " Bit set when a message with ERR_FATAL is set.\n"; 2291215976Sjmallett fail |= cvmx_error_add(&info); 2292215976Sjmallett 2293215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2294215976Sjmallett info.status_addr = CVMX_PEMX_DBG_INFO(0); 2295215976Sjmallett info.status_mask = 1ull<<8 /* rpmerc */; 2296215976Sjmallett info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0); 2297215976Sjmallett info.enable_mask = 1ull<<8 /* rpmerc */; 2298215976Sjmallett info.flags = 0; 2299215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2300215976Sjmallett info.group_index = 0; 2301215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2302215976Sjmallett info.parent.status_addr = CVMX_PEMX_INT_SUM(0); 2303215976Sjmallett info.parent.status_mask = 1ull<<10 /* exc */; 2304215976Sjmallett info.func = __cvmx_error_display; 2305215976Sjmallett info.user_info = (long) 2306215976Sjmallett "ERROR PEMX_DBG_INFO(0)[RPMERC]: Received PME Message (RC Mode only)\n" 2307215976Sjmallett " pedc_radm_pm_pme\n"; 2308215976Sjmallett fail |= cvmx_error_add(&info); 2309215976Sjmallett 2310215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2311215976Sjmallett info.status_addr = CVMX_PEMX_DBG_INFO(0); 2312215976Sjmallett info.status_mask = 1ull<<9 /* rptamrc */; 2313215976Sjmallett info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0); 2314215976Sjmallett info.enable_mask = 1ull<<9 /* rptamrc */; 2315215976Sjmallett info.flags = 0; 2316215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2317215976Sjmallett info.group_index = 0; 2318215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2319215976Sjmallett info.parent.status_addr = CVMX_PEMX_INT_SUM(0); 2320215976Sjmallett info.parent.status_mask = 1ull<<10 /* exc */; 2321215976Sjmallett info.func = __cvmx_error_display; 2322215976Sjmallett info.user_info = (long) 2323215976Sjmallett "ERROR PEMX_DBG_INFO(0)[RPTAMRC]: Received PME Turnoff Acknowledge Message\n" 2324215976Sjmallett " (RC Mode only)\n" 2325215976Sjmallett " pedc_radm_pm_to_ack\n"; 2326215976Sjmallett fail |= cvmx_error_add(&info); 2327215976Sjmallett 2328215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2329215976Sjmallett info.status_addr = CVMX_PEMX_DBG_INFO(0); 2330215976Sjmallett info.status_mask = 1ull<<10 /* rumep */; 2331215976Sjmallett info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0); 2332215976Sjmallett info.enable_mask = 1ull<<10 /* rumep */; 2333215976Sjmallett info.flags = 0; 2334215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2335215976Sjmallett info.group_index = 0; 2336215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2337215976Sjmallett info.parent.status_addr = CVMX_PEMX_INT_SUM(0); 2338215976Sjmallett info.parent.status_mask = 1ull<<10 /* exc */; 2339215976Sjmallett info.func = __cvmx_error_display; 2340215976Sjmallett info.user_info = (long) 2341215976Sjmallett "ERROR PEMX_DBG_INFO(0)[RUMEP]: Received Unlock Message (EP Mode Only)\n" 2342215976Sjmallett " pedc_radm_msg_unlock\n"; 2343215976Sjmallett fail |= cvmx_error_add(&info); 2344215976Sjmallett 2345215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2346215976Sjmallett info.status_addr = CVMX_PEMX_DBG_INFO(0); 2347215976Sjmallett info.status_mask = 1ull<<11 /* rvdm */; 2348215976Sjmallett info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0); 2349215976Sjmallett info.enable_mask = 1ull<<11 /* rvdm */; 2350215976Sjmallett info.flags = 0; 2351215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2352215976Sjmallett info.group_index = 0; 2353215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2354215976Sjmallett info.parent.status_addr = CVMX_PEMX_INT_SUM(0); 2355215976Sjmallett info.parent.status_mask = 1ull<<10 /* exc */; 2356215976Sjmallett info.func = __cvmx_error_display; 2357215976Sjmallett info.user_info = (long) 2358215976Sjmallett "ERROR PEMX_DBG_INFO(0)[RVDM]: Received Vendor-Defined Message\n" 2359215976Sjmallett " pedc_radm_vendor_msg\n"; 2360215976Sjmallett fail |= cvmx_error_add(&info); 2361215976Sjmallett 2362215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2363215976Sjmallett info.status_addr = CVMX_PEMX_DBG_INFO(0); 2364215976Sjmallett info.status_mask = 1ull<<12 /* acto */; 2365215976Sjmallett info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0); 2366215976Sjmallett info.enable_mask = 1ull<<12 /* acto */; 2367215976Sjmallett info.flags = 0; 2368215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2369215976Sjmallett info.group_index = 0; 2370215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2371215976Sjmallett info.parent.status_addr = CVMX_PEMX_INT_SUM(0); 2372215976Sjmallett info.parent.status_mask = 1ull<<10 /* exc */; 2373215976Sjmallett info.func = __cvmx_error_display; 2374215976Sjmallett info.user_info = (long) 2375215976Sjmallett "ERROR PEMX_DBG_INFO(0)[ACTO]: A Completion Timeout Occured\n" 2376215976Sjmallett " pedc_radm_cpl_timeout\n"; 2377215976Sjmallett fail |= cvmx_error_add(&info); 2378215976Sjmallett 2379215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2380215976Sjmallett info.status_addr = CVMX_PEMX_DBG_INFO(0); 2381215976Sjmallett info.status_mask = 1ull<<13 /* rte */; 2382215976Sjmallett info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0); 2383215976Sjmallett info.enable_mask = 1ull<<13 /* rte */; 2384215976Sjmallett info.flags = 0; 2385215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2386215976Sjmallett info.group_index = 0; 2387215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2388215976Sjmallett info.parent.status_addr = CVMX_PEMX_INT_SUM(0); 2389215976Sjmallett info.parent.status_mask = 1ull<<10 /* exc */; 2390215976Sjmallett info.func = __cvmx_error_display; 2391215976Sjmallett info.user_info = (long) 2392215976Sjmallett "ERROR PEMX_DBG_INFO(0)[RTE]: Replay Timer Expired\n" 2393215976Sjmallett " xdlh_replay_timeout_err\n" 2394215976Sjmallett " This bit is set when the REPLAY_TIMER expires in\n" 2395215976Sjmallett " the PCIE core. The probability of this bit being\n" 2396215976Sjmallett " set will increase with the traffic load.\n"; 2397215976Sjmallett fail |= cvmx_error_add(&info); 2398215976Sjmallett 2399215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2400215976Sjmallett info.status_addr = CVMX_PEMX_DBG_INFO(0); 2401215976Sjmallett info.status_mask = 1ull<<14 /* mre */; 2402215976Sjmallett info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0); 2403215976Sjmallett info.enable_mask = 1ull<<14 /* mre */; 2404215976Sjmallett info.flags = 0; 2405215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2406215976Sjmallett info.group_index = 0; 2407215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2408215976Sjmallett info.parent.status_addr = CVMX_PEMX_INT_SUM(0); 2409215976Sjmallett info.parent.status_mask = 1ull<<10 /* exc */; 2410215976Sjmallett info.func = __cvmx_error_display; 2411215976Sjmallett info.user_info = (long) 2412215976Sjmallett "ERROR PEMX_DBG_INFO(0)[MRE]: Max Retries Exceeded\n" 2413215976Sjmallett " xdlh_replay_num_rlover_err\n"; 2414215976Sjmallett fail |= cvmx_error_add(&info); 2415215976Sjmallett 2416215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2417215976Sjmallett info.status_addr = CVMX_PEMX_DBG_INFO(0); 2418215976Sjmallett info.status_mask = 1ull<<15 /* rdwdle */; 2419215976Sjmallett info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0); 2420215976Sjmallett info.enable_mask = 1ull<<15 /* rdwdle */; 2421215976Sjmallett info.flags = 0; 2422215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2423215976Sjmallett info.group_index = 0; 2424215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2425215976Sjmallett info.parent.status_addr = CVMX_PEMX_INT_SUM(0); 2426215976Sjmallett info.parent.status_mask = 1ull<<10 /* exc */; 2427215976Sjmallett info.func = __cvmx_error_display; 2428215976Sjmallett info.user_info = (long) 2429215976Sjmallett "ERROR PEMX_DBG_INFO(0)[RDWDLE]: Received DLLP with DataLink Layer Error\n" 2430215976Sjmallett " rdlh_bad_dllp_err\n"; 2431215976Sjmallett fail |= cvmx_error_add(&info); 2432215976Sjmallett 2433215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2434215976Sjmallett info.status_addr = CVMX_PEMX_DBG_INFO(0); 2435215976Sjmallett info.status_mask = 1ull<<16 /* rtwdle */; 2436215976Sjmallett info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0); 2437215976Sjmallett info.enable_mask = 1ull<<16 /* rtwdle */; 2438215976Sjmallett info.flags = 0; 2439215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2440215976Sjmallett info.group_index = 0; 2441215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2442215976Sjmallett info.parent.status_addr = CVMX_PEMX_INT_SUM(0); 2443215976Sjmallett info.parent.status_mask = 1ull<<10 /* exc */; 2444215976Sjmallett info.func = __cvmx_error_display; 2445215976Sjmallett info.user_info = (long) 2446215976Sjmallett "ERROR PEMX_DBG_INFO(0)[RTWDLE]: Received TLP with DataLink Layer Error\n" 2447215976Sjmallett " rdlh_bad_tlp_err\n"; 2448215976Sjmallett fail |= cvmx_error_add(&info); 2449215976Sjmallett 2450215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2451215976Sjmallett info.status_addr = CVMX_PEMX_DBG_INFO(0); 2452215976Sjmallett info.status_mask = 1ull<<17 /* dpeoosd */; 2453215976Sjmallett info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0); 2454215976Sjmallett info.enable_mask = 1ull<<17 /* dpeoosd */; 2455215976Sjmallett info.flags = 0; 2456215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2457215976Sjmallett info.group_index = 0; 2458215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2459215976Sjmallett info.parent.status_addr = CVMX_PEMX_INT_SUM(0); 2460215976Sjmallett info.parent.status_mask = 1ull<<10 /* exc */; 2461215976Sjmallett info.func = __cvmx_error_display; 2462215976Sjmallett info.user_info = (long) 2463215976Sjmallett "ERROR PEMX_DBG_INFO(0)[DPEOOSD]: DLLP protocol error (out of sequence DLLP)\n" 2464215976Sjmallett " rdlh_prot_err\n"; 2465215976Sjmallett fail |= cvmx_error_add(&info); 2466215976Sjmallett 2467215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2468215976Sjmallett info.status_addr = CVMX_PEMX_DBG_INFO(0); 2469215976Sjmallett info.status_mask = 1ull<<18 /* fcpvwt */; 2470215976Sjmallett info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0); 2471215976Sjmallett info.enable_mask = 1ull<<18 /* fcpvwt */; 2472215976Sjmallett info.flags = 0; 2473215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2474215976Sjmallett info.group_index = 0; 2475215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2476215976Sjmallett info.parent.status_addr = CVMX_PEMX_INT_SUM(0); 2477215976Sjmallett info.parent.status_mask = 1ull<<10 /* exc */; 2478215976Sjmallett info.func = __cvmx_error_display; 2479215976Sjmallett info.user_info = (long) 2480215976Sjmallett "ERROR PEMX_DBG_INFO(0)[FCPVWT]: Flow Control Protocol Violation (Watchdog Timer)\n" 2481215976Sjmallett " rtlh_fc_prot_err\n"; 2482215976Sjmallett fail |= cvmx_error_add(&info); 2483215976Sjmallett 2484215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2485215976Sjmallett info.status_addr = CVMX_PEMX_DBG_INFO(0); 2486215976Sjmallett info.status_mask = 1ull<<19 /* rpe */; 2487215976Sjmallett info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0); 2488215976Sjmallett info.enable_mask = 1ull<<19 /* rpe */; 2489215976Sjmallett info.flags = 0; 2490215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2491215976Sjmallett info.group_index = 0; 2492215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2493215976Sjmallett info.parent.status_addr = CVMX_PEMX_INT_SUM(0); 2494215976Sjmallett info.parent.status_mask = 1ull<<10 /* exc */; 2495215976Sjmallett info.func = __cvmx_error_display; 2496215976Sjmallett info.user_info = (long) 2497215976Sjmallett "ERROR PEMX_DBG_INFO(0)[RPE]: When the PHY reports 8B/10B decode error\n" 2498215976Sjmallett " (RxStatus = 3b100) or disparity error\n" 2499215976Sjmallett " (RxStatus = 3b111), the signal rmlh_rcvd_err will\n" 2500215976Sjmallett " be asserted.\n" 2501215976Sjmallett " rmlh_rcvd_err\n"; 2502215976Sjmallett fail |= cvmx_error_add(&info); 2503215976Sjmallett 2504215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2505215976Sjmallett info.status_addr = CVMX_PEMX_DBG_INFO(0); 2506215976Sjmallett info.status_mask = 1ull<<20 /* fcuv */; 2507215976Sjmallett info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0); 2508215976Sjmallett info.enable_mask = 1ull<<20 /* fcuv */; 2509215976Sjmallett info.flags = 0; 2510215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2511215976Sjmallett info.group_index = 0; 2512215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2513215976Sjmallett info.parent.status_addr = CVMX_PEMX_INT_SUM(0); 2514215976Sjmallett info.parent.status_mask = 1ull<<10 /* exc */; 2515215976Sjmallett info.func = __cvmx_error_display; 2516215976Sjmallett info.user_info = (long) 2517215976Sjmallett "ERROR PEMX_DBG_INFO(0)[FCUV]: Flow Control Update Violation (opt. checks)\n" 2518215976Sjmallett " int_xadm_fc_prot_err\n"; 2519215976Sjmallett fail |= cvmx_error_add(&info); 2520215976Sjmallett 2521215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2522215976Sjmallett info.status_addr = CVMX_PEMX_DBG_INFO(0); 2523215976Sjmallett info.status_mask = 1ull<<21 /* rqo */; 2524215976Sjmallett info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0); 2525215976Sjmallett info.enable_mask = 1ull<<21 /* rqo */; 2526215976Sjmallett info.flags = 0; 2527215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2528215976Sjmallett info.group_index = 0; 2529215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2530215976Sjmallett info.parent.status_addr = CVMX_PEMX_INT_SUM(0); 2531215976Sjmallett info.parent.status_mask = 1ull<<10 /* exc */; 2532215976Sjmallett info.func = __cvmx_error_display; 2533215976Sjmallett info.user_info = (long) 2534215976Sjmallett "ERROR PEMX_DBG_INFO(0)[RQO]: Receive queue overflow. Normally happens only when\n" 2535215976Sjmallett " flow control advertisements are ignored\n" 2536215976Sjmallett " radm_qoverflow\n"; 2537215976Sjmallett fail |= cvmx_error_add(&info); 2538215976Sjmallett 2539215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2540215976Sjmallett info.status_addr = CVMX_PEMX_DBG_INFO(0); 2541215976Sjmallett info.status_mask = 1ull<<22 /* rauc */; 2542215976Sjmallett info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0); 2543215976Sjmallett info.enable_mask = 1ull<<22 /* rauc */; 2544215976Sjmallett info.flags = 0; 2545215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2546215976Sjmallett info.group_index = 0; 2547215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2548215976Sjmallett info.parent.status_addr = CVMX_PEMX_INT_SUM(0); 2549215976Sjmallett info.parent.status_mask = 1ull<<10 /* exc */; 2550215976Sjmallett info.func = __cvmx_error_display; 2551215976Sjmallett info.user_info = (long) 2552215976Sjmallett "ERROR PEMX_DBG_INFO(0)[RAUC]: Received an unexpected completion\n" 2553215976Sjmallett " radm_unexp_cpl_err\n"; 2554215976Sjmallett fail |= cvmx_error_add(&info); 2555215976Sjmallett 2556215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2557215976Sjmallett info.status_addr = CVMX_PEMX_DBG_INFO(0); 2558215976Sjmallett info.status_mask = 1ull<<23 /* racur */; 2559215976Sjmallett info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0); 2560215976Sjmallett info.enable_mask = 1ull<<23 /* racur */; 2561215976Sjmallett info.flags = 0; 2562215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2563215976Sjmallett info.group_index = 0; 2564215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2565215976Sjmallett info.parent.status_addr = CVMX_PEMX_INT_SUM(0); 2566215976Sjmallett info.parent.status_mask = 1ull<<10 /* exc */; 2567215976Sjmallett info.func = __cvmx_error_display; 2568215976Sjmallett info.user_info = (long) 2569215976Sjmallett "ERROR PEMX_DBG_INFO(0)[RACUR]: Received a completion with UR status\n" 2570215976Sjmallett " radm_rcvd_cpl_ur\n"; 2571215976Sjmallett fail |= cvmx_error_add(&info); 2572215976Sjmallett 2573215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2574215976Sjmallett info.status_addr = CVMX_PEMX_DBG_INFO(0); 2575215976Sjmallett info.status_mask = 1ull<<24 /* racca */; 2576215976Sjmallett info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0); 2577215976Sjmallett info.enable_mask = 1ull<<24 /* racca */; 2578215976Sjmallett info.flags = 0; 2579215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2580215976Sjmallett info.group_index = 0; 2581215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2582215976Sjmallett info.parent.status_addr = CVMX_PEMX_INT_SUM(0); 2583215976Sjmallett info.parent.status_mask = 1ull<<10 /* exc */; 2584215976Sjmallett info.func = __cvmx_error_display; 2585215976Sjmallett info.user_info = (long) 2586215976Sjmallett "ERROR PEMX_DBG_INFO(0)[RACCA]: Received a completion with CA status\n" 2587215976Sjmallett " radm_rcvd_cpl_ca\n"; 2588215976Sjmallett fail |= cvmx_error_add(&info); 2589215976Sjmallett 2590215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2591215976Sjmallett info.status_addr = CVMX_PEMX_DBG_INFO(0); 2592215976Sjmallett info.status_mask = 1ull<<25 /* caar */; 2593215976Sjmallett info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0); 2594215976Sjmallett info.enable_mask = 1ull<<25 /* caar */; 2595215976Sjmallett info.flags = 0; 2596215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2597215976Sjmallett info.group_index = 0; 2598215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2599215976Sjmallett info.parent.status_addr = CVMX_PEMX_INT_SUM(0); 2600215976Sjmallett info.parent.status_mask = 1ull<<10 /* exc */; 2601215976Sjmallett info.func = __cvmx_error_display; 2602215976Sjmallett info.user_info = (long) 2603215976Sjmallett "ERROR PEMX_DBG_INFO(0)[CAAR]: Completer aborted a request\n" 2604215976Sjmallett " radm_rcvd_ca_req\n" 2605215976Sjmallett " This bit will never be set because Octeon does\n" 2606215976Sjmallett " not generate Completer Aborts.\n"; 2607215976Sjmallett fail |= cvmx_error_add(&info); 2608215976Sjmallett 2609215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2610215976Sjmallett info.status_addr = CVMX_PEMX_DBG_INFO(0); 2611215976Sjmallett info.status_mask = 1ull<<26 /* rarwdns */; 2612215976Sjmallett info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0); 2613215976Sjmallett info.enable_mask = 1ull<<26 /* rarwdns */; 2614215976Sjmallett info.flags = 0; 2615215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2616215976Sjmallett info.group_index = 0; 2617215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2618215976Sjmallett info.parent.status_addr = CVMX_PEMX_INT_SUM(0); 2619215976Sjmallett info.parent.status_mask = 1ull<<10 /* exc */; 2620215976Sjmallett info.func = __cvmx_error_display; 2621215976Sjmallett info.user_info = (long) 2622215976Sjmallett "ERROR PEMX_DBG_INFO(0)[RARWDNS]: Recieved a request which device does not support\n" 2623215976Sjmallett " radm_rcvd_ur_req\n"; 2624215976Sjmallett fail |= cvmx_error_add(&info); 2625215976Sjmallett 2626215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2627215976Sjmallett info.status_addr = CVMX_PEMX_DBG_INFO(0); 2628215976Sjmallett info.status_mask = 1ull<<27 /* ramtlp */; 2629215976Sjmallett info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0); 2630215976Sjmallett info.enable_mask = 1ull<<27 /* ramtlp */; 2631215976Sjmallett info.flags = 0; 2632215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2633215976Sjmallett info.group_index = 0; 2634215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2635215976Sjmallett info.parent.status_addr = CVMX_PEMX_INT_SUM(0); 2636215976Sjmallett info.parent.status_mask = 1ull<<10 /* exc */; 2637215976Sjmallett info.func = __cvmx_error_display; 2638215976Sjmallett info.user_info = (long) 2639215976Sjmallett "ERROR PEMX_DBG_INFO(0)[RAMTLP]: Received a malformed TLP\n" 2640215976Sjmallett " radm_mlf_tlp_err\n"; 2641215976Sjmallett fail |= cvmx_error_add(&info); 2642215976Sjmallett 2643215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2644215976Sjmallett info.status_addr = CVMX_PEMX_DBG_INFO(0); 2645215976Sjmallett info.status_mask = 1ull<<28 /* racpp */; 2646215976Sjmallett info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0); 2647215976Sjmallett info.enable_mask = 1ull<<28 /* racpp */; 2648215976Sjmallett info.flags = 0; 2649215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2650215976Sjmallett info.group_index = 0; 2651215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2652215976Sjmallett info.parent.status_addr = CVMX_PEMX_INT_SUM(0); 2653215976Sjmallett info.parent.status_mask = 1ull<<10 /* exc */; 2654215976Sjmallett info.func = __cvmx_error_display; 2655215976Sjmallett info.user_info = (long) 2656215976Sjmallett "ERROR PEMX_DBG_INFO(0)[RACPP]: Received a completion with poisoned payload\n" 2657215976Sjmallett " radm_rcvd_cpl_poisoned\n"; 2658215976Sjmallett fail |= cvmx_error_add(&info); 2659215976Sjmallett 2660215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2661215976Sjmallett info.status_addr = CVMX_PEMX_DBG_INFO(0); 2662215976Sjmallett info.status_mask = 1ull<<29 /* rawwpp */; 2663215976Sjmallett info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0); 2664215976Sjmallett info.enable_mask = 1ull<<29 /* rawwpp */; 2665215976Sjmallett info.flags = 0; 2666215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2667215976Sjmallett info.group_index = 0; 2668215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2669215976Sjmallett info.parent.status_addr = CVMX_PEMX_INT_SUM(0); 2670215976Sjmallett info.parent.status_mask = 1ull<<10 /* exc */; 2671215976Sjmallett info.func = __cvmx_error_display; 2672215976Sjmallett info.user_info = (long) 2673215976Sjmallett "ERROR PEMX_DBG_INFO(0)[RAWWPP]: Received a write with poisoned payload\n" 2674215976Sjmallett " radm_rcvd_wreq_poisoned\n"; 2675215976Sjmallett fail |= cvmx_error_add(&info); 2676215976Sjmallett 2677215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2678215976Sjmallett info.status_addr = CVMX_PEMX_DBG_INFO(0); 2679215976Sjmallett info.status_mask = 1ull<<30 /* ecrc_e */; 2680215976Sjmallett info.enable_addr = CVMX_PEMX_DBG_INFO_EN(0); 2681215976Sjmallett info.enable_mask = 1ull<<30 /* ecrc_e */; 2682215976Sjmallett info.flags = 0; 2683215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2684215976Sjmallett info.group_index = 0; 2685215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2686215976Sjmallett info.parent.status_addr = CVMX_PEMX_INT_SUM(0); 2687215976Sjmallett info.parent.status_mask = 1ull<<10 /* exc */; 2688215976Sjmallett info.func = __cvmx_error_display; 2689215976Sjmallett info.user_info = (long) 2690215976Sjmallett "ERROR PEMX_DBG_INFO(0)[ECRC_E]: Received a ECRC error.\n" 2691215976Sjmallett " radm_ecrc_err\n"; 2692215976Sjmallett fail |= cvmx_error_add(&info); 2693215976Sjmallett 2694215976Sjmallett /* CVMX_PEMX_INT_SUM(1) */ 2695215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2696215976Sjmallett info.status_addr = CVMX_PEMX_INT_SUM(1); 2697215976Sjmallett info.status_mask = 1ull<<1 /* se */; 2698215976Sjmallett info.enable_addr = CVMX_PEMX_INT_ENB(1); 2699215976Sjmallett info.enable_mask = 1ull<<1 /* se */; 2700215976Sjmallett info.flags = 0; 2701215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2702215976Sjmallett info.group_index = 1; 2703215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2704215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 2705215976Sjmallett info.parent.status_mask = 1ull<<26 /* pem1 */; 2706215976Sjmallett info.func = __cvmx_error_display; 2707215976Sjmallett info.user_info = (long) 2708215976Sjmallett "ERROR PEMX_INT_SUM(1)[SE]: System Error, RC Mode Only.\n" 2709215976Sjmallett " (cfg_sys_err_rc)\n"; 2710215976Sjmallett fail |= cvmx_error_add(&info); 2711215976Sjmallett 2712215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2713215976Sjmallett info.status_addr = CVMX_PEMX_INT_SUM(1); 2714215976Sjmallett info.status_mask = 1ull<<4 /* up_b1 */; 2715215976Sjmallett info.enable_addr = CVMX_PEMX_INT_ENB(1); 2716215976Sjmallett info.enable_mask = 1ull<<4 /* up_b1 */; 2717215976Sjmallett info.flags = 0; 2718215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2719215976Sjmallett info.group_index = 1; 2720215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2721215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 2722215976Sjmallett info.parent.status_mask = 1ull<<26 /* pem1 */; 2723215976Sjmallett info.func = __cvmx_error_display; 2724215976Sjmallett info.user_info = (long) 2725215976Sjmallett "ERROR PEMX_INT_SUM(1)[UP_B1]: Received P-TLP for Bar1 when bar1 index valid\n" 2726215976Sjmallett " is not set.\n"; 2727215976Sjmallett fail |= cvmx_error_add(&info); 2728215976Sjmallett 2729215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2730215976Sjmallett info.status_addr = CVMX_PEMX_INT_SUM(1); 2731215976Sjmallett info.status_mask = 1ull<<5 /* up_b2 */; 2732215976Sjmallett info.enable_addr = CVMX_PEMX_INT_ENB(1); 2733215976Sjmallett info.enable_mask = 1ull<<5 /* up_b2 */; 2734215976Sjmallett info.flags = 0; 2735215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2736215976Sjmallett info.group_index = 1; 2737215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2738215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 2739215976Sjmallett info.parent.status_mask = 1ull<<26 /* pem1 */; 2740215976Sjmallett info.func = __cvmx_error_display; 2741215976Sjmallett info.user_info = (long) 2742215976Sjmallett "ERROR PEMX_INT_SUM(1)[UP_B2]: Received P-TLP for Bar2 when bar2 is disabeld.\n"; 2743215976Sjmallett fail |= cvmx_error_add(&info); 2744215976Sjmallett 2745215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2746215976Sjmallett info.status_addr = CVMX_PEMX_INT_SUM(1); 2747215976Sjmallett info.status_mask = 1ull<<6 /* up_bx */; 2748215976Sjmallett info.enable_addr = CVMX_PEMX_INT_ENB(1); 2749215976Sjmallett info.enable_mask = 1ull<<6 /* up_bx */; 2750215976Sjmallett info.flags = 0; 2751215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2752215976Sjmallett info.group_index = 1; 2753215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2754215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 2755215976Sjmallett info.parent.status_mask = 1ull<<26 /* pem1 */; 2756215976Sjmallett info.func = __cvmx_error_display; 2757215976Sjmallett info.user_info = (long) 2758215976Sjmallett "ERROR PEMX_INT_SUM(1)[UP_BX]: Received P-TLP for an unknown Bar.\n"; 2759215976Sjmallett fail |= cvmx_error_add(&info); 2760215976Sjmallett 2761215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2762215976Sjmallett info.status_addr = CVMX_PEMX_INT_SUM(1); 2763215976Sjmallett info.status_mask = 1ull<<7 /* un_b1 */; 2764215976Sjmallett info.enable_addr = CVMX_PEMX_INT_ENB(1); 2765215976Sjmallett info.enable_mask = 1ull<<7 /* un_b1 */; 2766215976Sjmallett info.flags = 0; 2767215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2768215976Sjmallett info.group_index = 1; 2769215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2770215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 2771215976Sjmallett info.parent.status_mask = 1ull<<26 /* pem1 */; 2772215976Sjmallett info.func = __cvmx_error_display; 2773215976Sjmallett info.user_info = (long) 2774215976Sjmallett "ERROR PEMX_INT_SUM(1)[UN_B1]: Received N-TLP for Bar1 when bar1 index valid\n" 2775215976Sjmallett " is not set.\n"; 2776215976Sjmallett fail |= cvmx_error_add(&info); 2777215976Sjmallett 2778215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2779215976Sjmallett info.status_addr = CVMX_PEMX_INT_SUM(1); 2780215976Sjmallett info.status_mask = 1ull<<8 /* un_b2 */; 2781215976Sjmallett info.enable_addr = CVMX_PEMX_INT_ENB(1); 2782215976Sjmallett info.enable_mask = 1ull<<8 /* un_b2 */; 2783215976Sjmallett info.flags = 0; 2784215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2785215976Sjmallett info.group_index = 1; 2786215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2787215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 2788215976Sjmallett info.parent.status_mask = 1ull<<26 /* pem1 */; 2789215976Sjmallett info.func = __cvmx_error_display; 2790215976Sjmallett info.user_info = (long) 2791215976Sjmallett "ERROR PEMX_INT_SUM(1)[UN_B2]: Received N-TLP for Bar2 when bar2 is disabled.\n"; 2792215976Sjmallett fail |= cvmx_error_add(&info); 2793215976Sjmallett 2794215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2795215976Sjmallett info.status_addr = CVMX_PEMX_INT_SUM(1); 2796215976Sjmallett info.status_mask = 1ull<<9 /* un_bx */; 2797215976Sjmallett info.enable_addr = CVMX_PEMX_INT_ENB(1); 2798215976Sjmallett info.enable_mask = 1ull<<9 /* un_bx */; 2799215976Sjmallett info.flags = 0; 2800215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2801215976Sjmallett info.group_index = 1; 2802215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2803215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 2804215976Sjmallett info.parent.status_mask = 1ull<<26 /* pem1 */; 2805215976Sjmallett info.func = __cvmx_error_display; 2806215976Sjmallett info.user_info = (long) 2807215976Sjmallett "ERROR PEMX_INT_SUM(1)[UN_BX]: Received N-TLP for an unknown Bar.\n"; 2808215976Sjmallett fail |= cvmx_error_add(&info); 2809215976Sjmallett 2810215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2811215976Sjmallett info.status_addr = CVMX_PEMX_INT_SUM(1); 2812215976Sjmallett info.status_mask = 1ull<<11 /* rdlk */; 2813215976Sjmallett info.enable_addr = CVMX_PEMX_INT_ENB(1); 2814215976Sjmallett info.enable_mask = 1ull<<11 /* rdlk */; 2815215976Sjmallett info.flags = 0; 2816215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2817215976Sjmallett info.group_index = 1; 2818215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2819215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 2820215976Sjmallett info.parent.status_mask = 1ull<<26 /* pem1 */; 2821215976Sjmallett info.func = __cvmx_error_display; 2822215976Sjmallett info.user_info = (long) 2823215976Sjmallett "ERROR PEMX_INT_SUM(1)[RDLK]: Received Read Lock TLP.\n"; 2824215976Sjmallett fail |= cvmx_error_add(&info); 2825215976Sjmallett 2826215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2827215976Sjmallett info.status_addr = CVMX_PEMX_INT_SUM(1); 2828215976Sjmallett info.status_mask = 1ull<<12 /* crs_er */; 2829215976Sjmallett info.enable_addr = CVMX_PEMX_INT_ENB(1); 2830215976Sjmallett info.enable_mask = 1ull<<12 /* crs_er */; 2831215976Sjmallett info.flags = 0; 2832215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2833215976Sjmallett info.group_index = 1; 2834215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2835215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 2836215976Sjmallett info.parent.status_mask = 1ull<<26 /* pem1 */; 2837215976Sjmallett info.func = __cvmx_error_display; 2838215976Sjmallett info.user_info = (long) 2839215976Sjmallett "ERROR PEMX_INT_SUM(1)[CRS_ER]: Had a CRS Timeout when Retries were enabled.\n"; 2840215976Sjmallett fail |= cvmx_error_add(&info); 2841215976Sjmallett 2842215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2843215976Sjmallett info.status_addr = CVMX_PEMX_INT_SUM(1); 2844215976Sjmallett info.status_mask = 1ull<<13 /* crs_dr */; 2845215976Sjmallett info.enable_addr = CVMX_PEMX_INT_ENB(1); 2846215976Sjmallett info.enable_mask = 1ull<<13 /* crs_dr */; 2847215976Sjmallett info.flags = 0; 2848215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2849215976Sjmallett info.group_index = 1; 2850215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2851215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 2852215976Sjmallett info.parent.status_mask = 1ull<<26 /* pem1 */; 2853215976Sjmallett info.func = __cvmx_error_display; 2854215976Sjmallett info.user_info = (long) 2855215976Sjmallett "ERROR PEMX_INT_SUM(1)[CRS_DR]: Had a CRS Timeout when Retries were disabled.\n"; 2856215976Sjmallett fail |= cvmx_error_add(&info); 2857215976Sjmallett 2858215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2859215976Sjmallett info.status_addr = CVMX_PEMX_INT_SUM(1); 2860215976Sjmallett info.status_mask = 0; 2861215976Sjmallett info.enable_addr = 0; 2862215976Sjmallett info.enable_mask = 0; 2863215976Sjmallett info.flags = 0; 2864215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 2865215976Sjmallett info.group_index = 0; 2866215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2867215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 2868215976Sjmallett info.parent.status_mask = 1ull<<26 /* pem1 */; 2869215976Sjmallett info.func = __cvmx_error_decode; 2870215976Sjmallett info.user_info = 0; 2871215976Sjmallett fail |= cvmx_error_add(&info); 2872215976Sjmallett 2873215976Sjmallett /* CVMX_PEMX_DBG_INFO(1) */ 2874215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2875215976Sjmallett info.status_addr = CVMX_PEMX_DBG_INFO(1); 2876215976Sjmallett info.status_mask = 1ull<<0 /* spoison */; 2877215976Sjmallett info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1); 2878215976Sjmallett info.enable_mask = 1ull<<0 /* spoison */; 2879215976Sjmallett info.flags = 0; 2880215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2881215976Sjmallett info.group_index = 1; 2882215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2883215976Sjmallett info.parent.status_addr = CVMX_PEMX_INT_SUM(1); 2884215976Sjmallett info.parent.status_mask = 1ull<<10 /* exc */; 2885215976Sjmallett info.func = __cvmx_error_display; 2886215976Sjmallett info.user_info = (long) 2887215976Sjmallett "ERROR PEMX_DBG_INFO(1)[SPOISON]: Poisoned TLP sent\n" 2888215976Sjmallett " peai__client0_tlp_ep & peai__client0_tlp_hv\n"; 2889215976Sjmallett fail |= cvmx_error_add(&info); 2890215976Sjmallett 2891215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2892215976Sjmallett info.status_addr = CVMX_PEMX_DBG_INFO(1); 2893215976Sjmallett info.status_mask = 1ull<<2 /* rtlplle */; 2894215976Sjmallett info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1); 2895215976Sjmallett info.enable_mask = 1ull<<2 /* rtlplle */; 2896215976Sjmallett info.flags = 0; 2897215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2898215976Sjmallett info.group_index = 1; 2899215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2900215976Sjmallett info.parent.status_addr = CVMX_PEMX_INT_SUM(1); 2901215976Sjmallett info.parent.status_mask = 1ull<<10 /* exc */; 2902215976Sjmallett info.func = __cvmx_error_display; 2903215976Sjmallett info.user_info = (long) 2904215976Sjmallett "ERROR PEMX_DBG_INFO(1)[RTLPLLE]: Received TLP has link layer error\n" 2905215976Sjmallett " pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot\n"; 2906215976Sjmallett fail |= cvmx_error_add(&info); 2907215976Sjmallett 2908215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2909215976Sjmallett info.status_addr = CVMX_PEMX_DBG_INFO(1); 2910215976Sjmallett info.status_mask = 1ull<<3 /* recrce */; 2911215976Sjmallett info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1); 2912215976Sjmallett info.enable_mask = 1ull<<3 /* recrce */; 2913215976Sjmallett info.flags = 0; 2914215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2915215976Sjmallett info.group_index = 1; 2916215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2917215976Sjmallett info.parent.status_addr = CVMX_PEMX_INT_SUM(1); 2918215976Sjmallett info.parent.status_mask = 1ull<<10 /* exc */; 2919215976Sjmallett info.func = __cvmx_error_display; 2920215976Sjmallett info.user_info = (long) 2921215976Sjmallett "ERROR PEMX_DBG_INFO(1)[RECRCE]: Received ECRC Error\n" 2922215976Sjmallett " pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot\n"; 2923215976Sjmallett fail |= cvmx_error_add(&info); 2924215976Sjmallett 2925215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2926215976Sjmallett info.status_addr = CVMX_PEMX_DBG_INFO(1); 2927215976Sjmallett info.status_mask = 1ull<<4 /* rpoison */; 2928215976Sjmallett info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1); 2929215976Sjmallett info.enable_mask = 1ull<<4 /* rpoison */; 2930215976Sjmallett info.flags = 0; 2931215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2932215976Sjmallett info.group_index = 1; 2933215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2934215976Sjmallett info.parent.status_addr = CVMX_PEMX_INT_SUM(1); 2935215976Sjmallett info.parent.status_mask = 1ull<<10 /* exc */; 2936215976Sjmallett info.func = __cvmx_error_display; 2937215976Sjmallett info.user_info = (long) 2938215976Sjmallett "ERROR PEMX_DBG_INFO(1)[RPOISON]: Received Poisoned TLP\n" 2939215976Sjmallett " pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv\n"; 2940215976Sjmallett fail |= cvmx_error_add(&info); 2941215976Sjmallett 2942215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2943215976Sjmallett info.status_addr = CVMX_PEMX_DBG_INFO(1); 2944215976Sjmallett info.status_mask = 1ull<<5 /* rcemrc */; 2945215976Sjmallett info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1); 2946215976Sjmallett info.enable_mask = 1ull<<5 /* rcemrc */; 2947215976Sjmallett info.flags = 0; 2948215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2949215976Sjmallett info.group_index = 1; 2950215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2951215976Sjmallett info.parent.status_addr = CVMX_PEMX_INT_SUM(1); 2952215976Sjmallett info.parent.status_mask = 1ull<<10 /* exc */; 2953215976Sjmallett info.func = __cvmx_error_display; 2954215976Sjmallett info.user_info = (long) 2955215976Sjmallett "ERROR PEMX_DBG_INFO(1)[RCEMRC]: Received Correctable Error Message (RC Mode only)\n" 2956215976Sjmallett " pedc_radm_correctable_err\n"; 2957215976Sjmallett fail |= cvmx_error_add(&info); 2958215976Sjmallett 2959215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2960215976Sjmallett info.status_addr = CVMX_PEMX_DBG_INFO(1); 2961215976Sjmallett info.status_mask = 1ull<<6 /* rnfemrc */; 2962215976Sjmallett info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1); 2963215976Sjmallett info.enable_mask = 1ull<<6 /* rnfemrc */; 2964215976Sjmallett info.flags = 0; 2965215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2966215976Sjmallett info.group_index = 1; 2967215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2968215976Sjmallett info.parent.status_addr = CVMX_PEMX_INT_SUM(1); 2969215976Sjmallett info.parent.status_mask = 1ull<<10 /* exc */; 2970215976Sjmallett info.func = __cvmx_error_display; 2971215976Sjmallett info.user_info = (long) 2972215976Sjmallett "ERROR PEMX_DBG_INFO(1)[RNFEMRC]: Received Non-Fatal Error Message (RC Mode only)\n" 2973215976Sjmallett " pedc_radm_nonfatal_err\n"; 2974215976Sjmallett fail |= cvmx_error_add(&info); 2975215976Sjmallett 2976215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2977215976Sjmallett info.status_addr = CVMX_PEMX_DBG_INFO(1); 2978215976Sjmallett info.status_mask = 1ull<<7 /* rfemrc */; 2979215976Sjmallett info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1); 2980215976Sjmallett info.enable_mask = 1ull<<7 /* rfemrc */; 2981215976Sjmallett info.flags = 0; 2982215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 2983215976Sjmallett info.group_index = 1; 2984215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 2985215976Sjmallett info.parent.status_addr = CVMX_PEMX_INT_SUM(1); 2986215976Sjmallett info.parent.status_mask = 1ull<<10 /* exc */; 2987215976Sjmallett info.func = __cvmx_error_display; 2988215976Sjmallett info.user_info = (long) 2989215976Sjmallett "ERROR PEMX_DBG_INFO(1)[RFEMRC]: Received Fatal Error Message (RC Mode only)\n" 2990215976Sjmallett " pedc_radm_fatal_err\n" 2991215976Sjmallett " Bit set when a message with ERR_FATAL is set.\n"; 2992215976Sjmallett fail |= cvmx_error_add(&info); 2993215976Sjmallett 2994215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 2995215976Sjmallett info.status_addr = CVMX_PEMX_DBG_INFO(1); 2996215976Sjmallett info.status_mask = 1ull<<8 /* rpmerc */; 2997215976Sjmallett info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1); 2998215976Sjmallett info.enable_mask = 1ull<<8 /* rpmerc */; 2999215976Sjmallett info.flags = 0; 3000215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3001215976Sjmallett info.group_index = 1; 3002215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3003215976Sjmallett info.parent.status_addr = CVMX_PEMX_INT_SUM(1); 3004215976Sjmallett info.parent.status_mask = 1ull<<10 /* exc */; 3005215976Sjmallett info.func = __cvmx_error_display; 3006215976Sjmallett info.user_info = (long) 3007215976Sjmallett "ERROR PEMX_DBG_INFO(1)[RPMERC]: Received PME Message (RC Mode only)\n" 3008215976Sjmallett " pedc_radm_pm_pme\n"; 3009215976Sjmallett fail |= cvmx_error_add(&info); 3010215976Sjmallett 3011215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3012215976Sjmallett info.status_addr = CVMX_PEMX_DBG_INFO(1); 3013215976Sjmallett info.status_mask = 1ull<<9 /* rptamrc */; 3014215976Sjmallett info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1); 3015215976Sjmallett info.enable_mask = 1ull<<9 /* rptamrc */; 3016215976Sjmallett info.flags = 0; 3017215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3018215976Sjmallett info.group_index = 1; 3019215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3020215976Sjmallett info.parent.status_addr = CVMX_PEMX_INT_SUM(1); 3021215976Sjmallett info.parent.status_mask = 1ull<<10 /* exc */; 3022215976Sjmallett info.func = __cvmx_error_display; 3023215976Sjmallett info.user_info = (long) 3024215976Sjmallett "ERROR PEMX_DBG_INFO(1)[RPTAMRC]: Received PME Turnoff Acknowledge Message\n" 3025215976Sjmallett " (RC Mode only)\n" 3026215976Sjmallett " pedc_radm_pm_to_ack\n"; 3027215976Sjmallett fail |= cvmx_error_add(&info); 3028215976Sjmallett 3029215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3030215976Sjmallett info.status_addr = CVMX_PEMX_DBG_INFO(1); 3031215976Sjmallett info.status_mask = 1ull<<10 /* rumep */; 3032215976Sjmallett info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1); 3033215976Sjmallett info.enable_mask = 1ull<<10 /* rumep */; 3034215976Sjmallett info.flags = 0; 3035215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3036215976Sjmallett info.group_index = 1; 3037215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3038215976Sjmallett info.parent.status_addr = CVMX_PEMX_INT_SUM(1); 3039215976Sjmallett info.parent.status_mask = 1ull<<10 /* exc */; 3040215976Sjmallett info.func = __cvmx_error_display; 3041215976Sjmallett info.user_info = (long) 3042215976Sjmallett "ERROR PEMX_DBG_INFO(1)[RUMEP]: Received Unlock Message (EP Mode Only)\n" 3043215976Sjmallett " pedc_radm_msg_unlock\n"; 3044215976Sjmallett fail |= cvmx_error_add(&info); 3045215976Sjmallett 3046215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3047215976Sjmallett info.status_addr = CVMX_PEMX_DBG_INFO(1); 3048215976Sjmallett info.status_mask = 1ull<<11 /* rvdm */; 3049215976Sjmallett info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1); 3050215976Sjmallett info.enable_mask = 1ull<<11 /* rvdm */; 3051215976Sjmallett info.flags = 0; 3052215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3053215976Sjmallett info.group_index = 1; 3054215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3055215976Sjmallett info.parent.status_addr = CVMX_PEMX_INT_SUM(1); 3056215976Sjmallett info.parent.status_mask = 1ull<<10 /* exc */; 3057215976Sjmallett info.func = __cvmx_error_display; 3058215976Sjmallett info.user_info = (long) 3059215976Sjmallett "ERROR PEMX_DBG_INFO(1)[RVDM]: Received Vendor-Defined Message\n" 3060215976Sjmallett " pedc_radm_vendor_msg\n"; 3061215976Sjmallett fail |= cvmx_error_add(&info); 3062215976Sjmallett 3063215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3064215976Sjmallett info.status_addr = CVMX_PEMX_DBG_INFO(1); 3065215976Sjmallett info.status_mask = 1ull<<12 /* acto */; 3066215976Sjmallett info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1); 3067215976Sjmallett info.enable_mask = 1ull<<12 /* acto */; 3068215976Sjmallett info.flags = 0; 3069215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3070215976Sjmallett info.group_index = 1; 3071215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3072215976Sjmallett info.parent.status_addr = CVMX_PEMX_INT_SUM(1); 3073215976Sjmallett info.parent.status_mask = 1ull<<10 /* exc */; 3074215976Sjmallett info.func = __cvmx_error_display; 3075215976Sjmallett info.user_info = (long) 3076215976Sjmallett "ERROR PEMX_DBG_INFO(1)[ACTO]: A Completion Timeout Occured\n" 3077215976Sjmallett " pedc_radm_cpl_timeout\n"; 3078215976Sjmallett fail |= cvmx_error_add(&info); 3079215976Sjmallett 3080215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3081215976Sjmallett info.status_addr = CVMX_PEMX_DBG_INFO(1); 3082215976Sjmallett info.status_mask = 1ull<<13 /* rte */; 3083215976Sjmallett info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1); 3084215976Sjmallett info.enable_mask = 1ull<<13 /* rte */; 3085215976Sjmallett info.flags = 0; 3086215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3087215976Sjmallett info.group_index = 1; 3088215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3089215976Sjmallett info.parent.status_addr = CVMX_PEMX_INT_SUM(1); 3090215976Sjmallett info.parent.status_mask = 1ull<<10 /* exc */; 3091215976Sjmallett info.func = __cvmx_error_display; 3092215976Sjmallett info.user_info = (long) 3093215976Sjmallett "ERROR PEMX_DBG_INFO(1)[RTE]: Replay Timer Expired\n" 3094215976Sjmallett " xdlh_replay_timeout_err\n" 3095215976Sjmallett " This bit is set when the REPLAY_TIMER expires in\n" 3096215976Sjmallett " the PCIE core. The probability of this bit being\n" 3097215976Sjmallett " set will increase with the traffic load.\n"; 3098215976Sjmallett fail |= cvmx_error_add(&info); 3099215976Sjmallett 3100215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3101215976Sjmallett info.status_addr = CVMX_PEMX_DBG_INFO(1); 3102215976Sjmallett info.status_mask = 1ull<<14 /* mre */; 3103215976Sjmallett info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1); 3104215976Sjmallett info.enable_mask = 1ull<<14 /* mre */; 3105215976Sjmallett info.flags = 0; 3106215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3107215976Sjmallett info.group_index = 1; 3108215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3109215976Sjmallett info.parent.status_addr = CVMX_PEMX_INT_SUM(1); 3110215976Sjmallett info.parent.status_mask = 1ull<<10 /* exc */; 3111215976Sjmallett info.func = __cvmx_error_display; 3112215976Sjmallett info.user_info = (long) 3113215976Sjmallett "ERROR PEMX_DBG_INFO(1)[MRE]: Max Retries Exceeded\n" 3114215976Sjmallett " xdlh_replay_num_rlover_err\n"; 3115215976Sjmallett fail |= cvmx_error_add(&info); 3116215976Sjmallett 3117215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3118215976Sjmallett info.status_addr = CVMX_PEMX_DBG_INFO(1); 3119215976Sjmallett info.status_mask = 1ull<<15 /* rdwdle */; 3120215976Sjmallett info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1); 3121215976Sjmallett info.enable_mask = 1ull<<15 /* rdwdle */; 3122215976Sjmallett info.flags = 0; 3123215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3124215976Sjmallett info.group_index = 1; 3125215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3126215976Sjmallett info.parent.status_addr = CVMX_PEMX_INT_SUM(1); 3127215976Sjmallett info.parent.status_mask = 1ull<<10 /* exc */; 3128215976Sjmallett info.func = __cvmx_error_display; 3129215976Sjmallett info.user_info = (long) 3130215976Sjmallett "ERROR PEMX_DBG_INFO(1)[RDWDLE]: Received DLLP with DataLink Layer Error\n" 3131215976Sjmallett " rdlh_bad_dllp_err\n"; 3132215976Sjmallett fail |= cvmx_error_add(&info); 3133215976Sjmallett 3134215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3135215976Sjmallett info.status_addr = CVMX_PEMX_DBG_INFO(1); 3136215976Sjmallett info.status_mask = 1ull<<16 /* rtwdle */; 3137215976Sjmallett info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1); 3138215976Sjmallett info.enable_mask = 1ull<<16 /* rtwdle */; 3139215976Sjmallett info.flags = 0; 3140215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3141215976Sjmallett info.group_index = 1; 3142215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3143215976Sjmallett info.parent.status_addr = CVMX_PEMX_INT_SUM(1); 3144215976Sjmallett info.parent.status_mask = 1ull<<10 /* exc */; 3145215976Sjmallett info.func = __cvmx_error_display; 3146215976Sjmallett info.user_info = (long) 3147215976Sjmallett "ERROR PEMX_DBG_INFO(1)[RTWDLE]: Received TLP with DataLink Layer Error\n" 3148215976Sjmallett " rdlh_bad_tlp_err\n"; 3149215976Sjmallett fail |= cvmx_error_add(&info); 3150215976Sjmallett 3151215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3152215976Sjmallett info.status_addr = CVMX_PEMX_DBG_INFO(1); 3153215976Sjmallett info.status_mask = 1ull<<17 /* dpeoosd */; 3154215976Sjmallett info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1); 3155215976Sjmallett info.enable_mask = 1ull<<17 /* dpeoosd */; 3156215976Sjmallett info.flags = 0; 3157215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3158215976Sjmallett info.group_index = 1; 3159215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3160215976Sjmallett info.parent.status_addr = CVMX_PEMX_INT_SUM(1); 3161215976Sjmallett info.parent.status_mask = 1ull<<10 /* exc */; 3162215976Sjmallett info.func = __cvmx_error_display; 3163215976Sjmallett info.user_info = (long) 3164215976Sjmallett "ERROR PEMX_DBG_INFO(1)[DPEOOSD]: DLLP protocol error (out of sequence DLLP)\n" 3165215976Sjmallett " rdlh_prot_err\n"; 3166215976Sjmallett fail |= cvmx_error_add(&info); 3167215976Sjmallett 3168215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3169215976Sjmallett info.status_addr = CVMX_PEMX_DBG_INFO(1); 3170215976Sjmallett info.status_mask = 1ull<<18 /* fcpvwt */; 3171215976Sjmallett info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1); 3172215976Sjmallett info.enable_mask = 1ull<<18 /* fcpvwt */; 3173215976Sjmallett info.flags = 0; 3174215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3175215976Sjmallett info.group_index = 1; 3176215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3177215976Sjmallett info.parent.status_addr = CVMX_PEMX_INT_SUM(1); 3178215976Sjmallett info.parent.status_mask = 1ull<<10 /* exc */; 3179215976Sjmallett info.func = __cvmx_error_display; 3180215976Sjmallett info.user_info = (long) 3181215976Sjmallett "ERROR PEMX_DBG_INFO(1)[FCPVWT]: Flow Control Protocol Violation (Watchdog Timer)\n" 3182215976Sjmallett " rtlh_fc_prot_err\n"; 3183215976Sjmallett fail |= cvmx_error_add(&info); 3184215976Sjmallett 3185215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3186215976Sjmallett info.status_addr = CVMX_PEMX_DBG_INFO(1); 3187215976Sjmallett info.status_mask = 1ull<<19 /* rpe */; 3188215976Sjmallett info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1); 3189215976Sjmallett info.enable_mask = 1ull<<19 /* rpe */; 3190215976Sjmallett info.flags = 0; 3191215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3192215976Sjmallett info.group_index = 1; 3193215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3194215976Sjmallett info.parent.status_addr = CVMX_PEMX_INT_SUM(1); 3195215976Sjmallett info.parent.status_mask = 1ull<<10 /* exc */; 3196215976Sjmallett info.func = __cvmx_error_display; 3197215976Sjmallett info.user_info = (long) 3198215976Sjmallett "ERROR PEMX_DBG_INFO(1)[RPE]: When the PHY reports 8B/10B decode error\n" 3199215976Sjmallett " (RxStatus = 3b100) or disparity error\n" 3200215976Sjmallett " (RxStatus = 3b111), the signal rmlh_rcvd_err will\n" 3201215976Sjmallett " be asserted.\n" 3202215976Sjmallett " rmlh_rcvd_err\n"; 3203215976Sjmallett fail |= cvmx_error_add(&info); 3204215976Sjmallett 3205215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3206215976Sjmallett info.status_addr = CVMX_PEMX_DBG_INFO(1); 3207215976Sjmallett info.status_mask = 1ull<<20 /* fcuv */; 3208215976Sjmallett info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1); 3209215976Sjmallett info.enable_mask = 1ull<<20 /* fcuv */; 3210215976Sjmallett info.flags = 0; 3211215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3212215976Sjmallett info.group_index = 1; 3213215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3214215976Sjmallett info.parent.status_addr = CVMX_PEMX_INT_SUM(1); 3215215976Sjmallett info.parent.status_mask = 1ull<<10 /* exc */; 3216215976Sjmallett info.func = __cvmx_error_display; 3217215976Sjmallett info.user_info = (long) 3218215976Sjmallett "ERROR PEMX_DBG_INFO(1)[FCUV]: Flow Control Update Violation (opt. checks)\n" 3219215976Sjmallett " int_xadm_fc_prot_err\n"; 3220215976Sjmallett fail |= cvmx_error_add(&info); 3221215976Sjmallett 3222215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3223215976Sjmallett info.status_addr = CVMX_PEMX_DBG_INFO(1); 3224215976Sjmallett info.status_mask = 1ull<<21 /* rqo */; 3225215976Sjmallett info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1); 3226215976Sjmallett info.enable_mask = 1ull<<21 /* rqo */; 3227215976Sjmallett info.flags = 0; 3228215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3229215976Sjmallett info.group_index = 1; 3230215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3231215976Sjmallett info.parent.status_addr = CVMX_PEMX_INT_SUM(1); 3232215976Sjmallett info.parent.status_mask = 1ull<<10 /* exc */; 3233215976Sjmallett info.func = __cvmx_error_display; 3234215976Sjmallett info.user_info = (long) 3235215976Sjmallett "ERROR PEMX_DBG_INFO(1)[RQO]: Receive queue overflow. Normally happens only when\n" 3236215976Sjmallett " flow control advertisements are ignored\n" 3237215976Sjmallett " radm_qoverflow\n"; 3238215976Sjmallett fail |= cvmx_error_add(&info); 3239215976Sjmallett 3240215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3241215976Sjmallett info.status_addr = CVMX_PEMX_DBG_INFO(1); 3242215976Sjmallett info.status_mask = 1ull<<22 /* rauc */; 3243215976Sjmallett info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1); 3244215976Sjmallett info.enable_mask = 1ull<<22 /* rauc */; 3245215976Sjmallett info.flags = 0; 3246215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3247215976Sjmallett info.group_index = 1; 3248215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3249215976Sjmallett info.parent.status_addr = CVMX_PEMX_INT_SUM(1); 3250215976Sjmallett info.parent.status_mask = 1ull<<10 /* exc */; 3251215976Sjmallett info.func = __cvmx_error_display; 3252215976Sjmallett info.user_info = (long) 3253215976Sjmallett "ERROR PEMX_DBG_INFO(1)[RAUC]: Received an unexpected completion\n" 3254215976Sjmallett " radm_unexp_cpl_err\n"; 3255215976Sjmallett fail |= cvmx_error_add(&info); 3256215976Sjmallett 3257215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3258215976Sjmallett info.status_addr = CVMX_PEMX_DBG_INFO(1); 3259215976Sjmallett info.status_mask = 1ull<<23 /* racur */; 3260215976Sjmallett info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1); 3261215976Sjmallett info.enable_mask = 1ull<<23 /* racur */; 3262215976Sjmallett info.flags = 0; 3263215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3264215976Sjmallett info.group_index = 1; 3265215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3266215976Sjmallett info.parent.status_addr = CVMX_PEMX_INT_SUM(1); 3267215976Sjmallett info.parent.status_mask = 1ull<<10 /* exc */; 3268215976Sjmallett info.func = __cvmx_error_display; 3269215976Sjmallett info.user_info = (long) 3270215976Sjmallett "ERROR PEMX_DBG_INFO(1)[RACUR]: Received a completion with UR status\n" 3271215976Sjmallett " radm_rcvd_cpl_ur\n"; 3272215976Sjmallett fail |= cvmx_error_add(&info); 3273215976Sjmallett 3274215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3275215976Sjmallett info.status_addr = CVMX_PEMX_DBG_INFO(1); 3276215976Sjmallett info.status_mask = 1ull<<24 /* racca */; 3277215976Sjmallett info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1); 3278215976Sjmallett info.enable_mask = 1ull<<24 /* racca */; 3279215976Sjmallett info.flags = 0; 3280215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3281215976Sjmallett info.group_index = 1; 3282215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3283215976Sjmallett info.parent.status_addr = CVMX_PEMX_INT_SUM(1); 3284215976Sjmallett info.parent.status_mask = 1ull<<10 /* exc */; 3285215976Sjmallett info.func = __cvmx_error_display; 3286215976Sjmallett info.user_info = (long) 3287215976Sjmallett "ERROR PEMX_DBG_INFO(1)[RACCA]: Received a completion with CA status\n" 3288215976Sjmallett " radm_rcvd_cpl_ca\n"; 3289215976Sjmallett fail |= cvmx_error_add(&info); 3290215976Sjmallett 3291215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3292215976Sjmallett info.status_addr = CVMX_PEMX_DBG_INFO(1); 3293215976Sjmallett info.status_mask = 1ull<<25 /* caar */; 3294215976Sjmallett info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1); 3295215976Sjmallett info.enable_mask = 1ull<<25 /* caar */; 3296215976Sjmallett info.flags = 0; 3297215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3298215976Sjmallett info.group_index = 1; 3299215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3300215976Sjmallett info.parent.status_addr = CVMX_PEMX_INT_SUM(1); 3301215976Sjmallett info.parent.status_mask = 1ull<<10 /* exc */; 3302215976Sjmallett info.func = __cvmx_error_display; 3303215976Sjmallett info.user_info = (long) 3304215976Sjmallett "ERROR PEMX_DBG_INFO(1)[CAAR]: Completer aborted a request\n" 3305215976Sjmallett " radm_rcvd_ca_req\n" 3306215976Sjmallett " This bit will never be set because Octeon does\n" 3307215976Sjmallett " not generate Completer Aborts.\n"; 3308215976Sjmallett fail |= cvmx_error_add(&info); 3309215976Sjmallett 3310215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3311215976Sjmallett info.status_addr = CVMX_PEMX_DBG_INFO(1); 3312215976Sjmallett info.status_mask = 1ull<<26 /* rarwdns */; 3313215976Sjmallett info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1); 3314215976Sjmallett info.enable_mask = 1ull<<26 /* rarwdns */; 3315215976Sjmallett info.flags = 0; 3316215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3317215976Sjmallett info.group_index = 1; 3318215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3319215976Sjmallett info.parent.status_addr = CVMX_PEMX_INT_SUM(1); 3320215976Sjmallett info.parent.status_mask = 1ull<<10 /* exc */; 3321215976Sjmallett info.func = __cvmx_error_display; 3322215976Sjmallett info.user_info = (long) 3323215976Sjmallett "ERROR PEMX_DBG_INFO(1)[RARWDNS]: Recieved a request which device does not support\n" 3324215976Sjmallett " radm_rcvd_ur_req\n"; 3325215976Sjmallett fail |= cvmx_error_add(&info); 3326215976Sjmallett 3327215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3328215976Sjmallett info.status_addr = CVMX_PEMX_DBG_INFO(1); 3329215976Sjmallett info.status_mask = 1ull<<27 /* ramtlp */; 3330215976Sjmallett info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1); 3331215976Sjmallett info.enable_mask = 1ull<<27 /* ramtlp */; 3332215976Sjmallett info.flags = 0; 3333215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3334215976Sjmallett info.group_index = 1; 3335215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3336215976Sjmallett info.parent.status_addr = CVMX_PEMX_INT_SUM(1); 3337215976Sjmallett info.parent.status_mask = 1ull<<10 /* exc */; 3338215976Sjmallett info.func = __cvmx_error_display; 3339215976Sjmallett info.user_info = (long) 3340215976Sjmallett "ERROR PEMX_DBG_INFO(1)[RAMTLP]: Received a malformed TLP\n" 3341215976Sjmallett " radm_mlf_tlp_err\n"; 3342215976Sjmallett fail |= cvmx_error_add(&info); 3343215976Sjmallett 3344215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3345215976Sjmallett info.status_addr = CVMX_PEMX_DBG_INFO(1); 3346215976Sjmallett info.status_mask = 1ull<<28 /* racpp */; 3347215976Sjmallett info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1); 3348215976Sjmallett info.enable_mask = 1ull<<28 /* racpp */; 3349215976Sjmallett info.flags = 0; 3350215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3351215976Sjmallett info.group_index = 1; 3352215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3353215976Sjmallett info.parent.status_addr = CVMX_PEMX_INT_SUM(1); 3354215976Sjmallett info.parent.status_mask = 1ull<<10 /* exc */; 3355215976Sjmallett info.func = __cvmx_error_display; 3356215976Sjmallett info.user_info = (long) 3357215976Sjmallett "ERROR PEMX_DBG_INFO(1)[RACPP]: Received a completion with poisoned payload\n" 3358215976Sjmallett " radm_rcvd_cpl_poisoned\n"; 3359215976Sjmallett fail |= cvmx_error_add(&info); 3360215976Sjmallett 3361215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3362215976Sjmallett info.status_addr = CVMX_PEMX_DBG_INFO(1); 3363215976Sjmallett info.status_mask = 1ull<<29 /* rawwpp */; 3364215976Sjmallett info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1); 3365215976Sjmallett info.enable_mask = 1ull<<29 /* rawwpp */; 3366215976Sjmallett info.flags = 0; 3367215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3368215976Sjmallett info.group_index = 1; 3369215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3370215976Sjmallett info.parent.status_addr = CVMX_PEMX_INT_SUM(1); 3371215976Sjmallett info.parent.status_mask = 1ull<<10 /* exc */; 3372215976Sjmallett info.func = __cvmx_error_display; 3373215976Sjmallett info.user_info = (long) 3374215976Sjmallett "ERROR PEMX_DBG_INFO(1)[RAWWPP]: Received a write with poisoned payload\n" 3375215976Sjmallett " radm_rcvd_wreq_poisoned\n"; 3376215976Sjmallett fail |= cvmx_error_add(&info); 3377215976Sjmallett 3378215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3379215976Sjmallett info.status_addr = CVMX_PEMX_DBG_INFO(1); 3380215976Sjmallett info.status_mask = 1ull<<30 /* ecrc_e */; 3381215976Sjmallett info.enable_addr = CVMX_PEMX_DBG_INFO_EN(1); 3382215976Sjmallett info.enable_mask = 1ull<<30 /* ecrc_e */; 3383215976Sjmallett info.flags = 0; 3384215976Sjmallett info.group = CVMX_ERROR_GROUP_PCI; 3385215976Sjmallett info.group_index = 1; 3386215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3387215976Sjmallett info.parent.status_addr = CVMX_PEMX_INT_SUM(1); 3388215976Sjmallett info.parent.status_mask = 1ull<<10 /* exc */; 3389215976Sjmallett info.func = __cvmx_error_display; 3390215976Sjmallett info.user_info = (long) 3391215976Sjmallett "ERROR PEMX_DBG_INFO(1)[ECRC_E]: Received a ECRC error.\n" 3392215976Sjmallett " radm_ecrc_err\n"; 3393215976Sjmallett fail |= cvmx_error_add(&info); 3394215976Sjmallett 3395215976Sjmallett /* CVMX_FPA_INT_SUM */ 3396215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3397215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 3398215976Sjmallett info.status_mask = 1ull<<0 /* fed0_sbe */; 3399215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 3400215976Sjmallett info.enable_mask = 1ull<<0 /* fed0_sbe */; 3401215976Sjmallett info.flags = 0; 3402215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3403215976Sjmallett info.group_index = 0; 3404215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3405215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 3406215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 3407215976Sjmallett info.func = __cvmx_error_display; 3408215976Sjmallett info.user_info = (long) 3409215976Sjmallett "ERROR FPA_INT_SUM[FED0_SBE]: Set when a Single Bit Error is detected in FPF0.\n"; 3410215976Sjmallett fail |= cvmx_error_add(&info); 3411215976Sjmallett 3412215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3413215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 3414215976Sjmallett info.status_mask = 1ull<<1 /* fed0_dbe */; 3415215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 3416215976Sjmallett info.enable_mask = 1ull<<1 /* fed0_dbe */; 3417215976Sjmallett info.flags = 0; 3418215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3419215976Sjmallett info.group_index = 0; 3420215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3421215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 3422215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 3423215976Sjmallett info.func = __cvmx_error_display; 3424215976Sjmallett info.user_info = (long) 3425215976Sjmallett "ERROR FPA_INT_SUM[FED0_DBE]: Set when a Double Bit Error is detected in FPF0.\n"; 3426215976Sjmallett fail |= cvmx_error_add(&info); 3427215976Sjmallett 3428215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3429215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 3430215976Sjmallett info.status_mask = 1ull<<2 /* fed1_sbe */; 3431215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 3432215976Sjmallett info.enable_mask = 1ull<<2 /* fed1_sbe */; 3433215976Sjmallett info.flags = 0; 3434215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3435215976Sjmallett info.group_index = 0; 3436215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3437215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 3438215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 3439215976Sjmallett info.func = __cvmx_error_display; 3440215976Sjmallett info.user_info = (long) 3441215976Sjmallett "ERROR FPA_INT_SUM[FED1_SBE]: Set when a Single Bit Error is detected in FPF1.\n"; 3442215976Sjmallett fail |= cvmx_error_add(&info); 3443215976Sjmallett 3444215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3445215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 3446215976Sjmallett info.status_mask = 1ull<<3 /* fed1_dbe */; 3447215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 3448215976Sjmallett info.enable_mask = 1ull<<3 /* fed1_dbe */; 3449215976Sjmallett info.flags = 0; 3450215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3451215976Sjmallett info.group_index = 0; 3452215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3453215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 3454215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 3455215976Sjmallett info.func = __cvmx_error_display; 3456215976Sjmallett info.user_info = (long) 3457215976Sjmallett "ERROR FPA_INT_SUM[FED1_DBE]: Set when a Double Bit Error is detected in FPF1.\n"; 3458215976Sjmallett fail |= cvmx_error_add(&info); 3459215976Sjmallett 3460215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3461215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 3462215976Sjmallett info.status_mask = 1ull<<4 /* q0_und */; 3463215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 3464215976Sjmallett info.enable_mask = 1ull<<4 /* q0_und */; 3465215976Sjmallett info.flags = 0; 3466215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3467215976Sjmallett info.group_index = 0; 3468215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3469215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 3470215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 3471215976Sjmallett info.func = __cvmx_error_display; 3472215976Sjmallett info.user_info = (long) 3473215976Sjmallett "ERROR FPA_INT_SUM[Q0_UND]: Set when a Queue0 page count available goes\n" 3474215976Sjmallett " negative.\n"; 3475215976Sjmallett fail |= cvmx_error_add(&info); 3476215976Sjmallett 3477215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3478215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 3479215976Sjmallett info.status_mask = 1ull<<5 /* q0_coff */; 3480215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 3481215976Sjmallett info.enable_mask = 1ull<<5 /* q0_coff */; 3482215976Sjmallett info.flags = 0; 3483215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3484215976Sjmallett info.group_index = 0; 3485215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3486215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 3487215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 3488215976Sjmallett info.func = __cvmx_error_display; 3489215976Sjmallett info.user_info = (long) 3490215976Sjmallett "ERROR FPA_INT_SUM[Q0_COFF]: Set when a Queue0 stack end tag is present and\n" 3491215976Sjmallett " the count available is greater than pointers\n" 3492215976Sjmallett " present in the FPA.\n"; 3493215976Sjmallett fail |= cvmx_error_add(&info); 3494215976Sjmallett 3495215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3496215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 3497215976Sjmallett info.status_mask = 1ull<<6 /* q0_perr */; 3498215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 3499215976Sjmallett info.enable_mask = 1ull<<6 /* q0_perr */; 3500215976Sjmallett info.flags = 0; 3501215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3502215976Sjmallett info.group_index = 0; 3503215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3504215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 3505215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 3506215976Sjmallett info.func = __cvmx_error_display; 3507215976Sjmallett info.user_info = (long) 3508215976Sjmallett "ERROR FPA_INT_SUM[Q0_PERR]: Set when a Queue0 pointer read from the stack in\n" 3509215976Sjmallett " the L2C does not have the FPA owner ship bit set.\n"; 3510215976Sjmallett fail |= cvmx_error_add(&info); 3511215976Sjmallett 3512215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3513215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 3514215976Sjmallett info.status_mask = 1ull<<7 /* q1_und */; 3515215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 3516215976Sjmallett info.enable_mask = 1ull<<7 /* q1_und */; 3517215976Sjmallett info.flags = 0; 3518215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3519215976Sjmallett info.group_index = 0; 3520215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3521215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 3522215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 3523215976Sjmallett info.func = __cvmx_error_display; 3524215976Sjmallett info.user_info = (long) 3525215976Sjmallett "ERROR FPA_INT_SUM[Q1_UND]: Set when a Queue0 page count available goes\n" 3526215976Sjmallett " negative.\n"; 3527215976Sjmallett fail |= cvmx_error_add(&info); 3528215976Sjmallett 3529215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3530215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 3531215976Sjmallett info.status_mask = 1ull<<8 /* q1_coff */; 3532215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 3533215976Sjmallett info.enable_mask = 1ull<<8 /* q1_coff */; 3534215976Sjmallett info.flags = 0; 3535215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3536215976Sjmallett info.group_index = 0; 3537215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3538215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 3539215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 3540215976Sjmallett info.func = __cvmx_error_display; 3541215976Sjmallett info.user_info = (long) 3542215976Sjmallett "ERROR FPA_INT_SUM[Q1_COFF]: Set when a Queue0 stack end tag is present and\n" 3543215976Sjmallett " the count available is greater than pointers\n" 3544215976Sjmallett " present in the FPA.\n"; 3545215976Sjmallett fail |= cvmx_error_add(&info); 3546215976Sjmallett 3547215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3548215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 3549215976Sjmallett info.status_mask = 1ull<<9 /* q1_perr */; 3550215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 3551215976Sjmallett info.enable_mask = 1ull<<9 /* q1_perr */; 3552215976Sjmallett info.flags = 0; 3553215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3554215976Sjmallett info.group_index = 0; 3555215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3556215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 3557215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 3558215976Sjmallett info.func = __cvmx_error_display; 3559215976Sjmallett info.user_info = (long) 3560215976Sjmallett "ERROR FPA_INT_SUM[Q1_PERR]: Set when a Queue0 pointer read from the stack in\n" 3561215976Sjmallett " the L2C does not have the FPA owner ship bit set.\n"; 3562215976Sjmallett fail |= cvmx_error_add(&info); 3563215976Sjmallett 3564215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3565215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 3566215976Sjmallett info.status_mask = 1ull<<10 /* q2_und */; 3567215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 3568215976Sjmallett info.enable_mask = 1ull<<10 /* q2_und */; 3569215976Sjmallett info.flags = 0; 3570215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3571215976Sjmallett info.group_index = 0; 3572215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3573215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 3574215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 3575215976Sjmallett info.func = __cvmx_error_display; 3576215976Sjmallett info.user_info = (long) 3577215976Sjmallett "ERROR FPA_INT_SUM[Q2_UND]: Set when a Queue0 page count available goes\n" 3578215976Sjmallett " negative.\n"; 3579215976Sjmallett fail |= cvmx_error_add(&info); 3580215976Sjmallett 3581215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3582215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 3583215976Sjmallett info.status_mask = 1ull<<11 /* q2_coff */; 3584215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 3585215976Sjmallett info.enable_mask = 1ull<<11 /* q2_coff */; 3586215976Sjmallett info.flags = 0; 3587215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3588215976Sjmallett info.group_index = 0; 3589215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3590215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 3591215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 3592215976Sjmallett info.func = __cvmx_error_display; 3593215976Sjmallett info.user_info = (long) 3594215976Sjmallett "ERROR FPA_INT_SUM[Q2_COFF]: Set when a Queue0 stack end tag is present and\n" 3595215976Sjmallett " the count available is greater than than pointers\n" 3596215976Sjmallett " present in the FPA.\n"; 3597215976Sjmallett fail |= cvmx_error_add(&info); 3598215976Sjmallett 3599215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3600215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 3601215976Sjmallett info.status_mask = 1ull<<12 /* q2_perr */; 3602215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 3603215976Sjmallett info.enable_mask = 1ull<<12 /* q2_perr */; 3604215976Sjmallett info.flags = 0; 3605215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3606215976Sjmallett info.group_index = 0; 3607215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3608215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 3609215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 3610215976Sjmallett info.func = __cvmx_error_display; 3611215976Sjmallett info.user_info = (long) 3612215976Sjmallett "ERROR FPA_INT_SUM[Q2_PERR]: Set when a Queue0 pointer read from the stack in\n" 3613215976Sjmallett " the L2C does not have the FPA owner ship bit set.\n"; 3614215976Sjmallett fail |= cvmx_error_add(&info); 3615215976Sjmallett 3616215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3617215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 3618215976Sjmallett info.status_mask = 1ull<<13 /* q3_und */; 3619215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 3620215976Sjmallett info.enable_mask = 1ull<<13 /* q3_und */; 3621215976Sjmallett info.flags = 0; 3622215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3623215976Sjmallett info.group_index = 0; 3624215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3625215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 3626215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 3627215976Sjmallett info.func = __cvmx_error_display; 3628215976Sjmallett info.user_info = (long) 3629215976Sjmallett "ERROR FPA_INT_SUM[Q3_UND]: Set when a Queue0 page count available goes\n" 3630215976Sjmallett " negative.\n"; 3631215976Sjmallett fail |= cvmx_error_add(&info); 3632215976Sjmallett 3633215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3634215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 3635215976Sjmallett info.status_mask = 1ull<<14 /* q3_coff */; 3636215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 3637215976Sjmallett info.enable_mask = 1ull<<14 /* q3_coff */; 3638215976Sjmallett info.flags = 0; 3639215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3640215976Sjmallett info.group_index = 0; 3641215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3642215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 3643215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 3644215976Sjmallett info.func = __cvmx_error_display; 3645215976Sjmallett info.user_info = (long) 3646215976Sjmallett "ERROR FPA_INT_SUM[Q3_COFF]: Set when a Queue0 stack end tag is present and\n" 3647215976Sjmallett " the count available is greater than than pointers\n" 3648215976Sjmallett " present in the FPA.\n"; 3649215976Sjmallett fail |= cvmx_error_add(&info); 3650215976Sjmallett 3651215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3652215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 3653215976Sjmallett info.status_mask = 1ull<<15 /* q3_perr */; 3654215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 3655215976Sjmallett info.enable_mask = 1ull<<15 /* q3_perr */; 3656215976Sjmallett info.flags = 0; 3657215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3658215976Sjmallett info.group_index = 0; 3659215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3660215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 3661215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 3662215976Sjmallett info.func = __cvmx_error_display; 3663215976Sjmallett info.user_info = (long) 3664215976Sjmallett "ERROR FPA_INT_SUM[Q3_PERR]: Set when a Queue0 pointer read from the stack in\n" 3665215976Sjmallett " the L2C does not have the FPA owner ship bit set.\n"; 3666215976Sjmallett fail |= cvmx_error_add(&info); 3667215976Sjmallett 3668215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3669215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 3670215976Sjmallett info.status_mask = 1ull<<16 /* q4_und */; 3671215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 3672215976Sjmallett info.enable_mask = 1ull<<16 /* q4_und */; 3673215976Sjmallett info.flags = 0; 3674215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3675215976Sjmallett info.group_index = 0; 3676215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3677215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 3678215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 3679215976Sjmallett info.func = __cvmx_error_display; 3680215976Sjmallett info.user_info = (long) 3681215976Sjmallett "ERROR FPA_INT_SUM[Q4_UND]: Set when a Queue0 page count available goes\n" 3682215976Sjmallett " negative.\n"; 3683215976Sjmallett fail |= cvmx_error_add(&info); 3684215976Sjmallett 3685215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3686215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 3687215976Sjmallett info.status_mask = 1ull<<17 /* q4_coff */; 3688215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 3689215976Sjmallett info.enable_mask = 1ull<<17 /* q4_coff */; 3690215976Sjmallett info.flags = 0; 3691215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3692215976Sjmallett info.group_index = 0; 3693215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3694215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 3695215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 3696215976Sjmallett info.func = __cvmx_error_display; 3697215976Sjmallett info.user_info = (long) 3698215976Sjmallett "ERROR FPA_INT_SUM[Q4_COFF]: Set when a Queue0 stack end tag is present and\n" 3699215976Sjmallett " the count available is greater than than pointers\n" 3700215976Sjmallett " present in the FPA.\n"; 3701215976Sjmallett fail |= cvmx_error_add(&info); 3702215976Sjmallett 3703215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3704215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 3705215976Sjmallett info.status_mask = 1ull<<18 /* q4_perr */; 3706215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 3707215976Sjmallett info.enable_mask = 1ull<<18 /* q4_perr */; 3708215976Sjmallett info.flags = 0; 3709215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3710215976Sjmallett info.group_index = 0; 3711215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3712215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 3713215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 3714215976Sjmallett info.func = __cvmx_error_display; 3715215976Sjmallett info.user_info = (long) 3716215976Sjmallett "ERROR FPA_INT_SUM[Q4_PERR]: Set when a Queue0 pointer read from the stack in\n" 3717215976Sjmallett " the L2C does not have the FPA owner ship bit set.\n"; 3718215976Sjmallett fail |= cvmx_error_add(&info); 3719215976Sjmallett 3720215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3721215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 3722215976Sjmallett info.status_mask = 1ull<<19 /* q5_und */; 3723215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 3724215976Sjmallett info.enable_mask = 1ull<<19 /* q5_und */; 3725215976Sjmallett info.flags = 0; 3726215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3727215976Sjmallett info.group_index = 0; 3728215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3729215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 3730215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 3731215976Sjmallett info.func = __cvmx_error_display; 3732215976Sjmallett info.user_info = (long) 3733215976Sjmallett "ERROR FPA_INT_SUM[Q5_UND]: Set when a Queue0 page count available goes\n" 3734215976Sjmallett " negative.\n"; 3735215976Sjmallett fail |= cvmx_error_add(&info); 3736215976Sjmallett 3737215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3738215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 3739215976Sjmallett info.status_mask = 1ull<<20 /* q5_coff */; 3740215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 3741215976Sjmallett info.enable_mask = 1ull<<20 /* q5_coff */; 3742215976Sjmallett info.flags = 0; 3743215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3744215976Sjmallett info.group_index = 0; 3745215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3746215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 3747215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 3748215976Sjmallett info.func = __cvmx_error_display; 3749215976Sjmallett info.user_info = (long) 3750215976Sjmallett "ERROR FPA_INT_SUM[Q5_COFF]: Set when a Queue0 stack end tag is present and\n" 3751215976Sjmallett " the count available is greater than than pointers\n" 3752215976Sjmallett " present in the FPA.\n"; 3753215976Sjmallett fail |= cvmx_error_add(&info); 3754215976Sjmallett 3755215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3756215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 3757215976Sjmallett info.status_mask = 1ull<<21 /* q5_perr */; 3758215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 3759215976Sjmallett info.enable_mask = 1ull<<21 /* q5_perr */; 3760215976Sjmallett info.flags = 0; 3761215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3762215976Sjmallett info.group_index = 0; 3763215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3764215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 3765215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 3766215976Sjmallett info.func = __cvmx_error_display; 3767215976Sjmallett info.user_info = (long) 3768215976Sjmallett "ERROR FPA_INT_SUM[Q5_PERR]: Set when a Queue0 pointer read from the stack in\n" 3769215976Sjmallett " the L2C does not have the FPA owner ship bit set.\n"; 3770215976Sjmallett fail |= cvmx_error_add(&info); 3771215976Sjmallett 3772215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3773215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 3774215976Sjmallett info.status_mask = 1ull<<22 /* q6_und */; 3775215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 3776215976Sjmallett info.enable_mask = 1ull<<22 /* q6_und */; 3777215976Sjmallett info.flags = 0; 3778215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3779215976Sjmallett info.group_index = 0; 3780215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3781215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 3782215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 3783215976Sjmallett info.func = __cvmx_error_display; 3784215976Sjmallett info.user_info = (long) 3785215976Sjmallett "ERROR FPA_INT_SUM[Q6_UND]: Set when a Queue0 page count available goes\n" 3786215976Sjmallett " negative.\n"; 3787215976Sjmallett fail |= cvmx_error_add(&info); 3788215976Sjmallett 3789215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3790215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 3791215976Sjmallett info.status_mask = 1ull<<23 /* q6_coff */; 3792215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 3793215976Sjmallett info.enable_mask = 1ull<<23 /* q6_coff */; 3794215976Sjmallett info.flags = 0; 3795215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3796215976Sjmallett info.group_index = 0; 3797215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3798215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 3799215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 3800215976Sjmallett info.func = __cvmx_error_display; 3801215976Sjmallett info.user_info = (long) 3802215976Sjmallett "ERROR FPA_INT_SUM[Q6_COFF]: Set when a Queue0 stack end tag is present and\n" 3803215976Sjmallett " the count available is greater than than pointers\n" 3804215976Sjmallett " present in the FPA.\n"; 3805215976Sjmallett fail |= cvmx_error_add(&info); 3806215976Sjmallett 3807215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3808215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 3809215976Sjmallett info.status_mask = 1ull<<24 /* q6_perr */; 3810215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 3811215976Sjmallett info.enable_mask = 1ull<<24 /* q6_perr */; 3812215976Sjmallett info.flags = 0; 3813215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3814215976Sjmallett info.group_index = 0; 3815215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3816215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 3817215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 3818215976Sjmallett info.func = __cvmx_error_display; 3819215976Sjmallett info.user_info = (long) 3820215976Sjmallett "ERROR FPA_INT_SUM[Q6_PERR]: Set when a Queue0 pointer read from the stack in\n" 3821215976Sjmallett " the L2C does not have the FPA owner ship bit set.\n"; 3822215976Sjmallett fail |= cvmx_error_add(&info); 3823215976Sjmallett 3824215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3825215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 3826215976Sjmallett info.status_mask = 1ull<<25 /* q7_und */; 3827215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 3828215976Sjmallett info.enable_mask = 1ull<<25 /* q7_und */; 3829215976Sjmallett info.flags = 0; 3830215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3831215976Sjmallett info.group_index = 0; 3832215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3833215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 3834215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 3835215976Sjmallett info.func = __cvmx_error_display; 3836215976Sjmallett info.user_info = (long) 3837215976Sjmallett "ERROR FPA_INT_SUM[Q7_UND]: Set when a Queue0 page count available goes\n" 3838215976Sjmallett " negative.\n"; 3839215976Sjmallett fail |= cvmx_error_add(&info); 3840215976Sjmallett 3841215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3842215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 3843215976Sjmallett info.status_mask = 1ull<<26 /* q7_coff */; 3844215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 3845215976Sjmallett info.enable_mask = 1ull<<26 /* q7_coff */; 3846215976Sjmallett info.flags = 0; 3847215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3848215976Sjmallett info.group_index = 0; 3849215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3850215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 3851215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 3852215976Sjmallett info.func = __cvmx_error_display; 3853215976Sjmallett info.user_info = (long) 3854215976Sjmallett "ERROR FPA_INT_SUM[Q7_COFF]: Set when a Queue0 stack end tag is present and\n" 3855215976Sjmallett " the count available is greater than than pointers\n" 3856215976Sjmallett " present in the FPA.\n"; 3857215976Sjmallett fail |= cvmx_error_add(&info); 3858215976Sjmallett 3859215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3860215976Sjmallett info.status_addr = CVMX_FPA_INT_SUM; 3861215976Sjmallett info.status_mask = 1ull<<27 /* q7_perr */; 3862215976Sjmallett info.enable_addr = CVMX_FPA_INT_ENB; 3863215976Sjmallett info.enable_mask = 1ull<<27 /* q7_perr */; 3864215976Sjmallett info.flags = 0; 3865215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 3866215976Sjmallett info.group_index = 0; 3867215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3868215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 3869215976Sjmallett info.parent.status_mask = 1ull<<5 /* fpa */; 3870215976Sjmallett info.func = __cvmx_error_display; 3871215976Sjmallett info.user_info = (long) 3872215976Sjmallett "ERROR FPA_INT_SUM[Q7_PERR]: Set when a Queue0 pointer read from the stack in\n" 3873215976Sjmallett " the L2C does not have the FPA owner ship bit set.\n"; 3874215976Sjmallett fail |= cvmx_error_add(&info); 3875215976Sjmallett 3876215976Sjmallett /* CVMX_UCTLX_INT_REG(0) */ 3877215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3878215976Sjmallett info.status_addr = CVMX_UCTLX_INT_REG(0); 3879215976Sjmallett info.status_mask = 1ull<<0 /* pp_psh_f */; 3880215976Sjmallett info.enable_addr = CVMX_UCTLX_INT_ENA(0); 3881215976Sjmallett info.enable_mask = 1ull<<0 /* pp_psh_f */; 3882215976Sjmallett info.flags = 0; 3883215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3884215976Sjmallett info.group_index = 0; 3885215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3886215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 3887215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3888215976Sjmallett info.func = __cvmx_error_display; 3889215976Sjmallett info.user_info = (long) 3890215976Sjmallett "ERROR UCTLX_INT_REG(0)[PP_PSH_F]: PP Access FIFO Pushed When Full\n"; 3891215976Sjmallett fail |= cvmx_error_add(&info); 3892215976Sjmallett 3893215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3894215976Sjmallett info.status_addr = CVMX_UCTLX_INT_REG(0); 3895215976Sjmallett info.status_mask = 1ull<<1 /* er_psh_f */; 3896215976Sjmallett info.enable_addr = CVMX_UCTLX_INT_ENA(0); 3897215976Sjmallett info.enable_mask = 1ull<<1 /* er_psh_f */; 3898215976Sjmallett info.flags = 0; 3899215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3900215976Sjmallett info.group_index = 0; 3901215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3902215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 3903215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3904215976Sjmallett info.func = __cvmx_error_display; 3905215976Sjmallett info.user_info = (long) 3906215976Sjmallett "ERROR UCTLX_INT_REG(0)[ER_PSH_F]: EHCI Read Buffer FIFO Pushed When Full\n"; 3907215976Sjmallett fail |= cvmx_error_add(&info); 3908215976Sjmallett 3909215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3910215976Sjmallett info.status_addr = CVMX_UCTLX_INT_REG(0); 3911215976Sjmallett info.status_mask = 1ull<<2 /* or_psh_f */; 3912215976Sjmallett info.enable_addr = CVMX_UCTLX_INT_ENA(0); 3913215976Sjmallett info.enable_mask = 1ull<<2 /* or_psh_f */; 3914215976Sjmallett info.flags = 0; 3915215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3916215976Sjmallett info.group_index = 0; 3917215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3918215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 3919215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3920215976Sjmallett info.func = __cvmx_error_display; 3921215976Sjmallett info.user_info = (long) 3922215976Sjmallett "ERROR UCTLX_INT_REG(0)[OR_PSH_F]: OHCI Read Buffer FIFO Pushed When Full\n"; 3923215976Sjmallett fail |= cvmx_error_add(&info); 3924215976Sjmallett 3925215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3926215976Sjmallett info.status_addr = CVMX_UCTLX_INT_REG(0); 3927215976Sjmallett info.status_mask = 1ull<<3 /* cf_psh_f */; 3928215976Sjmallett info.enable_addr = CVMX_UCTLX_INT_ENA(0); 3929215976Sjmallett info.enable_mask = 1ull<<3 /* cf_psh_f */; 3930215976Sjmallett info.flags = 0; 3931215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3932215976Sjmallett info.group_index = 0; 3933215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3934215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 3935215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3936215976Sjmallett info.func = __cvmx_error_display; 3937215976Sjmallett info.user_info = (long) 3938215976Sjmallett "ERROR UCTLX_INT_REG(0)[CF_PSH_F]: Command FIFO Pushed When Full\n"; 3939215976Sjmallett fail |= cvmx_error_add(&info); 3940215976Sjmallett 3941215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3942215976Sjmallett info.status_addr = CVMX_UCTLX_INT_REG(0); 3943215976Sjmallett info.status_mask = 1ull<<4 /* wb_psh_f */; 3944215976Sjmallett info.enable_addr = CVMX_UCTLX_INT_ENA(0); 3945215976Sjmallett info.enable_mask = 1ull<<4 /* wb_psh_f */; 3946215976Sjmallett info.flags = 0; 3947215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3948215976Sjmallett info.group_index = 0; 3949215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3950215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 3951215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3952215976Sjmallett info.func = __cvmx_error_display; 3953215976Sjmallett info.user_info = (long) 3954215976Sjmallett "ERROR UCTLX_INT_REG(0)[WB_PSH_F]: Write Buffer FIFO Pushed When Full\n"; 3955215976Sjmallett fail |= cvmx_error_add(&info); 3956215976Sjmallett 3957215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3958215976Sjmallett info.status_addr = CVMX_UCTLX_INT_REG(0); 3959215976Sjmallett info.status_mask = 1ull<<5 /* wb_pop_e */; 3960215976Sjmallett info.enable_addr = CVMX_UCTLX_INT_ENA(0); 3961215976Sjmallett info.enable_mask = 1ull<<5 /* wb_pop_e */; 3962215976Sjmallett info.flags = 0; 3963215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3964215976Sjmallett info.group_index = 0; 3965215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3966215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 3967215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3968215976Sjmallett info.func = __cvmx_error_display; 3969215976Sjmallett info.user_info = (long) 3970215976Sjmallett "ERROR UCTLX_INT_REG(0)[WB_POP_E]: Write Buffer FIFO Poped When Empty\n"; 3971215976Sjmallett fail |= cvmx_error_add(&info); 3972215976Sjmallett 3973215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3974215976Sjmallett info.status_addr = CVMX_UCTLX_INT_REG(0); 3975215976Sjmallett info.status_mask = 1ull<<6 /* oc_ovf_e */; 3976215976Sjmallett info.enable_addr = CVMX_UCTLX_INT_ENA(0); 3977215976Sjmallett info.enable_mask = 1ull<<6 /* oc_ovf_e */; 3978215976Sjmallett info.flags = 0; 3979215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3980215976Sjmallett info.group_index = 0; 3981215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 3982215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 3983215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 3984215976Sjmallett info.func = __cvmx_error_display; 3985215976Sjmallett info.user_info = (long) 3986215976Sjmallett "ERROR UCTLX_INT_REG(0)[OC_OVF_E]: Ohci Commit OVerFlow Error\n" 3987215976Sjmallett " When the error happenes, the whole NCB system needs\n" 3988215976Sjmallett " to be reset.\n"; 3989215976Sjmallett fail |= cvmx_error_add(&info); 3990215976Sjmallett 3991215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 3992215976Sjmallett info.status_addr = CVMX_UCTLX_INT_REG(0); 3993215976Sjmallett info.status_mask = 1ull<<7 /* ec_ovf_e */; 3994215976Sjmallett info.enable_addr = CVMX_UCTLX_INT_ENA(0); 3995215976Sjmallett info.enable_mask = 1ull<<7 /* ec_ovf_e */; 3996215976Sjmallett info.flags = 0; 3997215976Sjmallett info.group = CVMX_ERROR_GROUP_USB; 3998215976Sjmallett info.group_index = 0; 3999215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4000215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 4001215976Sjmallett info.parent.status_mask = 1ull<<13 /* usb */; 4002215976Sjmallett info.func = __cvmx_error_display; 4003215976Sjmallett info.user_info = (long) 4004215976Sjmallett "ERROR UCTLX_INT_REG(0)[EC_OVF_E]: Ehci Commit OVerFlow Error\n" 4005215976Sjmallett " When the error happenes, the whole NCB system needs\n" 4006215976Sjmallett " to be reset.\n"; 4007215976Sjmallett fail |= cvmx_error_add(&info); 4008215976Sjmallett 4009215976Sjmallett /* CVMX_MIO_BOOT_ERR */ 4010215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4011215976Sjmallett info.status_addr = CVMX_MIO_BOOT_ERR; 4012215976Sjmallett info.status_mask = 1ull<<0 /* adr_err */; 4013215976Sjmallett info.enable_addr = CVMX_MIO_BOOT_INT; 4014215976Sjmallett info.enable_mask = 1ull<<0 /* adr_int */; 4015215976Sjmallett info.flags = 0; 4016215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 4017215976Sjmallett info.group_index = 0; 4018215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4019215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 4020215976Sjmallett info.parent.status_mask = 1ull<<0 /* mio */; 4021215976Sjmallett info.func = __cvmx_error_display; 4022215976Sjmallett info.user_info = (long) 4023215976Sjmallett "ERROR MIO_BOOT_ERR[ADR_ERR]: Address decode error\n"; 4024215976Sjmallett fail |= cvmx_error_add(&info); 4025215976Sjmallett 4026215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4027215976Sjmallett info.status_addr = CVMX_MIO_BOOT_ERR; 4028215976Sjmallett info.status_mask = 1ull<<1 /* wait_err */; 4029215976Sjmallett info.enable_addr = CVMX_MIO_BOOT_INT; 4030215976Sjmallett info.enable_mask = 1ull<<1 /* wait_int */; 4031215976Sjmallett info.flags = 0; 4032215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 4033215976Sjmallett info.group_index = 0; 4034215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4035215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 4036215976Sjmallett info.parent.status_mask = 1ull<<0 /* mio */; 4037215976Sjmallett info.func = __cvmx_error_display; 4038215976Sjmallett info.user_info = (long) 4039215976Sjmallett "ERROR MIO_BOOT_ERR[WAIT_ERR]: Wait mode error\n"; 4040215976Sjmallett fail |= cvmx_error_add(&info); 4041215976Sjmallett 4042215976Sjmallett /* CVMX_MIO_RST_INT */ 4043215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4044215976Sjmallett info.status_addr = CVMX_MIO_RST_INT; 4045215976Sjmallett info.status_mask = 1ull<<0 /* rst_link0 */; 4046215976Sjmallett info.enable_addr = CVMX_MIO_RST_INT_EN; 4047215976Sjmallett info.enable_mask = 1ull<<0 /* rst_link0 */; 4048215976Sjmallett info.flags = 0; 4049215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 4050215976Sjmallett info.group_index = 0; 4051215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4052215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 4053215976Sjmallett info.parent.status_mask = 1ull<<0 /* mio */; 4054215976Sjmallett info.func = __cvmx_error_display; 4055215976Sjmallett info.user_info = (long) 4056215976Sjmallett "ERROR MIO_RST_INT[RST_LINK0]: A controller0 link-down/hot-reset occurred while\n" 4057215976Sjmallett " MIO_RST_CTL0[RST_LINK]=0. Software must assert\n" 4058215976Sjmallett " then de-assert CIU_SOFT_PRST[SOFT_PRST]\n"; 4059215976Sjmallett fail |= cvmx_error_add(&info); 4060215976Sjmallett 4061215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4062215976Sjmallett info.status_addr = CVMX_MIO_RST_INT; 4063215976Sjmallett info.status_mask = 1ull<<1 /* rst_link1 */; 4064215976Sjmallett info.enable_addr = CVMX_MIO_RST_INT_EN; 4065215976Sjmallett info.enable_mask = 1ull<<1 /* rst_link1 */; 4066215976Sjmallett info.flags = 0; 4067215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 4068215976Sjmallett info.group_index = 0; 4069215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4070215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 4071215976Sjmallett info.parent.status_mask = 1ull<<0 /* mio */; 4072215976Sjmallett info.func = __cvmx_error_display; 4073215976Sjmallett info.user_info = (long) 4074215976Sjmallett "ERROR MIO_RST_INT[RST_LINK1]: A controller1 link-down/hot-reset occurred while\n" 4075215976Sjmallett " MIO_RST_CTL1[RST_LINK]=0. Software must assert\n" 4076215976Sjmallett " then de-assert CIU_SOFT_PRST1[SOFT_PRST]\n"; 4077215976Sjmallett fail |= cvmx_error_add(&info); 4078215976Sjmallett 4079215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4080215976Sjmallett info.status_addr = CVMX_MIO_RST_INT; 4081215976Sjmallett info.status_mask = 1ull<<8 /* perst0 */; 4082215976Sjmallett info.enable_addr = CVMX_MIO_RST_INT_EN; 4083215976Sjmallett info.enable_mask = 1ull<<8 /* perst0 */; 4084215976Sjmallett info.flags = 0; 4085215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 4086215976Sjmallett info.group_index = 0; 4087215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4088215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 4089215976Sjmallett info.parent.status_mask = 1ull<<0 /* mio */; 4090215976Sjmallett info.func = __cvmx_error_display; 4091215976Sjmallett info.user_info = (long) 4092215976Sjmallett "ERROR MIO_RST_INT[PERST0]: PERST0_L asserted while MIO_RST_CTL0[RST_RCV]=1\n" 4093215976Sjmallett " and MIO_RST_CTL0[RST_CHIP]=0\n"; 4094215976Sjmallett fail |= cvmx_error_add(&info); 4095215976Sjmallett 4096215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4097215976Sjmallett info.status_addr = CVMX_MIO_RST_INT; 4098215976Sjmallett info.status_mask = 1ull<<9 /* perst1 */; 4099215976Sjmallett info.enable_addr = CVMX_MIO_RST_INT_EN; 4100215976Sjmallett info.enable_mask = 1ull<<9 /* perst1 */; 4101215976Sjmallett info.flags = 0; 4102215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 4103215976Sjmallett info.group_index = 0; 4104215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4105215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 4106215976Sjmallett info.parent.status_mask = 1ull<<0 /* mio */; 4107215976Sjmallett info.func = __cvmx_error_display; 4108215976Sjmallett info.user_info = (long) 4109215976Sjmallett "ERROR MIO_RST_INT[PERST1]: PERST1_L asserted while MIO_RST_CTL1[RST_RCV]=1\n" 4110215976Sjmallett " and MIO_RST_CTL1[RST_CHIP]=0\n"; 4111215976Sjmallett fail |= cvmx_error_add(&info); 4112215976Sjmallett 4113215976Sjmallett /* CVMX_DFM_FNT_STAT */ 4114215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4115215976Sjmallett info.status_addr = CVMX_DFM_FNT_STAT; 4116215976Sjmallett info.status_mask = 1ull<<0 /* sbe_err */; 4117215976Sjmallett info.enable_addr = CVMX_DFM_FNT_IENA; 4118215976Sjmallett info.enable_mask = 1ull<<0 /* sbe_intena */; 4119215976Sjmallett info.flags = 0; 4120215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 4121215976Sjmallett info.group_index = 0; 4122215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4123215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 4124215976Sjmallett info.parent.status_mask = 1ull<<40 /* dfm */; 4125215976Sjmallett info.func = __cvmx_error_display; 4126215976Sjmallett info.user_info = (long) 4127215976Sjmallett "ERROR DFM_FNT_STAT[SBE_ERR]: Single bit error detected(corrected) during\n" 4128215976Sjmallett " Memory Read.\n" 4129215976Sjmallett " Write of 1 will clear the corresponding error bit\n"; 4130215976Sjmallett fail |= cvmx_error_add(&info); 4131215976Sjmallett 4132215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4133215976Sjmallett info.status_addr = CVMX_DFM_FNT_STAT; 4134215976Sjmallett info.status_mask = 1ull<<1 /* dbe_err */; 4135215976Sjmallett info.enable_addr = CVMX_DFM_FNT_IENA; 4136215976Sjmallett info.enable_mask = 1ull<<1 /* dbe_intena */; 4137215976Sjmallett info.flags = 0; 4138215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 4139215976Sjmallett info.group_index = 0; 4140215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4141215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 4142215976Sjmallett info.parent.status_mask = 1ull<<40 /* dfm */; 4143215976Sjmallett info.func = __cvmx_error_display; 4144215976Sjmallett info.user_info = (long) 4145215976Sjmallett "ERROR DFM_FNT_STAT[DBE_ERR]: Double bit error detected(uncorrectable) during\n" 4146215976Sjmallett " Memory Read.\n" 4147215976Sjmallett " Write of 1 will clear the corresponding error bit\n"; 4148215976Sjmallett fail |= cvmx_error_add(&info); 4149215976Sjmallett 4150215976Sjmallett /* CVMX_TIM_REG_ERROR */ 4151215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4152215976Sjmallett info.status_addr = CVMX_TIM_REG_ERROR; 4153215976Sjmallett info.status_mask = 0xffffull<<0 /* mask */; 4154215976Sjmallett info.enable_addr = CVMX_TIM_REG_INT_MASK; 4155215976Sjmallett info.enable_mask = 0xffffull<<0 /* mask */; 4156215976Sjmallett info.flags = 0; 4157215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 4158215976Sjmallett info.group_index = 0; 4159215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4160215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 4161215976Sjmallett info.parent.status_mask = 1ull<<11 /* tim */; 4162215976Sjmallett info.func = __cvmx_error_display; 4163215976Sjmallett info.user_info = (long) 4164215976Sjmallett "ERROR TIM_REG_ERROR[MASK]: Bit mask indicating the rings in error\n"; 4165215976Sjmallett fail |= cvmx_error_add(&info); 4166215976Sjmallett 4167215976Sjmallett /* CVMX_LMCX_INT(0) */ 4168215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4169215976Sjmallett info.status_addr = CVMX_LMCX_INT(0); 4170215976Sjmallett info.status_mask = 0xfull<<1 /* sec_err */; 4171215976Sjmallett info.enable_addr = CVMX_LMCX_INT_EN(0); 4172215976Sjmallett info.enable_mask = 1ull<<1 /* intr_sec_ena */; 4173215976Sjmallett info.flags = CVMX_ERROR_FLAGS_ECC_SINGLE_BIT; 4174215976Sjmallett info.group = CVMX_ERROR_GROUP_LMC; 4175215976Sjmallett info.group_index = 0; 4176215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4177215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 4178215976Sjmallett info.parent.status_mask = 1ull<<17 /* lmc0 */; 4179215976Sjmallett info.func = __cvmx_error_display; 4180215976Sjmallett info.user_info = (long) 4181215976Sjmallett "ERROR LMCX_INT(0)[SEC_ERR]: Single Error (corrected) of Rd Data\n" 4182215976Sjmallett " [0] corresponds to DQ[63:0]_c0_p0\n" 4183215976Sjmallett " [1] corresponds to DQ[63:0]_c0_p1\n" 4184215976Sjmallett " [2] corresponds to DQ[63:0]_c1_p0\n" 4185215976Sjmallett " [3] corresponds to DQ[63:0]_c1_p1\n" 4186215976Sjmallett " where _cC_pP denotes cycle C and phase P\n" 4187215976Sjmallett " Write of 1 will clear the corresponding error bit\n"; 4188215976Sjmallett fail |= cvmx_error_add(&info); 4189215976Sjmallett 4190215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4191215976Sjmallett info.status_addr = CVMX_LMCX_INT(0); 4192215976Sjmallett info.status_mask = 1ull<<0 /* nxm_wr_err */; 4193215976Sjmallett info.enable_addr = CVMX_LMCX_INT_EN(0); 4194215976Sjmallett info.enable_mask = 1ull<<0 /* intr_nxm_wr_ena */; 4195215976Sjmallett info.flags = 0; 4196215976Sjmallett info.group = CVMX_ERROR_GROUP_LMC; 4197215976Sjmallett info.group_index = 0; 4198215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4199215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 4200215976Sjmallett info.parent.status_mask = 1ull<<17 /* lmc0 */; 4201215976Sjmallett info.func = __cvmx_error_display; 4202215976Sjmallett info.user_info = (long) 4203215976Sjmallett "ERROR LMCX_INT(0)[NXM_WR_ERR]: Write to non-existent memory\n" 4204215976Sjmallett " Write of 1 will clear the corresponding error bit\n"; 4205215976Sjmallett fail |= cvmx_error_add(&info); 4206215976Sjmallett 4207215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4208215976Sjmallett info.status_addr = CVMX_LMCX_INT(0); 4209215976Sjmallett info.status_mask = 0xfull<<5 /* ded_err */; 4210215976Sjmallett info.enable_addr = CVMX_LMCX_INT_EN(0); 4211215976Sjmallett info.enable_mask = 1ull<<2 /* intr_ded_ena */; 4212215976Sjmallett info.flags = 0; 4213215976Sjmallett info.group = CVMX_ERROR_GROUP_LMC; 4214215976Sjmallett info.group_index = 0; 4215215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4216215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 4217215976Sjmallett info.parent.status_mask = 1ull<<17 /* lmc0 */; 4218215976Sjmallett info.func = __cvmx_error_display; 4219215976Sjmallett info.user_info = (long) 4220215976Sjmallett "ERROR LMCX_INT(0)[DED_ERR]: Double Error detected (DED) of Rd Data\n" 4221215976Sjmallett " [0] corresponds to DQ[63:0]_c0_p0\n" 4222215976Sjmallett " [1] corresponds to DQ[63:0]_c0_p1\n" 4223215976Sjmallett " [2] corresponds to DQ[63:0]_c1_p0\n" 4224215976Sjmallett " [3] corresponds to DQ[63:0]_c1_p1\n" 4225215976Sjmallett " where _cC_pP denotes cycle C and phase P\n" 4226215976Sjmallett " Write of 1 will clear the corresponding error bit\n"; 4227215976Sjmallett fail |= cvmx_error_add(&info); 4228215976Sjmallett 4229215976Sjmallett /* CVMX_KEY_INT_SUM */ 4230215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4231215976Sjmallett info.status_addr = CVMX_KEY_INT_SUM; 4232215976Sjmallett info.status_mask = 1ull<<0 /* ked0_sbe */; 4233215976Sjmallett info.enable_addr = CVMX_KEY_INT_ENB; 4234215976Sjmallett info.enable_mask = 1ull<<0 /* ked0_sbe */; 4235215976Sjmallett info.flags = 0; 4236215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 4237215976Sjmallett info.group_index = 0; 4238215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4239215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 4240215976Sjmallett info.parent.status_mask = 1ull<<4 /* key */; 4241215976Sjmallett info.func = __cvmx_error_display; 4242215976Sjmallett info.user_info = (long) 4243215976Sjmallett "ERROR KEY_INT_SUM[KED0_SBE]: Error Bit\n" 4244215976Sjmallett; 4245215976Sjmallett fail |= cvmx_error_add(&info); 4246215976Sjmallett 4247215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4248215976Sjmallett info.status_addr = CVMX_KEY_INT_SUM; 4249215976Sjmallett info.status_mask = 1ull<<1 /* ked0_dbe */; 4250215976Sjmallett info.enable_addr = CVMX_KEY_INT_ENB; 4251215976Sjmallett info.enable_mask = 1ull<<1 /* ked0_dbe */; 4252215976Sjmallett info.flags = 0; 4253215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 4254215976Sjmallett info.group_index = 0; 4255215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4256215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 4257215976Sjmallett info.parent.status_mask = 1ull<<4 /* key */; 4258215976Sjmallett info.func = __cvmx_error_display; 4259215976Sjmallett info.user_info = (long) 4260215976Sjmallett "ERROR KEY_INT_SUM[KED0_DBE]: Error Bit\n" 4261215976Sjmallett; 4262215976Sjmallett fail |= cvmx_error_add(&info); 4263215976Sjmallett 4264215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4265215976Sjmallett info.status_addr = CVMX_KEY_INT_SUM; 4266215976Sjmallett info.status_mask = 1ull<<2 /* ked1_sbe */; 4267215976Sjmallett info.enable_addr = CVMX_KEY_INT_ENB; 4268215976Sjmallett info.enable_mask = 1ull<<2 /* ked1_sbe */; 4269215976Sjmallett info.flags = 0; 4270215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 4271215976Sjmallett info.group_index = 0; 4272215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4273215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 4274215976Sjmallett info.parent.status_mask = 1ull<<4 /* key */; 4275215976Sjmallett info.func = __cvmx_error_display; 4276215976Sjmallett info.user_info = (long) 4277215976Sjmallett "ERROR KEY_INT_SUM[KED1_SBE]: Error Bit\n" 4278215976Sjmallett; 4279215976Sjmallett fail |= cvmx_error_add(&info); 4280215976Sjmallett 4281215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4282215976Sjmallett info.status_addr = CVMX_KEY_INT_SUM; 4283215976Sjmallett info.status_mask = 1ull<<3 /* ked1_dbe */; 4284215976Sjmallett info.enable_addr = CVMX_KEY_INT_ENB; 4285215976Sjmallett info.enable_mask = 1ull<<3 /* ked1_dbe */; 4286215976Sjmallett info.flags = 0; 4287215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 4288215976Sjmallett info.group_index = 0; 4289215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4290215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 4291215976Sjmallett info.parent.status_mask = 1ull<<4 /* key */; 4292215976Sjmallett info.func = __cvmx_error_display; 4293215976Sjmallett info.user_info = (long) 4294215976Sjmallett "ERROR KEY_INT_SUM[KED1_DBE]: Error Bit\n" 4295215976Sjmallett; 4296215976Sjmallett fail |= cvmx_error_add(&info); 4297215976Sjmallett 4298215976Sjmallett /* CVMX_GMXX_BAD_REG(0) */ 4299215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4300215976Sjmallett info.status_addr = CVMX_GMXX_BAD_REG(0); 4301215976Sjmallett info.status_mask = 0xfull<<2 /* out_ovr */; 4302215976Sjmallett info.enable_addr = 0; 4303215976Sjmallett info.enable_mask = 0; 4304215976Sjmallett info.flags = 0; 4305215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4306215976Sjmallett info.group_index = 0; 4307215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4308215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 4309215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 4310215976Sjmallett info.func = __cvmx_error_display; 4311215976Sjmallett info.user_info = (long) 4312215976Sjmallett "ERROR GMXX_BAD_REG(0)[OUT_OVR]: Outbound data FIFO overflow (per port)\n"; 4313215976Sjmallett fail |= cvmx_error_add(&info); 4314215976Sjmallett 4315215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4316215976Sjmallett info.status_addr = CVMX_GMXX_BAD_REG(0); 4317215976Sjmallett info.status_mask = 0xfull<<22 /* loststat */; 4318215976Sjmallett info.enable_addr = 0; 4319215976Sjmallett info.enable_mask = 0; 4320215976Sjmallett info.flags = 0; 4321215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4322215976Sjmallett info.group_index = 0; 4323215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4324215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 4325215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 4326215976Sjmallett info.func = __cvmx_error_display; 4327215976Sjmallett info.user_info = (long) 4328215976Sjmallett "ERROR GMXX_BAD_REG(0)[LOSTSTAT]: TX Statistics data was over-written\n" 4329215976Sjmallett " In SGMII, one bit per port\n" 4330215976Sjmallett " In XAUI, only port0 is used\n" 4331215976Sjmallett " TX Stats are corrupted\n"; 4332215976Sjmallett fail |= cvmx_error_add(&info); 4333215976Sjmallett 4334215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4335215976Sjmallett info.status_addr = CVMX_GMXX_BAD_REG(0); 4336215976Sjmallett info.status_mask = 1ull<<26 /* statovr */; 4337215976Sjmallett info.enable_addr = 0; 4338215976Sjmallett info.enable_mask = 0; 4339215976Sjmallett info.flags = 0; 4340215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4341215976Sjmallett info.group_index = 0; 4342215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4343215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 4344215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 4345215976Sjmallett info.func = __cvmx_error_display; 4346215976Sjmallett info.user_info = (long) 4347215976Sjmallett "ERROR GMXX_BAD_REG(0)[STATOVR]: TX Statistics overflow\n" 4348215976Sjmallett " The common FIFO to SGMII and XAUI had an overflow\n" 4349215976Sjmallett " TX Stats are corrupted\n"; 4350215976Sjmallett fail |= cvmx_error_add(&info); 4351215976Sjmallett 4352215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4353215976Sjmallett info.status_addr = CVMX_GMXX_BAD_REG(0); 4354215976Sjmallett info.status_mask = 0xfull<<27 /* inb_nxa */; 4355215976Sjmallett info.enable_addr = 0; 4356215976Sjmallett info.enable_mask = 0; 4357215976Sjmallett info.flags = 0; 4358215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4359215976Sjmallett info.group_index = 0; 4360215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4361215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 4362215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 4363215976Sjmallett info.func = __cvmx_error_display; 4364215976Sjmallett info.user_info = (long) 4365215976Sjmallett "ERROR GMXX_BAD_REG(0)[INB_NXA]: Inbound port > GMX_RX_PRTS\n"; 4366215976Sjmallett fail |= cvmx_error_add(&info); 4367215976Sjmallett 4368215976Sjmallett /* CVMX_GMXX_RXX_INT_REG(0,0) */ 4369215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4370215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0); 4371215976Sjmallett info.status_mask = 1ull<<1 /* carext */; 4372215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0); 4373215976Sjmallett info.enable_mask = 1ull<<1 /* carext */; 4374215976Sjmallett info.flags = 0; 4375215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4376215976Sjmallett info.group_index = 0; 4377215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4378215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 4379215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 4380215976Sjmallett info.func = __cvmx_error_display; 4381215976Sjmallett info.user_info = (long) 4382215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,0)[CAREXT]: Carrier extend error\n" 4383215976Sjmallett " (SGMII/1000Base-X only)\n"; 4384215976Sjmallett fail |= cvmx_error_add(&info); 4385215976Sjmallett 4386215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4387215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0); 4388215976Sjmallett info.status_mask = 1ull<<8 /* skperr */; 4389215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0); 4390215976Sjmallett info.enable_mask = 1ull<<8 /* skperr */; 4391215976Sjmallett info.flags = 0; 4392215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4393215976Sjmallett info.group_index = 0; 4394215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4395215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 4396215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 4397215976Sjmallett info.func = __cvmx_error_display; 4398215976Sjmallett info.user_info = (long) 4399215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,0)[SKPERR]: Skipper error\n"; 4400215976Sjmallett fail |= cvmx_error_add(&info); 4401215976Sjmallett 4402215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4403215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0); 4404215976Sjmallett info.status_mask = 1ull<<10 /* ovrerr */; 4405215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0); 4406215976Sjmallett info.enable_mask = 1ull<<10 /* ovrerr */; 4407215976Sjmallett info.flags = 0; 4408215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4409215976Sjmallett info.group_index = 0; 4410215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4411215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 4412215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 4413215976Sjmallett info.func = __cvmx_error_display; 4414215976Sjmallett info.user_info = (long) 4415215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,0)[OVRERR]: Internal Data Aggregation Overflow\n" 4416215976Sjmallett " This interrupt should never assert\n" 4417215976Sjmallett " (SGMII/1000Base-X only)\n"; 4418215976Sjmallett fail |= cvmx_error_add(&info); 4419215976Sjmallett 4420215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4421215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0); 4422215976Sjmallett info.status_mask = 1ull<<20 /* loc_fault */; 4423215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0); 4424215976Sjmallett info.enable_mask = 1ull<<20 /* loc_fault */; 4425215976Sjmallett info.flags = 0; 4426215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4427215976Sjmallett info.group_index = 0; 4428215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4429215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 4430215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 4431215976Sjmallett info.func = __cvmx_error_display; 4432215976Sjmallett info.user_info = (long) 4433215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,0)[LOC_FAULT]: Local Fault Sequence Deteted\n" 4434215976Sjmallett " (XAUI Mode only)\n"; 4435215976Sjmallett fail |= cvmx_error_add(&info); 4436215976Sjmallett 4437215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4438215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0); 4439215976Sjmallett info.status_mask = 1ull<<21 /* rem_fault */; 4440215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0); 4441215976Sjmallett info.enable_mask = 1ull<<21 /* rem_fault */; 4442215976Sjmallett info.flags = 0; 4443215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4444215976Sjmallett info.group_index = 0; 4445215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4446215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 4447215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 4448215976Sjmallett info.func = __cvmx_error_display; 4449215976Sjmallett info.user_info = (long) 4450215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,0)[REM_FAULT]: Remote Fault Sequence Deteted\n" 4451215976Sjmallett " (XAUI Mode only)\n"; 4452215976Sjmallett fail |= cvmx_error_add(&info); 4453215976Sjmallett 4454215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4455215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0); 4456215976Sjmallett info.status_mask = 1ull<<22 /* bad_seq */; 4457215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0); 4458215976Sjmallett info.enable_mask = 1ull<<22 /* bad_seq */; 4459215976Sjmallett info.flags = 0; 4460215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4461215976Sjmallett info.group_index = 0; 4462215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4463215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 4464215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 4465215976Sjmallett info.func = __cvmx_error_display; 4466215976Sjmallett info.user_info = (long) 4467215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,0)[BAD_SEQ]: Reserved Sequence Deteted\n" 4468215976Sjmallett " (XAUI Mode only)\n"; 4469215976Sjmallett fail |= cvmx_error_add(&info); 4470215976Sjmallett 4471215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4472215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0); 4473215976Sjmallett info.status_mask = 1ull<<23 /* bad_term */; 4474215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0); 4475215976Sjmallett info.enable_mask = 1ull<<23 /* bad_term */; 4476215976Sjmallett info.flags = 0; 4477215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4478215976Sjmallett info.group_index = 0; 4479215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4480215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 4481215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 4482215976Sjmallett info.func = __cvmx_error_display; 4483215976Sjmallett info.user_info = (long) 4484215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,0)[BAD_TERM]: Frame is terminated by control character other\n" 4485215976Sjmallett " than /T/. The error propagation control\n" 4486215976Sjmallett " character /E/ will be included as part of the\n" 4487215976Sjmallett " frame and does not cause a frame termination.\n" 4488215976Sjmallett " (XAUI Mode only)\n"; 4489215976Sjmallett fail |= cvmx_error_add(&info); 4490215976Sjmallett 4491215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4492215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0); 4493215976Sjmallett info.status_mask = 1ull<<24 /* unsop */; 4494215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0); 4495215976Sjmallett info.enable_mask = 1ull<<24 /* unsop */; 4496215976Sjmallett info.flags = 0; 4497215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4498215976Sjmallett info.group_index = 0; 4499215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4500215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 4501215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 4502215976Sjmallett info.func = __cvmx_error_display; 4503215976Sjmallett info.user_info = (long) 4504215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,0)[UNSOP]: Unexpected SOP\n" 4505215976Sjmallett " (XAUI Mode only)\n"; 4506215976Sjmallett fail |= cvmx_error_add(&info); 4507215976Sjmallett 4508215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4509215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0); 4510215976Sjmallett info.status_mask = 1ull<<25 /* uneop */; 4511215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0); 4512215976Sjmallett info.enable_mask = 1ull<<25 /* uneop */; 4513215976Sjmallett info.flags = 0; 4514215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4515215976Sjmallett info.group_index = 0; 4516215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4517215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 4518215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 4519215976Sjmallett info.func = __cvmx_error_display; 4520215976Sjmallett info.user_info = (long) 4521215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,0)[UNEOP]: Unexpected EOP\n" 4522215976Sjmallett " (XAUI Mode only)\n"; 4523215976Sjmallett fail |= cvmx_error_add(&info); 4524215976Sjmallett 4525215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4526215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0); 4527215976Sjmallett info.status_mask = 1ull<<26 /* undat */; 4528215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0); 4529215976Sjmallett info.enable_mask = 1ull<<26 /* undat */; 4530215976Sjmallett info.flags = 0; 4531215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4532215976Sjmallett info.group_index = 0; 4533215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4534215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 4535215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 4536215976Sjmallett info.func = __cvmx_error_display; 4537215976Sjmallett info.user_info = (long) 4538215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,0)[UNDAT]: Unexpected Data\n" 4539215976Sjmallett " (XAUI Mode only)\n"; 4540215976Sjmallett fail |= cvmx_error_add(&info); 4541215976Sjmallett 4542215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4543215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0); 4544215976Sjmallett info.status_mask = 1ull<<27 /* hg2fld */; 4545215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0); 4546215976Sjmallett info.enable_mask = 1ull<<27 /* hg2fld */; 4547215976Sjmallett info.flags = 0; 4548215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4549215976Sjmallett info.group_index = 0; 4550215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4551215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 4552215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 4553215976Sjmallett info.func = __cvmx_error_display; 4554215976Sjmallett info.user_info = (long) 4555215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,0)[HG2FLD]: HiGig2 received message field error, as below\n" 4556215976Sjmallett " 1) MSG_TYPE field not 6'b00_0000\n" 4557215976Sjmallett " i.e. it is not a FLOW CONTROL message, which\n" 4558215976Sjmallett " is the only defined type for HiGig2\n" 4559215976Sjmallett " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n" 4560215976Sjmallett " which is the only defined type for HiGig2\n" 4561215976Sjmallett " 3) FC_OBJECT field is neither 4'b0000 for\n" 4562215976Sjmallett " Physical Link nor 4'b0010 for Logical Link.\n" 4563215976Sjmallett " Those are the only two defined types in HiGig2\n"; 4564215976Sjmallett fail |= cvmx_error_add(&info); 4565215976Sjmallett 4566215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4567215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(0,0); 4568215976Sjmallett info.status_mask = 1ull<<28 /* hg2cc */; 4569215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(0,0); 4570215976Sjmallett info.enable_mask = 1ull<<28 /* hg2cc */; 4571215976Sjmallett info.flags = 0; 4572215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4573215976Sjmallett info.group_index = 0; 4574215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4575215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 4576215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 4577215976Sjmallett info.func = __cvmx_error_display; 4578215976Sjmallett info.user_info = (long) 4579215976Sjmallett "ERROR GMXX_RXX_INT_REG(0,0)[HG2CC]: HiGig2 received message CRC or Control char error\n" 4580215976Sjmallett " Set when either CRC8 error detected or when\n" 4581215976Sjmallett " a Control Character is found in the message\n" 4582215976Sjmallett " bytes after the K.SOM\n" 4583215976Sjmallett " NOTE: HG2CC has higher priority than HG2FLD\n" 4584215976Sjmallett " i.e. a HiGig2 message that results in HG2CC\n" 4585215976Sjmallett " getting set, will never set HG2FLD.\n"; 4586215976Sjmallett fail |= cvmx_error_add(&info); 4587215976Sjmallett 4588215976Sjmallett /* CVMX_GMXX_RXX_INT_REG(1,0) */ 4589215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4590215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0); 4591215976Sjmallett info.status_mask = 1ull<<1 /* carext */; 4592215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0); 4593215976Sjmallett info.enable_mask = 1ull<<1 /* carext */; 4594215976Sjmallett info.flags = 0; 4595215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4596215976Sjmallett info.group_index = 1; 4597215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4598215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 4599215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 4600215976Sjmallett info.func = __cvmx_error_display; 4601215976Sjmallett info.user_info = (long) 4602215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,0)[CAREXT]: Carrier extend error\n" 4603215976Sjmallett " (SGMII/1000Base-X only)\n"; 4604215976Sjmallett fail |= cvmx_error_add(&info); 4605215976Sjmallett 4606215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4607215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0); 4608215976Sjmallett info.status_mask = 1ull<<8 /* skperr */; 4609215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0); 4610215976Sjmallett info.enable_mask = 1ull<<8 /* skperr */; 4611215976Sjmallett info.flags = 0; 4612215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4613215976Sjmallett info.group_index = 1; 4614215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4615215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 4616215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 4617215976Sjmallett info.func = __cvmx_error_display; 4618215976Sjmallett info.user_info = (long) 4619215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,0)[SKPERR]: Skipper error\n"; 4620215976Sjmallett fail |= cvmx_error_add(&info); 4621215976Sjmallett 4622215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4623215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0); 4624215976Sjmallett info.status_mask = 1ull<<10 /* ovrerr */; 4625215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0); 4626215976Sjmallett info.enable_mask = 1ull<<10 /* ovrerr */; 4627215976Sjmallett info.flags = 0; 4628215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4629215976Sjmallett info.group_index = 1; 4630215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4631215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 4632215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 4633215976Sjmallett info.func = __cvmx_error_display; 4634215976Sjmallett info.user_info = (long) 4635215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,0)[OVRERR]: Internal Data Aggregation Overflow\n" 4636215976Sjmallett " This interrupt should never assert\n" 4637215976Sjmallett " (SGMII/1000Base-X only)\n"; 4638215976Sjmallett fail |= cvmx_error_add(&info); 4639215976Sjmallett 4640215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4641215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0); 4642215976Sjmallett info.status_mask = 1ull<<20 /* loc_fault */; 4643215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0); 4644215976Sjmallett info.enable_mask = 1ull<<20 /* loc_fault */; 4645215976Sjmallett info.flags = 0; 4646215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4647215976Sjmallett info.group_index = 1; 4648215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4649215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 4650215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 4651215976Sjmallett info.func = __cvmx_error_display; 4652215976Sjmallett info.user_info = (long) 4653215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,0)[LOC_FAULT]: Local Fault Sequence Deteted\n" 4654215976Sjmallett " (XAUI Mode only)\n"; 4655215976Sjmallett fail |= cvmx_error_add(&info); 4656215976Sjmallett 4657215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4658215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0); 4659215976Sjmallett info.status_mask = 1ull<<21 /* rem_fault */; 4660215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0); 4661215976Sjmallett info.enable_mask = 1ull<<21 /* rem_fault */; 4662215976Sjmallett info.flags = 0; 4663215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4664215976Sjmallett info.group_index = 1; 4665215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4666215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 4667215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 4668215976Sjmallett info.func = __cvmx_error_display; 4669215976Sjmallett info.user_info = (long) 4670215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,0)[REM_FAULT]: Remote Fault Sequence Deteted\n" 4671215976Sjmallett " (XAUI Mode only)\n"; 4672215976Sjmallett fail |= cvmx_error_add(&info); 4673215976Sjmallett 4674215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4675215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0); 4676215976Sjmallett info.status_mask = 1ull<<22 /* bad_seq */; 4677215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0); 4678215976Sjmallett info.enable_mask = 1ull<<22 /* bad_seq */; 4679215976Sjmallett info.flags = 0; 4680215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4681215976Sjmallett info.group_index = 1; 4682215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4683215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 4684215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 4685215976Sjmallett info.func = __cvmx_error_display; 4686215976Sjmallett info.user_info = (long) 4687215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,0)[BAD_SEQ]: Reserved Sequence Deteted\n" 4688215976Sjmallett " (XAUI Mode only)\n"; 4689215976Sjmallett fail |= cvmx_error_add(&info); 4690215976Sjmallett 4691215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4692215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0); 4693215976Sjmallett info.status_mask = 1ull<<23 /* bad_term */; 4694215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0); 4695215976Sjmallett info.enable_mask = 1ull<<23 /* bad_term */; 4696215976Sjmallett info.flags = 0; 4697215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4698215976Sjmallett info.group_index = 1; 4699215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4700215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 4701215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 4702215976Sjmallett info.func = __cvmx_error_display; 4703215976Sjmallett info.user_info = (long) 4704215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,0)[BAD_TERM]: Frame is terminated by control character other\n" 4705215976Sjmallett " than /T/. The error propagation control\n" 4706215976Sjmallett " character /E/ will be included as part of the\n" 4707215976Sjmallett " frame and does not cause a frame termination.\n" 4708215976Sjmallett " (XAUI Mode only)\n"; 4709215976Sjmallett fail |= cvmx_error_add(&info); 4710215976Sjmallett 4711215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4712215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0); 4713215976Sjmallett info.status_mask = 1ull<<24 /* unsop */; 4714215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0); 4715215976Sjmallett info.enable_mask = 1ull<<24 /* unsop */; 4716215976Sjmallett info.flags = 0; 4717215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4718215976Sjmallett info.group_index = 1; 4719215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4720215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 4721215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 4722215976Sjmallett info.func = __cvmx_error_display; 4723215976Sjmallett info.user_info = (long) 4724215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,0)[UNSOP]: Unexpected SOP\n" 4725215976Sjmallett " (XAUI Mode only)\n"; 4726215976Sjmallett fail |= cvmx_error_add(&info); 4727215976Sjmallett 4728215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4729215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0); 4730215976Sjmallett info.status_mask = 1ull<<25 /* uneop */; 4731215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0); 4732215976Sjmallett info.enable_mask = 1ull<<25 /* uneop */; 4733215976Sjmallett info.flags = 0; 4734215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4735215976Sjmallett info.group_index = 1; 4736215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4737215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 4738215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 4739215976Sjmallett info.func = __cvmx_error_display; 4740215976Sjmallett info.user_info = (long) 4741215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,0)[UNEOP]: Unexpected EOP\n" 4742215976Sjmallett " (XAUI Mode only)\n"; 4743215976Sjmallett fail |= cvmx_error_add(&info); 4744215976Sjmallett 4745215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4746215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0); 4747215976Sjmallett info.status_mask = 1ull<<26 /* undat */; 4748215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0); 4749215976Sjmallett info.enable_mask = 1ull<<26 /* undat */; 4750215976Sjmallett info.flags = 0; 4751215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4752215976Sjmallett info.group_index = 1; 4753215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4754215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 4755215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 4756215976Sjmallett info.func = __cvmx_error_display; 4757215976Sjmallett info.user_info = (long) 4758215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,0)[UNDAT]: Unexpected Data\n" 4759215976Sjmallett " (XAUI Mode only)\n"; 4760215976Sjmallett fail |= cvmx_error_add(&info); 4761215976Sjmallett 4762215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4763215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0); 4764215976Sjmallett info.status_mask = 1ull<<27 /* hg2fld */; 4765215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0); 4766215976Sjmallett info.enable_mask = 1ull<<27 /* hg2fld */; 4767215976Sjmallett info.flags = 0; 4768215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4769215976Sjmallett info.group_index = 1; 4770215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4771215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 4772215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 4773215976Sjmallett info.func = __cvmx_error_display; 4774215976Sjmallett info.user_info = (long) 4775215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,0)[HG2FLD]: HiGig2 received message field error, as below\n" 4776215976Sjmallett " 1) MSG_TYPE field not 6'b00_0000\n" 4777215976Sjmallett " i.e. it is not a FLOW CONTROL message, which\n" 4778215976Sjmallett " is the only defined type for HiGig2\n" 4779215976Sjmallett " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n" 4780215976Sjmallett " which is the only defined type for HiGig2\n" 4781215976Sjmallett " 3) FC_OBJECT field is neither 4'b0000 for\n" 4782215976Sjmallett " Physical Link nor 4'b0010 for Logical Link.\n" 4783215976Sjmallett " Those are the only two defined types in HiGig2\n"; 4784215976Sjmallett fail |= cvmx_error_add(&info); 4785215976Sjmallett 4786215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4787215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(1,0); 4788215976Sjmallett info.status_mask = 1ull<<28 /* hg2cc */; 4789215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(1,0); 4790215976Sjmallett info.enable_mask = 1ull<<28 /* hg2cc */; 4791215976Sjmallett info.flags = 0; 4792215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4793215976Sjmallett info.group_index = 1; 4794215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4795215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 4796215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 4797215976Sjmallett info.func = __cvmx_error_display; 4798215976Sjmallett info.user_info = (long) 4799215976Sjmallett "ERROR GMXX_RXX_INT_REG(1,0)[HG2CC]: HiGig2 received message CRC or Control char error\n" 4800215976Sjmallett " Set when either CRC8 error detected or when\n" 4801215976Sjmallett " a Control Character is found in the message\n" 4802215976Sjmallett " bytes after the K.SOM\n" 4803215976Sjmallett " NOTE: HG2CC has higher priority than HG2FLD\n" 4804215976Sjmallett " i.e. a HiGig2 message that results in HG2CC\n" 4805215976Sjmallett " getting set, will never set HG2FLD.\n"; 4806215976Sjmallett fail |= cvmx_error_add(&info); 4807215976Sjmallett 4808215976Sjmallett /* CVMX_GMXX_RXX_INT_REG(2,0) */ 4809215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4810215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0); 4811215976Sjmallett info.status_mask = 1ull<<1 /* carext */; 4812215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0); 4813215976Sjmallett info.enable_mask = 1ull<<1 /* carext */; 4814215976Sjmallett info.flags = 0; 4815215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4816215976Sjmallett info.group_index = 2; 4817215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4818215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 4819215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 4820215976Sjmallett info.func = __cvmx_error_display; 4821215976Sjmallett info.user_info = (long) 4822215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,0)[CAREXT]: Carrier extend error\n" 4823215976Sjmallett " (SGMII/1000Base-X only)\n"; 4824215976Sjmallett fail |= cvmx_error_add(&info); 4825215976Sjmallett 4826215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4827215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0); 4828215976Sjmallett info.status_mask = 1ull<<8 /* skperr */; 4829215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0); 4830215976Sjmallett info.enable_mask = 1ull<<8 /* skperr */; 4831215976Sjmallett info.flags = 0; 4832215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4833215976Sjmallett info.group_index = 2; 4834215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4835215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 4836215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 4837215976Sjmallett info.func = __cvmx_error_display; 4838215976Sjmallett info.user_info = (long) 4839215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,0)[SKPERR]: Skipper error\n"; 4840215976Sjmallett fail |= cvmx_error_add(&info); 4841215976Sjmallett 4842215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4843215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0); 4844215976Sjmallett info.status_mask = 1ull<<10 /* ovrerr */; 4845215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0); 4846215976Sjmallett info.enable_mask = 1ull<<10 /* ovrerr */; 4847215976Sjmallett info.flags = 0; 4848215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4849215976Sjmallett info.group_index = 2; 4850215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4851215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 4852215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 4853215976Sjmallett info.func = __cvmx_error_display; 4854215976Sjmallett info.user_info = (long) 4855215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,0)[OVRERR]: Internal Data Aggregation Overflow\n" 4856215976Sjmallett " This interrupt should never assert\n" 4857215976Sjmallett " (SGMII/1000Base-X only)\n"; 4858215976Sjmallett fail |= cvmx_error_add(&info); 4859215976Sjmallett 4860215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4861215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0); 4862215976Sjmallett info.status_mask = 1ull<<20 /* loc_fault */; 4863215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0); 4864215976Sjmallett info.enable_mask = 1ull<<20 /* loc_fault */; 4865215976Sjmallett info.flags = 0; 4866215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4867215976Sjmallett info.group_index = 2; 4868215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4869215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 4870215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 4871215976Sjmallett info.func = __cvmx_error_display; 4872215976Sjmallett info.user_info = (long) 4873215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,0)[LOC_FAULT]: Local Fault Sequence Deteted\n" 4874215976Sjmallett " (XAUI Mode only)\n"; 4875215976Sjmallett fail |= cvmx_error_add(&info); 4876215976Sjmallett 4877215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4878215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0); 4879215976Sjmallett info.status_mask = 1ull<<21 /* rem_fault */; 4880215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0); 4881215976Sjmallett info.enable_mask = 1ull<<21 /* rem_fault */; 4882215976Sjmallett info.flags = 0; 4883215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4884215976Sjmallett info.group_index = 2; 4885215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4886215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 4887215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 4888215976Sjmallett info.func = __cvmx_error_display; 4889215976Sjmallett info.user_info = (long) 4890215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,0)[REM_FAULT]: Remote Fault Sequence Deteted\n" 4891215976Sjmallett " (XAUI Mode only)\n"; 4892215976Sjmallett fail |= cvmx_error_add(&info); 4893215976Sjmallett 4894215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4895215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0); 4896215976Sjmallett info.status_mask = 1ull<<22 /* bad_seq */; 4897215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0); 4898215976Sjmallett info.enable_mask = 1ull<<22 /* bad_seq */; 4899215976Sjmallett info.flags = 0; 4900215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4901215976Sjmallett info.group_index = 2; 4902215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4903215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 4904215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 4905215976Sjmallett info.func = __cvmx_error_display; 4906215976Sjmallett info.user_info = (long) 4907215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,0)[BAD_SEQ]: Reserved Sequence Deteted\n" 4908215976Sjmallett " (XAUI Mode only)\n"; 4909215976Sjmallett fail |= cvmx_error_add(&info); 4910215976Sjmallett 4911215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4912215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0); 4913215976Sjmallett info.status_mask = 1ull<<23 /* bad_term */; 4914215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0); 4915215976Sjmallett info.enable_mask = 1ull<<23 /* bad_term */; 4916215976Sjmallett info.flags = 0; 4917215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4918215976Sjmallett info.group_index = 2; 4919215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4920215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 4921215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 4922215976Sjmallett info.func = __cvmx_error_display; 4923215976Sjmallett info.user_info = (long) 4924215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,0)[BAD_TERM]: Frame is terminated by control character other\n" 4925215976Sjmallett " than /T/. The error propagation control\n" 4926215976Sjmallett " character /E/ will be included as part of the\n" 4927215976Sjmallett " frame and does not cause a frame termination.\n" 4928215976Sjmallett " (XAUI Mode only)\n"; 4929215976Sjmallett fail |= cvmx_error_add(&info); 4930215976Sjmallett 4931215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4932215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0); 4933215976Sjmallett info.status_mask = 1ull<<24 /* unsop */; 4934215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0); 4935215976Sjmallett info.enable_mask = 1ull<<24 /* unsop */; 4936215976Sjmallett info.flags = 0; 4937215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4938215976Sjmallett info.group_index = 2; 4939215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4940215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 4941215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 4942215976Sjmallett info.func = __cvmx_error_display; 4943215976Sjmallett info.user_info = (long) 4944215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,0)[UNSOP]: Unexpected SOP\n" 4945215976Sjmallett " (XAUI Mode only)\n"; 4946215976Sjmallett fail |= cvmx_error_add(&info); 4947215976Sjmallett 4948215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4949215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0); 4950215976Sjmallett info.status_mask = 1ull<<25 /* uneop */; 4951215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0); 4952215976Sjmallett info.enable_mask = 1ull<<25 /* uneop */; 4953215976Sjmallett info.flags = 0; 4954215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4955215976Sjmallett info.group_index = 2; 4956215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4957215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 4958215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 4959215976Sjmallett info.func = __cvmx_error_display; 4960215976Sjmallett info.user_info = (long) 4961215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,0)[UNEOP]: Unexpected EOP\n" 4962215976Sjmallett " (XAUI Mode only)\n"; 4963215976Sjmallett fail |= cvmx_error_add(&info); 4964215976Sjmallett 4965215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4966215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0); 4967215976Sjmallett info.status_mask = 1ull<<26 /* undat */; 4968215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0); 4969215976Sjmallett info.enable_mask = 1ull<<26 /* undat */; 4970215976Sjmallett info.flags = 0; 4971215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4972215976Sjmallett info.group_index = 2; 4973215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4974215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 4975215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 4976215976Sjmallett info.func = __cvmx_error_display; 4977215976Sjmallett info.user_info = (long) 4978215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,0)[UNDAT]: Unexpected Data\n" 4979215976Sjmallett " (XAUI Mode only)\n"; 4980215976Sjmallett fail |= cvmx_error_add(&info); 4981215976Sjmallett 4982215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 4983215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0); 4984215976Sjmallett info.status_mask = 1ull<<27 /* hg2fld */; 4985215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0); 4986215976Sjmallett info.enable_mask = 1ull<<27 /* hg2fld */; 4987215976Sjmallett info.flags = 0; 4988215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 4989215976Sjmallett info.group_index = 2; 4990215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 4991215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 4992215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 4993215976Sjmallett info.func = __cvmx_error_display; 4994215976Sjmallett info.user_info = (long) 4995215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,0)[HG2FLD]: HiGig2 received message field error, as below\n" 4996215976Sjmallett " 1) MSG_TYPE field not 6'b00_0000\n" 4997215976Sjmallett " i.e. it is not a FLOW CONTROL message, which\n" 4998215976Sjmallett " is the only defined type for HiGig2\n" 4999215976Sjmallett " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n" 5000215976Sjmallett " which is the only defined type for HiGig2\n" 5001215976Sjmallett " 3) FC_OBJECT field is neither 4'b0000 for\n" 5002215976Sjmallett " Physical Link nor 4'b0010 for Logical Link.\n" 5003215976Sjmallett " Those are the only two defined types in HiGig2\n"; 5004215976Sjmallett fail |= cvmx_error_add(&info); 5005215976Sjmallett 5006215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5007215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(2,0); 5008215976Sjmallett info.status_mask = 1ull<<28 /* hg2cc */; 5009215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(2,0); 5010215976Sjmallett info.enable_mask = 1ull<<28 /* hg2cc */; 5011215976Sjmallett info.flags = 0; 5012215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5013215976Sjmallett info.group_index = 2; 5014215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5015215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 5016215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 5017215976Sjmallett info.func = __cvmx_error_display; 5018215976Sjmallett info.user_info = (long) 5019215976Sjmallett "ERROR GMXX_RXX_INT_REG(2,0)[HG2CC]: HiGig2 received message CRC or Control char error\n" 5020215976Sjmallett " Set when either CRC8 error detected or when\n" 5021215976Sjmallett " a Control Character is found in the message\n" 5022215976Sjmallett " bytes after the K.SOM\n" 5023215976Sjmallett " NOTE: HG2CC has higher priority than HG2FLD\n" 5024215976Sjmallett " i.e. a HiGig2 message that results in HG2CC\n" 5025215976Sjmallett " getting set, will never set HG2FLD.\n"; 5026215976Sjmallett fail |= cvmx_error_add(&info); 5027215976Sjmallett 5028215976Sjmallett /* CVMX_GMXX_RXX_INT_REG(3,0) */ 5029215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5030215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0); 5031215976Sjmallett info.status_mask = 1ull<<1 /* carext */; 5032215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0); 5033215976Sjmallett info.enable_mask = 1ull<<1 /* carext */; 5034215976Sjmallett info.flags = 0; 5035215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5036215976Sjmallett info.group_index = 3; 5037215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5038215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 5039215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 5040215976Sjmallett info.func = __cvmx_error_display; 5041215976Sjmallett info.user_info = (long) 5042215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,0)[CAREXT]: Carrier extend error\n" 5043215976Sjmallett " (SGMII/1000Base-X only)\n"; 5044215976Sjmallett fail |= cvmx_error_add(&info); 5045215976Sjmallett 5046215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5047215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0); 5048215976Sjmallett info.status_mask = 1ull<<8 /* skperr */; 5049215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0); 5050215976Sjmallett info.enable_mask = 1ull<<8 /* skperr */; 5051215976Sjmallett info.flags = 0; 5052215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5053215976Sjmallett info.group_index = 3; 5054215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5055215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 5056215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 5057215976Sjmallett info.func = __cvmx_error_display; 5058215976Sjmallett info.user_info = (long) 5059215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,0)[SKPERR]: Skipper error\n"; 5060215976Sjmallett fail |= cvmx_error_add(&info); 5061215976Sjmallett 5062215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5063215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0); 5064215976Sjmallett info.status_mask = 1ull<<10 /* ovrerr */; 5065215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0); 5066215976Sjmallett info.enable_mask = 1ull<<10 /* ovrerr */; 5067215976Sjmallett info.flags = 0; 5068215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5069215976Sjmallett info.group_index = 3; 5070215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5071215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 5072215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 5073215976Sjmallett info.func = __cvmx_error_display; 5074215976Sjmallett info.user_info = (long) 5075215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,0)[OVRERR]: Internal Data Aggregation Overflow\n" 5076215976Sjmallett " This interrupt should never assert\n" 5077215976Sjmallett " (SGMII/1000Base-X only)\n"; 5078215976Sjmallett fail |= cvmx_error_add(&info); 5079215976Sjmallett 5080215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5081215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0); 5082215976Sjmallett info.status_mask = 1ull<<20 /* loc_fault */; 5083215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0); 5084215976Sjmallett info.enable_mask = 1ull<<20 /* loc_fault */; 5085215976Sjmallett info.flags = 0; 5086215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5087215976Sjmallett info.group_index = 3; 5088215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5089215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 5090215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 5091215976Sjmallett info.func = __cvmx_error_display; 5092215976Sjmallett info.user_info = (long) 5093215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,0)[LOC_FAULT]: Local Fault Sequence Deteted\n" 5094215976Sjmallett " (XAUI Mode only)\n"; 5095215976Sjmallett fail |= cvmx_error_add(&info); 5096215976Sjmallett 5097215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5098215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0); 5099215976Sjmallett info.status_mask = 1ull<<21 /* rem_fault */; 5100215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0); 5101215976Sjmallett info.enable_mask = 1ull<<21 /* rem_fault */; 5102215976Sjmallett info.flags = 0; 5103215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5104215976Sjmallett info.group_index = 3; 5105215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5106215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 5107215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 5108215976Sjmallett info.func = __cvmx_error_display; 5109215976Sjmallett info.user_info = (long) 5110215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,0)[REM_FAULT]: Remote Fault Sequence Deteted\n" 5111215976Sjmallett " (XAUI Mode only)\n"; 5112215976Sjmallett fail |= cvmx_error_add(&info); 5113215976Sjmallett 5114215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5115215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0); 5116215976Sjmallett info.status_mask = 1ull<<22 /* bad_seq */; 5117215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0); 5118215976Sjmallett info.enable_mask = 1ull<<22 /* bad_seq */; 5119215976Sjmallett info.flags = 0; 5120215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5121215976Sjmallett info.group_index = 3; 5122215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5123215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 5124215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 5125215976Sjmallett info.func = __cvmx_error_display; 5126215976Sjmallett info.user_info = (long) 5127215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,0)[BAD_SEQ]: Reserved Sequence Deteted\n" 5128215976Sjmallett " (XAUI Mode only)\n"; 5129215976Sjmallett fail |= cvmx_error_add(&info); 5130215976Sjmallett 5131215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5132215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0); 5133215976Sjmallett info.status_mask = 1ull<<23 /* bad_term */; 5134215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0); 5135215976Sjmallett info.enable_mask = 1ull<<23 /* bad_term */; 5136215976Sjmallett info.flags = 0; 5137215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5138215976Sjmallett info.group_index = 3; 5139215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5140215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 5141215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 5142215976Sjmallett info.func = __cvmx_error_display; 5143215976Sjmallett info.user_info = (long) 5144215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,0)[BAD_TERM]: Frame is terminated by control character other\n" 5145215976Sjmallett " than /T/. The error propagation control\n" 5146215976Sjmallett " character /E/ will be included as part of the\n" 5147215976Sjmallett " frame and does not cause a frame termination.\n" 5148215976Sjmallett " (XAUI Mode only)\n"; 5149215976Sjmallett fail |= cvmx_error_add(&info); 5150215976Sjmallett 5151215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5152215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0); 5153215976Sjmallett info.status_mask = 1ull<<24 /* unsop */; 5154215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0); 5155215976Sjmallett info.enable_mask = 1ull<<24 /* unsop */; 5156215976Sjmallett info.flags = 0; 5157215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5158215976Sjmallett info.group_index = 3; 5159215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5160215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 5161215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 5162215976Sjmallett info.func = __cvmx_error_display; 5163215976Sjmallett info.user_info = (long) 5164215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,0)[UNSOP]: Unexpected SOP\n" 5165215976Sjmallett " (XAUI Mode only)\n"; 5166215976Sjmallett fail |= cvmx_error_add(&info); 5167215976Sjmallett 5168215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5169215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0); 5170215976Sjmallett info.status_mask = 1ull<<25 /* uneop */; 5171215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0); 5172215976Sjmallett info.enable_mask = 1ull<<25 /* uneop */; 5173215976Sjmallett info.flags = 0; 5174215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5175215976Sjmallett info.group_index = 3; 5176215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5177215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 5178215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 5179215976Sjmallett info.func = __cvmx_error_display; 5180215976Sjmallett info.user_info = (long) 5181215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,0)[UNEOP]: Unexpected EOP\n" 5182215976Sjmallett " (XAUI Mode only)\n"; 5183215976Sjmallett fail |= cvmx_error_add(&info); 5184215976Sjmallett 5185215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5186215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0); 5187215976Sjmallett info.status_mask = 1ull<<26 /* undat */; 5188215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0); 5189215976Sjmallett info.enable_mask = 1ull<<26 /* undat */; 5190215976Sjmallett info.flags = 0; 5191215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5192215976Sjmallett info.group_index = 3; 5193215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5194215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 5195215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 5196215976Sjmallett info.func = __cvmx_error_display; 5197215976Sjmallett info.user_info = (long) 5198215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,0)[UNDAT]: Unexpected Data\n" 5199215976Sjmallett " (XAUI Mode only)\n"; 5200215976Sjmallett fail |= cvmx_error_add(&info); 5201215976Sjmallett 5202215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5203215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0); 5204215976Sjmallett info.status_mask = 1ull<<27 /* hg2fld */; 5205215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0); 5206215976Sjmallett info.enable_mask = 1ull<<27 /* hg2fld */; 5207215976Sjmallett info.flags = 0; 5208215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5209215976Sjmallett info.group_index = 3; 5210215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5211215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 5212215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 5213215976Sjmallett info.func = __cvmx_error_display; 5214215976Sjmallett info.user_info = (long) 5215215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,0)[HG2FLD]: HiGig2 received message field error, as below\n" 5216215976Sjmallett " 1) MSG_TYPE field not 6'b00_0000\n" 5217215976Sjmallett " i.e. it is not a FLOW CONTROL message, which\n" 5218215976Sjmallett " is the only defined type for HiGig2\n" 5219215976Sjmallett " 2) FWD_TYPE field not 2'b00 i.e. Link Level msg\n" 5220215976Sjmallett " which is the only defined type for HiGig2\n" 5221215976Sjmallett " 3) FC_OBJECT field is neither 4'b0000 for\n" 5222215976Sjmallett " Physical Link nor 4'b0010 for Logical Link.\n" 5223215976Sjmallett " Those are the only two defined types in HiGig2\n"; 5224215976Sjmallett fail |= cvmx_error_add(&info); 5225215976Sjmallett 5226215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5227215976Sjmallett info.status_addr = CVMX_GMXX_RXX_INT_REG(3,0); 5228215976Sjmallett info.status_mask = 1ull<<28 /* hg2cc */; 5229215976Sjmallett info.enable_addr = CVMX_GMXX_RXX_INT_EN(3,0); 5230215976Sjmallett info.enable_mask = 1ull<<28 /* hg2cc */; 5231215976Sjmallett info.flags = 0; 5232215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5233215976Sjmallett info.group_index = 3; 5234215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5235215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 5236215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 5237215976Sjmallett info.func = __cvmx_error_display; 5238215976Sjmallett info.user_info = (long) 5239215976Sjmallett "ERROR GMXX_RXX_INT_REG(3,0)[HG2CC]: HiGig2 received message CRC or Control char error\n" 5240215976Sjmallett " Set when either CRC8 error detected or when\n" 5241215976Sjmallett " a Control Character is found in the message\n" 5242215976Sjmallett " bytes after the K.SOM\n" 5243215976Sjmallett " NOTE: HG2CC has higher priority than HG2FLD\n" 5244215976Sjmallett " i.e. a HiGig2 message that results in HG2CC\n" 5245215976Sjmallett " getting set, will never set HG2FLD.\n"; 5246215976Sjmallett fail |= cvmx_error_add(&info); 5247215976Sjmallett 5248215976Sjmallett /* CVMX_GMXX_TX_INT_REG(0) */ 5249215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5250215976Sjmallett info.status_addr = CVMX_GMXX_TX_INT_REG(0); 5251215976Sjmallett info.status_mask = 1ull<<0 /* pko_nxa */; 5252215976Sjmallett info.enable_addr = CVMX_GMXX_TX_INT_EN(0); 5253215976Sjmallett info.enable_mask = 1ull<<0 /* pko_nxa */; 5254215976Sjmallett info.flags = 0; 5255215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5256215976Sjmallett info.group_index = 0; 5257215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5258215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 5259215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 5260215976Sjmallett info.func = __cvmx_error_display; 5261215976Sjmallett info.user_info = (long) 5262215976Sjmallett "ERROR GMXX_TX_INT_REG(0)[PKO_NXA]: Port address out-of-range from PKO Interface\n"; 5263215976Sjmallett fail |= cvmx_error_add(&info); 5264215976Sjmallett 5265215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5266215976Sjmallett info.status_addr = CVMX_GMXX_TX_INT_REG(0); 5267215976Sjmallett info.status_mask = 0xfull<<2 /* undflw */; 5268215976Sjmallett info.enable_addr = CVMX_GMXX_TX_INT_EN(0); 5269215976Sjmallett info.enable_mask = 0xfull<<2 /* undflw */; 5270215976Sjmallett info.flags = 0; 5271215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5272215976Sjmallett info.group_index = 0; 5273215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5274215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 5275215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 5276215976Sjmallett info.func = __cvmx_error_display; 5277215976Sjmallett info.user_info = (long) 5278215976Sjmallett "ERROR GMXX_TX_INT_REG(0)[UNDFLW]: TX Underflow\n"; 5279215976Sjmallett fail |= cvmx_error_add(&info); 5280215976Sjmallett 5281215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5282215976Sjmallett info.status_addr = CVMX_GMXX_TX_INT_REG(0); 5283215976Sjmallett info.status_mask = 0xfull<<20 /* ptp_lost */; 5284215976Sjmallett info.enable_addr = CVMX_GMXX_TX_INT_EN(0); 5285215976Sjmallett info.enable_mask = 0xfull<<20 /* ptp_lost */; 5286215976Sjmallett info.flags = 0; 5287215976Sjmallett info.group = CVMX_ERROR_GROUP_ETHERNET; 5288215976Sjmallett info.group_index = 0; 5289215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5290215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 5291215976Sjmallett info.parent.status_mask = 1ull<<1 /* gmx0 */; 5292215976Sjmallett info.func = __cvmx_error_display; 5293215976Sjmallett info.user_info = (long) 5294215976Sjmallett "ERROR GMXX_TX_INT_REG(0)[PTP_LOST]: A packet with a PTP request was not able to be\n" 5295215976Sjmallett " sent due to XSCOL\n"; 5296215976Sjmallett fail |= cvmx_error_add(&info); 5297215976Sjmallett 5298215976Sjmallett /* CVMX_IOB_INT_SUM */ 5299215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5300215976Sjmallett info.status_addr = CVMX_IOB_INT_SUM; 5301215976Sjmallett info.status_mask = 1ull<<0 /* np_sop */; 5302215976Sjmallett info.enable_addr = CVMX_IOB_INT_ENB; 5303215976Sjmallett info.enable_mask = 1ull<<0 /* np_sop */; 5304215976Sjmallett info.flags = 0; 5305215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 5306215976Sjmallett info.group_index = 0; 5307215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5308215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 5309215976Sjmallett info.parent.status_mask = 1ull<<30 /* iob */; 5310215976Sjmallett info.func = __cvmx_error_display; 5311215976Sjmallett info.user_info = (long) 5312215976Sjmallett "ERROR IOB_INT_SUM[NP_SOP]: Set when a SOP is followed by an SOP for the same\n" 5313215976Sjmallett " port for a non-passthrough packet.\n" 5314215976Sjmallett " The first detected error associated with bits [5:0]\n" 5315215976Sjmallett " of this register will only be set here. A new bit\n" 5316215976Sjmallett " can be set when the previous reported bit is cleared.\n"; 5317215976Sjmallett fail |= cvmx_error_add(&info); 5318215976Sjmallett 5319215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5320215976Sjmallett info.status_addr = CVMX_IOB_INT_SUM; 5321215976Sjmallett info.status_mask = 1ull<<1 /* np_eop */; 5322215976Sjmallett info.enable_addr = CVMX_IOB_INT_ENB; 5323215976Sjmallett info.enable_mask = 1ull<<1 /* np_eop */; 5324215976Sjmallett info.flags = 0; 5325215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 5326215976Sjmallett info.group_index = 0; 5327215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5328215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 5329215976Sjmallett info.parent.status_mask = 1ull<<30 /* iob */; 5330215976Sjmallett info.func = __cvmx_error_display; 5331215976Sjmallett info.user_info = (long) 5332215976Sjmallett "ERROR IOB_INT_SUM[NP_EOP]: Set when a EOP is followed by an EOP for the same\n" 5333215976Sjmallett " port for a non-passthrough packet.\n" 5334215976Sjmallett " The first detected error associated with bits [5:0]\n" 5335215976Sjmallett " of this register will only be set here. A new bit\n" 5336215976Sjmallett " can be set when the previous reported bit is cleared.\n"; 5337215976Sjmallett fail |= cvmx_error_add(&info); 5338215976Sjmallett 5339215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5340215976Sjmallett info.status_addr = CVMX_IOB_INT_SUM; 5341215976Sjmallett info.status_mask = 1ull<<2 /* p_sop */; 5342215976Sjmallett info.enable_addr = CVMX_IOB_INT_ENB; 5343215976Sjmallett info.enable_mask = 1ull<<2 /* p_sop */; 5344215976Sjmallett info.flags = 0; 5345215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 5346215976Sjmallett info.group_index = 0; 5347215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5348215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 5349215976Sjmallett info.parent.status_mask = 1ull<<30 /* iob */; 5350215976Sjmallett info.func = __cvmx_error_display; 5351215976Sjmallett info.user_info = (long) 5352215976Sjmallett "ERROR IOB_INT_SUM[P_SOP]: Set when a SOP is followed by an SOP for the same\n" 5353215976Sjmallett " port for a passthrough packet.\n" 5354215976Sjmallett " The first detected error associated with bits [5:0]\n" 5355215976Sjmallett " of this register will only be set here. A new bit\n" 5356215976Sjmallett " can be set when the previous reported bit is cleared.\n"; 5357215976Sjmallett fail |= cvmx_error_add(&info); 5358215976Sjmallett 5359215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5360215976Sjmallett info.status_addr = CVMX_IOB_INT_SUM; 5361215976Sjmallett info.status_mask = 1ull<<3 /* p_eop */; 5362215976Sjmallett info.enable_addr = CVMX_IOB_INT_ENB; 5363215976Sjmallett info.enable_mask = 1ull<<3 /* p_eop */; 5364215976Sjmallett info.flags = 0; 5365215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 5366215976Sjmallett info.group_index = 0; 5367215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5368215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 5369215976Sjmallett info.parent.status_mask = 1ull<<30 /* iob */; 5370215976Sjmallett info.func = __cvmx_error_display; 5371215976Sjmallett info.user_info = (long) 5372215976Sjmallett "ERROR IOB_INT_SUM[P_EOP]: Set when a EOP is followed by an EOP for the same\n" 5373215976Sjmallett " port for a passthrough packet.\n" 5374215976Sjmallett " The first detected error associated with bits [5:0]\n" 5375215976Sjmallett " of this register will only be set here. A new bit\n" 5376215976Sjmallett " can be set when the previous reported bit is cleared.\n"; 5377215976Sjmallett fail |= cvmx_error_add(&info); 5378215976Sjmallett 5379215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5380215976Sjmallett info.status_addr = CVMX_IOB_INT_SUM; 5381215976Sjmallett info.status_mask = 1ull<<4 /* np_dat */; 5382215976Sjmallett info.enable_addr = CVMX_IOB_INT_ENB; 5383215976Sjmallett info.enable_mask = 1ull<<4 /* np_dat */; 5384215976Sjmallett info.flags = 0; 5385215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 5386215976Sjmallett info.group_index = 0; 5387215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5388215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 5389215976Sjmallett info.parent.status_mask = 1ull<<30 /* iob */; 5390215976Sjmallett info.func = __cvmx_error_display; 5391215976Sjmallett info.user_info = (long) 5392215976Sjmallett "ERROR IOB_INT_SUM[NP_DAT]: Set when a data arrives before a SOP for the same\n" 5393215976Sjmallett " port for a non-passthrough packet.\n" 5394215976Sjmallett " The first detected error associated with bits [5:0]\n" 5395215976Sjmallett " of this register will only be set here. A new bit\n" 5396215976Sjmallett " can be set when the previous reported bit is cleared.\n"; 5397215976Sjmallett fail |= cvmx_error_add(&info); 5398215976Sjmallett 5399215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5400215976Sjmallett info.status_addr = CVMX_IOB_INT_SUM; 5401215976Sjmallett info.status_mask = 1ull<<5 /* p_dat */; 5402215976Sjmallett info.enable_addr = CVMX_IOB_INT_ENB; 5403215976Sjmallett info.enable_mask = 1ull<<5 /* p_dat */; 5404215976Sjmallett info.flags = 0; 5405215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 5406215976Sjmallett info.group_index = 0; 5407215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5408215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 5409215976Sjmallett info.parent.status_mask = 1ull<<30 /* iob */; 5410215976Sjmallett info.func = __cvmx_error_display; 5411215976Sjmallett info.user_info = (long) 5412215976Sjmallett "ERROR IOB_INT_SUM[P_DAT]: Set when a data arrives before a SOP for the same\n" 5413215976Sjmallett " port for a passthrough packet.\n" 5414215976Sjmallett " The first detected error associated with bits [5:0]\n" 5415215976Sjmallett " of this register will only be set here. A new bit\n" 5416215976Sjmallett " can be set when the previous reported bit is cleared.\n"; 5417215976Sjmallett fail |= cvmx_error_add(&info); 5418215976Sjmallett 5419215976Sjmallett /* CVMX_AGL_GMX_BAD_REG */ 5420215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5421215976Sjmallett info.status_addr = CVMX_AGL_GMX_BAD_REG; 5422215976Sjmallett info.status_mask = 1ull<<32 /* ovrflw */; 5423215976Sjmallett info.enable_addr = 0; 5424215976Sjmallett info.enable_mask = 0; 5425215976Sjmallett info.flags = 0; 5426215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 5427215976Sjmallett info.group_index = 0; 5428215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5429215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 5430215976Sjmallett info.parent.status_mask = 1ull<<28 /* agl */; 5431215976Sjmallett info.func = __cvmx_error_display; 5432215976Sjmallett info.user_info = (long) 5433215976Sjmallett "ERROR AGL_GMX_BAD_REG[OVRFLW]: RX FIFO overflow (MII0)\n"; 5434215976Sjmallett fail |= cvmx_error_add(&info); 5435215976Sjmallett 5436215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5437215976Sjmallett info.status_addr = CVMX_AGL_GMX_BAD_REG; 5438215976Sjmallett info.status_mask = 1ull<<33 /* txpop */; 5439215976Sjmallett info.enable_addr = 0; 5440215976Sjmallett info.enable_mask = 0; 5441215976Sjmallett info.flags = 0; 5442215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 5443215976Sjmallett info.group_index = 0; 5444215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5445215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 5446215976Sjmallett info.parent.status_mask = 1ull<<28 /* agl */; 5447215976Sjmallett info.func = __cvmx_error_display; 5448215976Sjmallett info.user_info = (long) 5449215976Sjmallett "ERROR AGL_GMX_BAD_REG[TXPOP]: TX FIFO underflow (MII0)\n"; 5450215976Sjmallett fail |= cvmx_error_add(&info); 5451215976Sjmallett 5452215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5453215976Sjmallett info.status_addr = CVMX_AGL_GMX_BAD_REG; 5454215976Sjmallett info.status_mask = 1ull<<34 /* txpsh */; 5455215976Sjmallett info.enable_addr = 0; 5456215976Sjmallett info.enable_mask = 0; 5457215976Sjmallett info.flags = 0; 5458215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 5459215976Sjmallett info.group_index = 0; 5460215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5461215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 5462215976Sjmallett info.parent.status_mask = 1ull<<28 /* agl */; 5463215976Sjmallett info.func = __cvmx_error_display; 5464215976Sjmallett info.user_info = (long) 5465215976Sjmallett "ERROR AGL_GMX_BAD_REG[TXPSH]: TX FIFO overflow (MII0)\n"; 5466215976Sjmallett fail |= cvmx_error_add(&info); 5467215976Sjmallett 5468215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5469215976Sjmallett info.status_addr = CVMX_AGL_GMX_BAD_REG; 5470215976Sjmallett info.status_mask = 1ull<<35 /* ovrflw1 */; 5471215976Sjmallett info.enable_addr = 0; 5472215976Sjmallett info.enable_mask = 0; 5473215976Sjmallett info.flags = 0; 5474215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 5475215976Sjmallett info.group_index = 0; 5476215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5477215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 5478215976Sjmallett info.parent.status_mask = 1ull<<28 /* agl */; 5479215976Sjmallett info.func = __cvmx_error_display; 5480215976Sjmallett info.user_info = (long) 5481215976Sjmallett "ERROR AGL_GMX_BAD_REG[OVRFLW1]: RX FIFO overflow (MII1)\n"; 5482215976Sjmallett fail |= cvmx_error_add(&info); 5483215976Sjmallett 5484215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5485215976Sjmallett info.status_addr = CVMX_AGL_GMX_BAD_REG; 5486215976Sjmallett info.status_mask = 1ull<<36 /* txpop1 */; 5487215976Sjmallett info.enable_addr = 0; 5488215976Sjmallett info.enable_mask = 0; 5489215976Sjmallett info.flags = 0; 5490215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 5491215976Sjmallett info.group_index = 0; 5492215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5493215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 5494215976Sjmallett info.parent.status_mask = 1ull<<28 /* agl */; 5495215976Sjmallett info.func = __cvmx_error_display; 5496215976Sjmallett info.user_info = (long) 5497215976Sjmallett "ERROR AGL_GMX_BAD_REG[TXPOP1]: TX FIFO underflow (MII1)\n"; 5498215976Sjmallett fail |= cvmx_error_add(&info); 5499215976Sjmallett 5500215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5501215976Sjmallett info.status_addr = CVMX_AGL_GMX_BAD_REG; 5502215976Sjmallett info.status_mask = 1ull<<37 /* txpsh1 */; 5503215976Sjmallett info.enable_addr = 0; 5504215976Sjmallett info.enable_mask = 0; 5505215976Sjmallett info.flags = 0; 5506215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 5507215976Sjmallett info.group_index = 0; 5508215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5509215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 5510215976Sjmallett info.parent.status_mask = 1ull<<28 /* agl */; 5511215976Sjmallett info.func = __cvmx_error_display; 5512215976Sjmallett info.user_info = (long) 5513215976Sjmallett "ERROR AGL_GMX_BAD_REG[TXPSH1]: TX FIFO overflow (MII1)\n"; 5514215976Sjmallett fail |= cvmx_error_add(&info); 5515215976Sjmallett 5516215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5517215976Sjmallett info.status_addr = CVMX_AGL_GMX_BAD_REG; 5518215976Sjmallett info.status_mask = 0x3ull<<2 /* out_ovr */; 5519215976Sjmallett info.enable_addr = 0; 5520215976Sjmallett info.enable_mask = 0; 5521215976Sjmallett info.flags = 0; 5522215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 5523215976Sjmallett info.group_index = 0; 5524215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5525215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 5526215976Sjmallett info.parent.status_mask = 1ull<<28 /* agl */; 5527215976Sjmallett info.func = __cvmx_error_display; 5528215976Sjmallett info.user_info = (long) 5529215976Sjmallett "ERROR AGL_GMX_BAD_REG[OUT_OVR]: Outbound data FIFO overflow\n"; 5530215976Sjmallett fail |= cvmx_error_add(&info); 5531215976Sjmallett 5532215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5533215976Sjmallett info.status_addr = CVMX_AGL_GMX_BAD_REG; 5534215976Sjmallett info.status_mask = 0x3ull<<22 /* loststat */; 5535215976Sjmallett info.enable_addr = 0; 5536215976Sjmallett info.enable_mask = 0; 5537215976Sjmallett info.flags = 0; 5538215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 5539215976Sjmallett info.group_index = 0; 5540215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5541215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 5542215976Sjmallett info.parent.status_mask = 1ull<<28 /* agl */; 5543215976Sjmallett info.func = __cvmx_error_display; 5544215976Sjmallett info.user_info = (long) 5545215976Sjmallett "ERROR AGL_GMX_BAD_REG[LOSTSTAT]: TX Statistics data was over-written\n" 5546215976Sjmallett " In MII/RGMII, one bit per port\n" 5547215976Sjmallett " TX Stats are corrupted\n"; 5548215976Sjmallett fail |= cvmx_error_add(&info); 5549215976Sjmallett 5550215976Sjmallett /* CVMX_AGL_GMX_RXX_INT_REG(0) */ 5551215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5552215976Sjmallett info.status_addr = CVMX_AGL_GMX_RXX_INT_REG(0); 5553215976Sjmallett info.status_mask = 1ull<<8 /* skperr */; 5554215976Sjmallett info.enable_addr = CVMX_AGL_GMX_RXX_INT_EN(0); 5555215976Sjmallett info.enable_mask = 1ull<<8 /* skperr */; 5556215976Sjmallett info.flags = 0; 5557215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 5558215976Sjmallett info.group_index = 0; 5559215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5560215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 5561215976Sjmallett info.parent.status_mask = 1ull<<28 /* agl */; 5562215976Sjmallett info.func = __cvmx_error_display; 5563215976Sjmallett info.user_info = (long) 5564215976Sjmallett "ERROR AGL_GMX_RXX_INT_REG(0)[SKPERR]: Skipper error\n"; 5565215976Sjmallett fail |= cvmx_error_add(&info); 5566215976Sjmallett 5567215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5568215976Sjmallett info.status_addr = CVMX_AGL_GMX_RXX_INT_REG(0); 5569215976Sjmallett info.status_mask = 1ull<<10 /* ovrerr */; 5570215976Sjmallett info.enable_addr = CVMX_AGL_GMX_RXX_INT_EN(0); 5571215976Sjmallett info.enable_mask = 1ull<<10 /* ovrerr */; 5572215976Sjmallett info.flags = 0; 5573215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 5574215976Sjmallett info.group_index = 0; 5575215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5576215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 5577215976Sjmallett info.parent.status_mask = 1ull<<28 /* agl */; 5578215976Sjmallett info.func = __cvmx_error_display; 5579215976Sjmallett info.user_info = (long) 5580215976Sjmallett "ERROR AGL_GMX_RXX_INT_REG(0)[OVRERR]: Internal Data Aggregation Overflow\n" 5581215976Sjmallett " This interrupt should never assert\n"; 5582215976Sjmallett fail |= cvmx_error_add(&info); 5583215976Sjmallett 5584215976Sjmallett /* CVMX_AGL_GMX_RXX_INT_REG(1) */ 5585215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5586215976Sjmallett info.status_addr = CVMX_AGL_GMX_RXX_INT_REG(1); 5587215976Sjmallett info.status_mask = 1ull<<8 /* skperr */; 5588215976Sjmallett info.enable_addr = CVMX_AGL_GMX_RXX_INT_EN(1); 5589215976Sjmallett info.enable_mask = 1ull<<8 /* skperr */; 5590215976Sjmallett info.flags = 0; 5591215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 5592215976Sjmallett info.group_index = 1; 5593215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5594215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 5595215976Sjmallett info.parent.status_mask = 1ull<<28 /* agl */; 5596215976Sjmallett info.func = __cvmx_error_display; 5597215976Sjmallett info.user_info = (long) 5598215976Sjmallett "ERROR AGL_GMX_RXX_INT_REG(1)[SKPERR]: Skipper error\n"; 5599215976Sjmallett fail |= cvmx_error_add(&info); 5600215976Sjmallett 5601215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5602215976Sjmallett info.status_addr = CVMX_AGL_GMX_RXX_INT_REG(1); 5603215976Sjmallett info.status_mask = 1ull<<10 /* ovrerr */; 5604215976Sjmallett info.enable_addr = CVMX_AGL_GMX_RXX_INT_EN(1); 5605215976Sjmallett info.enable_mask = 1ull<<10 /* ovrerr */; 5606215976Sjmallett info.flags = 0; 5607215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 5608215976Sjmallett info.group_index = 1; 5609215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5610215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 5611215976Sjmallett info.parent.status_mask = 1ull<<28 /* agl */; 5612215976Sjmallett info.func = __cvmx_error_display; 5613215976Sjmallett info.user_info = (long) 5614215976Sjmallett "ERROR AGL_GMX_RXX_INT_REG(1)[OVRERR]: Internal Data Aggregation Overflow\n" 5615215976Sjmallett " This interrupt should never assert\n"; 5616215976Sjmallett fail |= cvmx_error_add(&info); 5617215976Sjmallett 5618215976Sjmallett /* CVMX_AGL_GMX_TX_INT_REG */ 5619215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5620215976Sjmallett info.status_addr = CVMX_AGL_GMX_TX_INT_REG; 5621215976Sjmallett info.status_mask = 1ull<<0 /* pko_nxa */; 5622215976Sjmallett info.enable_addr = CVMX_AGL_GMX_TX_INT_EN; 5623215976Sjmallett info.enable_mask = 1ull<<0 /* pko_nxa */; 5624215976Sjmallett info.flags = 0; 5625215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 5626215976Sjmallett info.group_index = 0; 5627215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5628215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 5629215976Sjmallett info.parent.status_mask = 1ull<<28 /* agl */; 5630215976Sjmallett info.func = __cvmx_error_display; 5631215976Sjmallett info.user_info = (long) 5632215976Sjmallett "ERROR AGL_GMX_TX_INT_REG[PKO_NXA]: Port address out-of-range from PKO Interface\n"; 5633215976Sjmallett fail |= cvmx_error_add(&info); 5634215976Sjmallett 5635215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5636215976Sjmallett info.status_addr = CVMX_AGL_GMX_TX_INT_REG; 5637215976Sjmallett info.status_mask = 0x3ull<<2 /* undflw */; 5638215976Sjmallett info.enable_addr = CVMX_AGL_GMX_TX_INT_EN; 5639215976Sjmallett info.enable_mask = 0x3ull<<2 /* undflw */; 5640215976Sjmallett info.flags = 0; 5641215976Sjmallett info.group = CVMX_ERROR_GROUP_MGMT_PORT; 5642215976Sjmallett info.group_index = 0; 5643215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5644215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 5645215976Sjmallett info.parent.status_mask = 1ull<<28 /* agl */; 5646215976Sjmallett info.func = __cvmx_error_display; 5647215976Sjmallett info.user_info = (long) 5648215976Sjmallett "ERROR AGL_GMX_TX_INT_REG[UNDFLW]: TX Underflow\n"; 5649215976Sjmallett fail |= cvmx_error_add(&info); 5650215976Sjmallett 5651215976Sjmallett /* CVMX_ZIP_ERROR */ 5652215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5653215976Sjmallett info.status_addr = CVMX_ZIP_ERROR; 5654215976Sjmallett info.status_mask = 1ull<<0 /* doorbell */; 5655215976Sjmallett info.enable_addr = CVMX_ZIP_INT_MASK; 5656215976Sjmallett info.enable_mask = 1ull<<0 /* doorbell */; 5657215976Sjmallett info.flags = 0; 5658215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 5659215976Sjmallett info.group_index = 0; 5660215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5661215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 5662215976Sjmallett info.parent.status_mask = 1ull<<7 /* zip */; 5663215976Sjmallett info.func = __cvmx_error_display; 5664215976Sjmallett info.user_info = (long) 5665215976Sjmallett "ERROR ZIP_ERROR[DOORBELL]: A doorbell count has overflowed\n"; 5666215976Sjmallett fail |= cvmx_error_add(&info); 5667215976Sjmallett 5668215976Sjmallett /* CVMX_DFA_ERROR */ 5669215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5670215976Sjmallett info.status_addr = CVMX_DFA_ERROR; 5671215976Sjmallett info.status_mask = 1ull<<0 /* dblovf */; 5672215976Sjmallett info.enable_addr = CVMX_DFA_INTMSK; 5673215976Sjmallett info.enable_mask = 1ull<<0 /* dblina */; 5674215976Sjmallett info.flags = 0; 5675215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 5676215976Sjmallett info.group_index = 0; 5677215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5678215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 5679215976Sjmallett info.parent.status_mask = 1ull<<6 /* dfa */; 5680215976Sjmallett info.func = __cvmx_error_display; 5681215976Sjmallett info.user_info = (long) 5682215976Sjmallett "ERROR DFA_ERROR[DBLOVF]: Doorbell Overflow detected - Status bit\n" 5683215976Sjmallett " When set, the 20b accumulated doorbell register\n" 5684215976Sjmallett " had overflowed (SW wrote too many doorbell requests).\n" 5685215976Sjmallett " If the DBLINA had previously been enabled(set),\n" 5686215976Sjmallett " an interrupt will be posted. Software can clear\n" 5687215976Sjmallett " the interrupt by writing a 1 to this register bit.\n" 5688215976Sjmallett " NOTE: Detection of a Doorbell Register overflow\n" 5689215976Sjmallett " is a catastrophic error which may leave the DFA\n" 5690215976Sjmallett " HW in an unrecoverable state.\n"; 5691215976Sjmallett fail |= cvmx_error_add(&info); 5692215976Sjmallett 5693215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5694215976Sjmallett info.status_addr = CVMX_DFA_ERROR; 5695215976Sjmallett info.status_mask = 0x7ull<<1 /* dc0perr */; 5696215976Sjmallett info.enable_addr = CVMX_DFA_INTMSK; 5697215976Sjmallett info.enable_mask = 0x7ull<<1 /* dc0pena */; 5698215976Sjmallett info.flags = 0; 5699215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 5700215976Sjmallett info.group_index = 0; 5701215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5702215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 5703215976Sjmallett info.parent.status_mask = 1ull<<6 /* dfa */; 5704215976Sjmallett info.func = __cvmx_error_display; 5705215976Sjmallett info.user_info = (long) 5706215976Sjmallett "ERROR DFA_ERROR[DC0PERR]: RAM[3:1] Parity Error Detected from Node Cluster #0\n" 5707215976Sjmallett " See also DFA_DTCFADR register which contains the\n" 5708215976Sjmallett " failing addresses for the internal node cache RAMs.\n"; 5709215976Sjmallett fail |= cvmx_error_add(&info); 5710215976Sjmallett 5711215976Sjmallett /* CVMX_SRIOX_INT_REG(0) */ 5712215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5713215976Sjmallett info.status_addr = CVMX_SRIOX_INT_REG(0); 5714215976Sjmallett info.status_mask = 1ull<<4 /* bar_err */; 5715215976Sjmallett info.enable_addr = CVMX_SRIOX_INT_ENABLE(0); 5716215976Sjmallett info.enable_mask = 1ull<<4 /* bar_err */; 5717215976Sjmallett info.flags = 0; 5718215976Sjmallett info.group = CVMX_ERROR_GROUP_SRIO; 5719215976Sjmallett info.group_index = 0; 5720215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5721215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 5722215976Sjmallett info.parent.status_mask = 1ull<<32 /* srio0 */; 5723215976Sjmallett info.func = __cvmx_error_display; 5724215976Sjmallett info.user_info = (long) 5725215976Sjmallett "ERROR SRIOX_INT_REG(0)[BAR_ERR]: Incoming Access Crossing/Missing BAR Address\n"; 5726215976Sjmallett fail |= cvmx_error_add(&info); 5727215976Sjmallett 5728215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5729215976Sjmallett info.status_addr = CVMX_SRIOX_INT_REG(0); 5730215976Sjmallett info.status_mask = 1ull<<5 /* deny_wr */; 5731215976Sjmallett info.enable_addr = CVMX_SRIOX_INT_ENABLE(0); 5732215976Sjmallett info.enable_mask = 1ull<<5 /* deny_wr */; 5733215976Sjmallett info.flags = 0; 5734215976Sjmallett info.group = CVMX_ERROR_GROUP_SRIO; 5735215976Sjmallett info.group_index = 0; 5736215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5737215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 5738215976Sjmallett info.parent.status_mask = 1ull<<32 /* srio0 */; 5739215976Sjmallett info.func = __cvmx_error_display; 5740215976Sjmallett info.user_info = (long) 5741215976Sjmallett "ERROR SRIOX_INT_REG(0)[DENY_WR]: Incoming Maint_Wr Access to Denied Bar Registers.\n"; 5742215976Sjmallett fail |= cvmx_error_add(&info); 5743215976Sjmallett 5744215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5745215976Sjmallett info.status_addr = CVMX_SRIOX_INT_REG(0); 5746215976Sjmallett info.status_mask = 1ull<<6 /* sli_err */; 5747215976Sjmallett info.enable_addr = CVMX_SRIOX_INT_ENABLE(0); 5748215976Sjmallett info.enable_mask = 1ull<<6 /* sli_err */; 5749215976Sjmallett info.flags = 0; 5750215976Sjmallett info.group = CVMX_ERROR_GROUP_SRIO; 5751215976Sjmallett info.group_index = 0; 5752215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5753215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 5754215976Sjmallett info.parent.status_mask = 1ull<<32 /* srio0 */; 5755215976Sjmallett info.func = __cvmx_error_display; 5756215976Sjmallett info.user_info = (long) 5757215976Sjmallett "ERROR SRIOX_INT_REG(0)[SLI_ERR]: Unsupported S2M Transaction Received.\n" 5758215976Sjmallett " See SRIO(0..1)_INT_INFO[1:0]\n"; 5759215976Sjmallett fail |= cvmx_error_add(&info); 5760215976Sjmallett 5761215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5762215976Sjmallett info.status_addr = CVMX_SRIOX_INT_REG(0); 5763215976Sjmallett info.status_mask = 1ull<<9 /* mce_rx */; 5764215976Sjmallett info.enable_addr = CVMX_SRIOX_INT_ENABLE(0); 5765215976Sjmallett info.enable_mask = 1ull<<9 /* mce_rx */; 5766215976Sjmallett info.flags = 0; 5767215976Sjmallett info.group = CVMX_ERROR_GROUP_SRIO; 5768215976Sjmallett info.group_index = 0; 5769215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5770215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 5771215976Sjmallett info.parent.status_mask = 1ull<<32 /* srio0 */; 5772215976Sjmallett info.func = __cvmx_error_display; 5773215976Sjmallett info.user_info = (long) 5774215976Sjmallett "ERROR SRIOX_INT_REG(0)[MCE_RX]: Incoming Multicast Event Symbol\n"; 5775215976Sjmallett fail |= cvmx_error_add(&info); 5776215976Sjmallett 5777215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5778215976Sjmallett info.status_addr = CVMX_SRIOX_INT_REG(0); 5779215976Sjmallett info.status_mask = 1ull<<12 /* log_erb */; 5780215976Sjmallett info.enable_addr = CVMX_SRIOX_INT_ENABLE(0); 5781215976Sjmallett info.enable_mask = 1ull<<12 /* log_erb */; 5782215976Sjmallett info.flags = 0; 5783215976Sjmallett info.group = CVMX_ERROR_GROUP_SRIO; 5784215976Sjmallett info.group_index = 0; 5785215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5786215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 5787215976Sjmallett info.parent.status_mask = 1ull<<32 /* srio0 */; 5788215976Sjmallett info.func = __cvmx_error_display; 5789215976Sjmallett info.user_info = (long) 5790215976Sjmallett "ERROR SRIOX_INT_REG(0)[LOG_ERB]: Logical/Transport Layer Error detected in ERB\n" 5791215976Sjmallett " See SRIOMAINT(0..1)_ERB_LT_ERR_DET\n"; 5792215976Sjmallett fail |= cvmx_error_add(&info); 5793215976Sjmallett 5794215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5795215976Sjmallett info.status_addr = CVMX_SRIOX_INT_REG(0); 5796215976Sjmallett info.status_mask = 1ull<<13 /* phy_erb */; 5797215976Sjmallett info.enable_addr = CVMX_SRIOX_INT_ENABLE(0); 5798215976Sjmallett info.enable_mask = 1ull<<13 /* phy_erb */; 5799215976Sjmallett info.flags = 0; 5800215976Sjmallett info.group = CVMX_ERROR_GROUP_SRIO; 5801215976Sjmallett info.group_index = 0; 5802215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5803215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 5804215976Sjmallett info.parent.status_mask = 1ull<<32 /* srio0 */; 5805215976Sjmallett info.func = __cvmx_error_display; 5806215976Sjmallett info.user_info = (long) 5807215976Sjmallett "ERROR SRIOX_INT_REG(0)[PHY_ERB]: Physical Layer Error detected in ERB\n" 5808215976Sjmallett " See SRIOMAINT*_ERB_ATTR_CAPT\n"; 5809215976Sjmallett fail |= cvmx_error_add(&info); 5810215976Sjmallett 5811215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5812215976Sjmallett info.status_addr = CVMX_SRIOX_INT_REG(0); 5813215976Sjmallett info.status_mask = 1ull<<18 /* omsg_err */; 5814215976Sjmallett info.enable_addr = CVMX_SRIOX_INT_ENABLE(0); 5815215976Sjmallett info.enable_mask = 1ull<<18 /* omsg_err */; 5816215976Sjmallett info.flags = 0; 5817215976Sjmallett info.group = CVMX_ERROR_GROUP_SRIO; 5818215976Sjmallett info.group_index = 0; 5819215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5820215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 5821215976Sjmallett info.parent.status_mask = 1ull<<32 /* srio0 */; 5822215976Sjmallett info.func = __cvmx_error_display; 5823215976Sjmallett info.user_info = (long) 5824215976Sjmallett "ERROR SRIOX_INT_REG(0)[OMSG_ERR]: Outbound Message Invalid Descriptor Error\n" 5825215976Sjmallett " See SRIO(0..1)_INT_INFO2\n"; 5826215976Sjmallett fail |= cvmx_error_add(&info); 5827215976Sjmallett 5828215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5829215976Sjmallett info.status_addr = CVMX_SRIOX_INT_REG(0); 5830215976Sjmallett info.status_mask = 1ull<<19 /* pko_err */; 5831215976Sjmallett info.enable_addr = CVMX_SRIOX_INT_ENABLE(0); 5832215976Sjmallett info.enable_mask = 1ull<<19 /* pko_err */; 5833215976Sjmallett info.flags = 0; 5834215976Sjmallett info.group = CVMX_ERROR_GROUP_SRIO; 5835215976Sjmallett info.group_index = 0; 5836215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5837215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 5838215976Sjmallett info.parent.status_mask = 1ull<<32 /* srio0 */; 5839215976Sjmallett info.func = __cvmx_error_display; 5840215976Sjmallett info.user_info = (long) 5841215976Sjmallett "ERROR SRIOX_INT_REG(0)[PKO_ERR]: Outbound Message Received PKO Error\n"; 5842215976Sjmallett fail |= cvmx_error_add(&info); 5843215976Sjmallett 5844215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5845215976Sjmallett info.status_addr = CVMX_SRIOX_INT_REG(0); 5846215976Sjmallett info.status_mask = 1ull<<20 /* rtry_err */; 5847215976Sjmallett info.enable_addr = CVMX_SRIOX_INT_ENABLE(0); 5848215976Sjmallett info.enable_mask = 1ull<<20 /* rtry_err */; 5849215976Sjmallett info.flags = 0; 5850215976Sjmallett info.group = CVMX_ERROR_GROUP_SRIO; 5851215976Sjmallett info.group_index = 0; 5852215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5853215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 5854215976Sjmallett info.parent.status_mask = 1ull<<32 /* srio0 */; 5855215976Sjmallett info.func = __cvmx_error_display; 5856215976Sjmallett info.user_info = (long) 5857215976Sjmallett "ERROR SRIOX_INT_REG(0)[RTRY_ERR]: Outbound Message Retry Threshold Exceeded\n" 5858215976Sjmallett " See SRIO(0..1)_INT_INFO3\n" 5859215976Sjmallett " When one or more of the segments in an outgoing\n" 5860215976Sjmallett " message have a RTRY_ERR, SRIO will not set\n" 5861215976Sjmallett " OMSG* after the message \"transfer\".\n"; 5862215976Sjmallett fail |= cvmx_error_add(&info); 5863215976Sjmallett 5864215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5865215976Sjmallett info.status_addr = CVMX_SRIOX_INT_REG(0); 5866215976Sjmallett info.status_mask = 1ull<<21 /* f_error */; 5867215976Sjmallett info.enable_addr = CVMX_SRIOX_INT_ENABLE(0); 5868215976Sjmallett info.enable_mask = 1ull<<21 /* f_error */; 5869215976Sjmallett info.flags = 0; 5870215976Sjmallett info.group = CVMX_ERROR_GROUP_SRIO; 5871215976Sjmallett info.group_index = 0; 5872215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5873215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 5874215976Sjmallett info.parent.status_mask = 1ull<<32 /* srio0 */; 5875215976Sjmallett info.func = __cvmx_error_display; 5876215976Sjmallett info.user_info = (long) 5877215976Sjmallett "ERROR SRIOX_INT_REG(0)[F_ERROR]: SRIO Fatal Port Error (MAC reset required)\n"; 5878215976Sjmallett fail |= cvmx_error_add(&info); 5879215976Sjmallett 5880215976Sjmallett /* CVMX_SRIOX_INT_REG(1) */ 5881215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5882215976Sjmallett info.status_addr = CVMX_SRIOX_INT_REG(1); 5883215976Sjmallett info.status_mask = 1ull<<4 /* bar_err */; 5884215976Sjmallett info.enable_addr = CVMX_SRIOX_INT_ENABLE(1); 5885215976Sjmallett info.enable_mask = 1ull<<4 /* bar_err */; 5886215976Sjmallett info.flags = 0; 5887215976Sjmallett info.group = CVMX_ERROR_GROUP_SRIO; 5888215976Sjmallett info.group_index = 1; 5889215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5890215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 5891215976Sjmallett info.parent.status_mask = 1ull<<33 /* srio1 */; 5892215976Sjmallett info.func = __cvmx_error_display; 5893215976Sjmallett info.user_info = (long) 5894215976Sjmallett "ERROR SRIOX_INT_REG(1)[BAR_ERR]: Incoming Access Crossing/Missing BAR Address\n"; 5895215976Sjmallett fail |= cvmx_error_add(&info); 5896215976Sjmallett 5897215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5898215976Sjmallett info.status_addr = CVMX_SRIOX_INT_REG(1); 5899215976Sjmallett info.status_mask = 1ull<<5 /* deny_wr */; 5900215976Sjmallett info.enable_addr = CVMX_SRIOX_INT_ENABLE(1); 5901215976Sjmallett info.enable_mask = 1ull<<5 /* deny_wr */; 5902215976Sjmallett info.flags = 0; 5903215976Sjmallett info.group = CVMX_ERROR_GROUP_SRIO; 5904215976Sjmallett info.group_index = 1; 5905215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5906215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 5907215976Sjmallett info.parent.status_mask = 1ull<<33 /* srio1 */; 5908215976Sjmallett info.func = __cvmx_error_display; 5909215976Sjmallett info.user_info = (long) 5910215976Sjmallett "ERROR SRIOX_INT_REG(1)[DENY_WR]: Incoming Maint_Wr Access to Denied Bar Registers.\n"; 5911215976Sjmallett fail |= cvmx_error_add(&info); 5912215976Sjmallett 5913215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5914215976Sjmallett info.status_addr = CVMX_SRIOX_INT_REG(1); 5915215976Sjmallett info.status_mask = 1ull<<6 /* sli_err */; 5916215976Sjmallett info.enable_addr = CVMX_SRIOX_INT_ENABLE(1); 5917215976Sjmallett info.enable_mask = 1ull<<6 /* sli_err */; 5918215976Sjmallett info.flags = 0; 5919215976Sjmallett info.group = CVMX_ERROR_GROUP_SRIO; 5920215976Sjmallett info.group_index = 1; 5921215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5922215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 5923215976Sjmallett info.parent.status_mask = 1ull<<33 /* srio1 */; 5924215976Sjmallett info.func = __cvmx_error_display; 5925215976Sjmallett info.user_info = (long) 5926215976Sjmallett "ERROR SRIOX_INT_REG(1)[SLI_ERR]: Unsupported S2M Transaction Received.\n" 5927215976Sjmallett " See SRIO(0..1)_INT_INFO[1:0]\n"; 5928215976Sjmallett fail |= cvmx_error_add(&info); 5929215976Sjmallett 5930215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5931215976Sjmallett info.status_addr = CVMX_SRIOX_INT_REG(1); 5932215976Sjmallett info.status_mask = 1ull<<9 /* mce_rx */; 5933215976Sjmallett info.enable_addr = CVMX_SRIOX_INT_ENABLE(1); 5934215976Sjmallett info.enable_mask = 1ull<<9 /* mce_rx */; 5935215976Sjmallett info.flags = 0; 5936215976Sjmallett info.group = CVMX_ERROR_GROUP_SRIO; 5937215976Sjmallett info.group_index = 1; 5938215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5939215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 5940215976Sjmallett info.parent.status_mask = 1ull<<33 /* srio1 */; 5941215976Sjmallett info.func = __cvmx_error_display; 5942215976Sjmallett info.user_info = (long) 5943215976Sjmallett "ERROR SRIOX_INT_REG(1)[MCE_RX]: Incoming Multicast Event Symbol\n"; 5944215976Sjmallett fail |= cvmx_error_add(&info); 5945215976Sjmallett 5946215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5947215976Sjmallett info.status_addr = CVMX_SRIOX_INT_REG(1); 5948215976Sjmallett info.status_mask = 1ull<<12 /* log_erb */; 5949215976Sjmallett info.enable_addr = CVMX_SRIOX_INT_ENABLE(1); 5950215976Sjmallett info.enable_mask = 1ull<<12 /* log_erb */; 5951215976Sjmallett info.flags = 0; 5952215976Sjmallett info.group = CVMX_ERROR_GROUP_SRIO; 5953215976Sjmallett info.group_index = 1; 5954215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5955215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 5956215976Sjmallett info.parent.status_mask = 1ull<<33 /* srio1 */; 5957215976Sjmallett info.func = __cvmx_error_display; 5958215976Sjmallett info.user_info = (long) 5959215976Sjmallett "ERROR SRIOX_INT_REG(1)[LOG_ERB]: Logical/Transport Layer Error detected in ERB\n" 5960215976Sjmallett " See SRIOMAINT(0..1)_ERB_LT_ERR_DET\n"; 5961215976Sjmallett fail |= cvmx_error_add(&info); 5962215976Sjmallett 5963215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5964215976Sjmallett info.status_addr = CVMX_SRIOX_INT_REG(1); 5965215976Sjmallett info.status_mask = 1ull<<13 /* phy_erb */; 5966215976Sjmallett info.enable_addr = CVMX_SRIOX_INT_ENABLE(1); 5967215976Sjmallett info.enable_mask = 1ull<<13 /* phy_erb */; 5968215976Sjmallett info.flags = 0; 5969215976Sjmallett info.group = CVMX_ERROR_GROUP_SRIO; 5970215976Sjmallett info.group_index = 1; 5971215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5972215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 5973215976Sjmallett info.parent.status_mask = 1ull<<33 /* srio1 */; 5974215976Sjmallett info.func = __cvmx_error_display; 5975215976Sjmallett info.user_info = (long) 5976215976Sjmallett "ERROR SRIOX_INT_REG(1)[PHY_ERB]: Physical Layer Error detected in ERB\n" 5977215976Sjmallett " See SRIOMAINT*_ERB_ATTR_CAPT\n"; 5978215976Sjmallett fail |= cvmx_error_add(&info); 5979215976Sjmallett 5980215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5981215976Sjmallett info.status_addr = CVMX_SRIOX_INT_REG(1); 5982215976Sjmallett info.status_mask = 1ull<<18 /* omsg_err */; 5983215976Sjmallett info.enable_addr = CVMX_SRIOX_INT_ENABLE(1); 5984215976Sjmallett info.enable_mask = 1ull<<18 /* omsg_err */; 5985215976Sjmallett info.flags = 0; 5986215976Sjmallett info.group = CVMX_ERROR_GROUP_SRIO; 5987215976Sjmallett info.group_index = 1; 5988215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 5989215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 5990215976Sjmallett info.parent.status_mask = 1ull<<33 /* srio1 */; 5991215976Sjmallett info.func = __cvmx_error_display; 5992215976Sjmallett info.user_info = (long) 5993215976Sjmallett "ERROR SRIOX_INT_REG(1)[OMSG_ERR]: Outbound Message Invalid Descriptor Error\n" 5994215976Sjmallett " See SRIO(0..1)_INT_INFO2\n"; 5995215976Sjmallett fail |= cvmx_error_add(&info); 5996215976Sjmallett 5997215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 5998215976Sjmallett info.status_addr = CVMX_SRIOX_INT_REG(1); 5999215976Sjmallett info.status_mask = 1ull<<19 /* pko_err */; 6000215976Sjmallett info.enable_addr = CVMX_SRIOX_INT_ENABLE(1); 6001215976Sjmallett info.enable_mask = 1ull<<19 /* pko_err */; 6002215976Sjmallett info.flags = 0; 6003215976Sjmallett info.group = CVMX_ERROR_GROUP_SRIO; 6004215976Sjmallett info.group_index = 1; 6005215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6006215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 6007215976Sjmallett info.parent.status_mask = 1ull<<33 /* srio1 */; 6008215976Sjmallett info.func = __cvmx_error_display; 6009215976Sjmallett info.user_info = (long) 6010215976Sjmallett "ERROR SRIOX_INT_REG(1)[PKO_ERR]: Outbound Message Received PKO Error\n"; 6011215976Sjmallett fail |= cvmx_error_add(&info); 6012215976Sjmallett 6013215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6014215976Sjmallett info.status_addr = CVMX_SRIOX_INT_REG(1); 6015215976Sjmallett info.status_mask = 1ull<<20 /* rtry_err */; 6016215976Sjmallett info.enable_addr = CVMX_SRIOX_INT_ENABLE(1); 6017215976Sjmallett info.enable_mask = 1ull<<20 /* rtry_err */; 6018215976Sjmallett info.flags = 0; 6019215976Sjmallett info.group = CVMX_ERROR_GROUP_SRIO; 6020215976Sjmallett info.group_index = 1; 6021215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6022215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 6023215976Sjmallett info.parent.status_mask = 1ull<<33 /* srio1 */; 6024215976Sjmallett info.func = __cvmx_error_display; 6025215976Sjmallett info.user_info = (long) 6026215976Sjmallett "ERROR SRIOX_INT_REG(1)[RTRY_ERR]: Outbound Message Retry Threshold Exceeded\n" 6027215976Sjmallett " See SRIO(0..1)_INT_INFO3\n" 6028215976Sjmallett " When one or more of the segments in an outgoing\n" 6029215976Sjmallett " message have a RTRY_ERR, SRIO will not set\n" 6030215976Sjmallett " OMSG* after the message \"transfer\".\n"; 6031215976Sjmallett fail |= cvmx_error_add(&info); 6032215976Sjmallett 6033215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6034215976Sjmallett info.status_addr = CVMX_SRIOX_INT_REG(1); 6035215976Sjmallett info.status_mask = 1ull<<21 /* f_error */; 6036215976Sjmallett info.enable_addr = CVMX_SRIOX_INT_ENABLE(1); 6037215976Sjmallett info.enable_mask = 1ull<<21 /* f_error */; 6038215976Sjmallett info.flags = 0; 6039215976Sjmallett info.group = CVMX_ERROR_GROUP_SRIO; 6040215976Sjmallett info.group_index = 1; 6041215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6042215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 6043215976Sjmallett info.parent.status_mask = 1ull<<33 /* srio1 */; 6044215976Sjmallett info.func = __cvmx_error_display; 6045215976Sjmallett info.user_info = (long) 6046215976Sjmallett "ERROR SRIOX_INT_REG(1)[F_ERROR]: SRIO Fatal Port Error (MAC reset required)\n"; 6047215976Sjmallett fail |= cvmx_error_add(&info); 6048215976Sjmallett 6049215976Sjmallett /* CVMX_PEXP_SLI_INT_SUM */ 6050215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6051215976Sjmallett info.status_addr = CVMX_PEXP_SLI_INT_SUM; 6052215976Sjmallett info.status_mask = 1ull<<0 /* rml_to */; 6053215976Sjmallett info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU; 6054215976Sjmallett info.enable_mask = 1ull<<0 /* rml_to */; 6055215976Sjmallett info.flags = 0; 6056215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6057215976Sjmallett info.group_index = 0; 6058215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6059215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 6060215976Sjmallett info.parent.status_mask = 1ull<<3 /* sli */; 6061215976Sjmallett info.func = __cvmx_error_display; 6062215976Sjmallett info.user_info = (long) 6063215976Sjmallett "ERROR PEXP_SLI_INT_SUM[RML_TO]: A read or write transfer did not complete\n" 6064215976Sjmallett " within 0xffff core clocks.\n"; 6065215976Sjmallett fail |= cvmx_error_add(&info); 6066215976Sjmallett 6067215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6068215976Sjmallett info.status_addr = CVMX_PEXP_SLI_INT_SUM; 6069215976Sjmallett info.status_mask = 1ull<<1 /* reserved_1_1 */; 6070215976Sjmallett info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU; 6071215976Sjmallett info.enable_mask = 1ull<<1 /* reserved_1_1 */; 6072215976Sjmallett info.flags = 0; 6073215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6074215976Sjmallett info.group_index = 0; 6075215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6076215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 6077215976Sjmallett info.parent.status_mask = 1ull<<3 /* sli */; 6078215976Sjmallett info.func = __cvmx_error_display; 6079215976Sjmallett info.user_info = (long) 6080215976Sjmallett "ERROR PEXP_SLI_INT_SUM[RESERVED_1_1]: Error Bit\n" 6081215976Sjmallett; 6082215976Sjmallett fail |= cvmx_error_add(&info); 6083215976Sjmallett 6084215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6085215976Sjmallett info.status_addr = CVMX_PEXP_SLI_INT_SUM; 6086215976Sjmallett info.status_mask = 1ull<<2 /* bar0_to */; 6087215976Sjmallett info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU; 6088215976Sjmallett info.enable_mask = 1ull<<2 /* bar0_to */; 6089215976Sjmallett info.flags = 0; 6090215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6091215976Sjmallett info.group_index = 0; 6092215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6093215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 6094215976Sjmallett info.parent.status_mask = 1ull<<3 /* sli */; 6095215976Sjmallett info.func = __cvmx_error_display; 6096215976Sjmallett info.user_info = (long) 6097215976Sjmallett "ERROR PEXP_SLI_INT_SUM[BAR0_TO]: BAR0 R/W to a NCB device did not receive\n" 6098215976Sjmallett " read-data/commit in 0xffff core clocks.\n"; 6099215976Sjmallett fail |= cvmx_error_add(&info); 6100215976Sjmallett 6101215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6102215976Sjmallett info.status_addr = CVMX_PEXP_SLI_INT_SUM; 6103215976Sjmallett info.status_mask = 1ull<<3 /* iob2big */; 6104215976Sjmallett info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU; 6105215976Sjmallett info.enable_mask = 1ull<<3 /* iob2big */; 6106215976Sjmallett info.flags = 0; 6107215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6108215976Sjmallett info.group_index = 0; 6109215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6110215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 6111215976Sjmallett info.parent.status_mask = 1ull<<3 /* sli */; 6112215976Sjmallett info.func = __cvmx_error_display; 6113215976Sjmallett info.user_info = (long) 6114215976Sjmallett "ERROR PEXP_SLI_INT_SUM[IOB2BIG]: A requested IOBDMA is to large.\n"; 6115215976Sjmallett fail |= cvmx_error_add(&info); 6116215976Sjmallett 6117215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6118215976Sjmallett info.status_addr = CVMX_PEXP_SLI_INT_SUM; 6119215976Sjmallett info.status_mask = 0x3ull<<6 /* reserved_6_7 */; 6120215976Sjmallett info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU; 6121215976Sjmallett info.enable_mask = 0x3ull<<6 /* reserved_6_7 */; 6122215976Sjmallett info.flags = 0; 6123215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6124215976Sjmallett info.group_index = 0; 6125215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6126215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 6127215976Sjmallett info.parent.status_mask = 1ull<<3 /* sli */; 6128215976Sjmallett info.func = __cvmx_error_display; 6129215976Sjmallett info.user_info = (long) 6130215976Sjmallett "ERROR PEXP_SLI_INT_SUM[RESERVED_6_7]: Error Bit\n" 6131215976Sjmallett; 6132215976Sjmallett fail |= cvmx_error_add(&info); 6133215976Sjmallett 6134215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6135215976Sjmallett info.status_addr = CVMX_PEXP_SLI_INT_SUM; 6136215976Sjmallett info.status_mask = 1ull<<8 /* m0_up_b0 */; 6137215976Sjmallett info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU; 6138215976Sjmallett info.enable_mask = 1ull<<8 /* m0_up_b0 */; 6139215976Sjmallett info.flags = 0; 6140215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6141215976Sjmallett info.group_index = 0; 6142215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6143215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 6144215976Sjmallett info.parent.status_mask = 1ull<<3 /* sli */; 6145215976Sjmallett info.func = __cvmx_error_display; 6146215976Sjmallett info.user_info = (long) 6147215976Sjmallett "ERROR PEXP_SLI_INT_SUM[M0_UP_B0]: Received Unsupported P-TLP for Bar0 from MAC 0.\n" 6148215976Sjmallett " This occurs when the BAR 0 address space is\n" 6149215976Sjmallett " disabeled.\n"; 6150215976Sjmallett fail |= cvmx_error_add(&info); 6151215976Sjmallett 6152215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6153215976Sjmallett info.status_addr = CVMX_PEXP_SLI_INT_SUM; 6154215976Sjmallett info.status_mask = 1ull<<9 /* m0_up_wi */; 6155215976Sjmallett info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU; 6156215976Sjmallett info.enable_mask = 1ull<<9 /* m0_up_wi */; 6157215976Sjmallett info.flags = 0; 6158215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6159215976Sjmallett info.group_index = 0; 6160215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6161215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 6162215976Sjmallett info.parent.status_mask = 1ull<<3 /* sli */; 6163215976Sjmallett info.func = __cvmx_error_display; 6164215976Sjmallett info.user_info = (long) 6165215976Sjmallett "ERROR PEXP_SLI_INT_SUM[M0_UP_WI]: Received Unsupported P-TLP for Window Register\n" 6166215976Sjmallett " from MAC 0. This occurs when the window registers\n" 6167215976Sjmallett " are disabeld and a window register access occurs.\n"; 6168215976Sjmallett fail |= cvmx_error_add(&info); 6169215976Sjmallett 6170215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6171215976Sjmallett info.status_addr = CVMX_PEXP_SLI_INT_SUM; 6172215976Sjmallett info.status_mask = 1ull<<10 /* m0_un_b0 */; 6173215976Sjmallett info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU; 6174215976Sjmallett info.enable_mask = 1ull<<10 /* m0_un_b0 */; 6175215976Sjmallett info.flags = 0; 6176215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6177215976Sjmallett info.group_index = 0; 6178215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6179215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 6180215976Sjmallett info.parent.status_mask = 1ull<<3 /* sli */; 6181215976Sjmallett info.func = __cvmx_error_display; 6182215976Sjmallett info.user_info = (long) 6183215976Sjmallett "ERROR PEXP_SLI_INT_SUM[M0_UN_B0]: Received Unsupported N-TLP for Bar0 from MAC 0.\n" 6184215976Sjmallett " This occurs when the BAR 0 address space is\n" 6185215976Sjmallett " disabeled.\n"; 6186215976Sjmallett fail |= cvmx_error_add(&info); 6187215976Sjmallett 6188215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6189215976Sjmallett info.status_addr = CVMX_PEXP_SLI_INT_SUM; 6190215976Sjmallett info.status_mask = 1ull<<11 /* m0_un_wi */; 6191215976Sjmallett info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU; 6192215976Sjmallett info.enable_mask = 1ull<<11 /* m0_un_wi */; 6193215976Sjmallett info.flags = 0; 6194215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6195215976Sjmallett info.group_index = 0; 6196215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6197215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 6198215976Sjmallett info.parent.status_mask = 1ull<<3 /* sli */; 6199215976Sjmallett info.func = __cvmx_error_display; 6200215976Sjmallett info.user_info = (long) 6201215976Sjmallett "ERROR PEXP_SLI_INT_SUM[M0_UN_WI]: Received Unsupported N-TLP for Window Register\n" 6202215976Sjmallett " from MAC 0. This occurs when the window registers\n" 6203215976Sjmallett " are disabeld and a window register access occurs.\n"; 6204215976Sjmallett fail |= cvmx_error_add(&info); 6205215976Sjmallett 6206215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6207215976Sjmallett info.status_addr = CVMX_PEXP_SLI_INT_SUM; 6208215976Sjmallett info.status_mask = 1ull<<12 /* m1_up_b0 */; 6209215976Sjmallett info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU; 6210215976Sjmallett info.enable_mask = 1ull<<12 /* m1_up_b0 */; 6211215976Sjmallett info.flags = 0; 6212215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6213215976Sjmallett info.group_index = 0; 6214215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6215215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 6216215976Sjmallett info.parent.status_mask = 1ull<<3 /* sli */; 6217215976Sjmallett info.func = __cvmx_error_display; 6218215976Sjmallett info.user_info = (long) 6219215976Sjmallett "ERROR PEXP_SLI_INT_SUM[M1_UP_B0]: Received Unsupported P-TLP for Bar0 from MAC 1.\n" 6220215976Sjmallett " This occurs when the BAR 0 address space is\n" 6221215976Sjmallett " disabeled.\n"; 6222215976Sjmallett fail |= cvmx_error_add(&info); 6223215976Sjmallett 6224215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6225215976Sjmallett info.status_addr = CVMX_PEXP_SLI_INT_SUM; 6226215976Sjmallett info.status_mask = 1ull<<13 /* m1_up_wi */; 6227215976Sjmallett info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU; 6228215976Sjmallett info.enable_mask = 1ull<<13 /* m1_up_wi */; 6229215976Sjmallett info.flags = 0; 6230215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6231215976Sjmallett info.group_index = 0; 6232215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6233215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 6234215976Sjmallett info.parent.status_mask = 1ull<<3 /* sli */; 6235215976Sjmallett info.func = __cvmx_error_display; 6236215976Sjmallett info.user_info = (long) 6237215976Sjmallett "ERROR PEXP_SLI_INT_SUM[M1_UP_WI]: Received Unsupported P-TLP for Window Register\n" 6238215976Sjmallett " from MAC 1. This occurs when the window registers\n" 6239215976Sjmallett " are disabeld and a window register access occurs.\n"; 6240215976Sjmallett fail |= cvmx_error_add(&info); 6241215976Sjmallett 6242215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6243215976Sjmallett info.status_addr = CVMX_PEXP_SLI_INT_SUM; 6244215976Sjmallett info.status_mask = 1ull<<14 /* m1_un_b0 */; 6245215976Sjmallett info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU; 6246215976Sjmallett info.enable_mask = 1ull<<14 /* m1_un_b0 */; 6247215976Sjmallett info.flags = 0; 6248215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6249215976Sjmallett info.group_index = 0; 6250215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6251215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 6252215976Sjmallett info.parent.status_mask = 1ull<<3 /* sli */; 6253215976Sjmallett info.func = __cvmx_error_display; 6254215976Sjmallett info.user_info = (long) 6255215976Sjmallett "ERROR PEXP_SLI_INT_SUM[M1_UN_B0]: Received Unsupported N-TLP for Bar0 from MAC 1.\n" 6256215976Sjmallett " This occurs when the BAR 0 address space is\n" 6257215976Sjmallett " disabeled.\n"; 6258215976Sjmallett fail |= cvmx_error_add(&info); 6259215976Sjmallett 6260215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6261215976Sjmallett info.status_addr = CVMX_PEXP_SLI_INT_SUM; 6262215976Sjmallett info.status_mask = 1ull<<15 /* m1_un_wi */; 6263215976Sjmallett info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU; 6264215976Sjmallett info.enable_mask = 1ull<<15 /* m1_un_wi */; 6265215976Sjmallett info.flags = 0; 6266215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6267215976Sjmallett info.group_index = 0; 6268215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6269215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 6270215976Sjmallett info.parent.status_mask = 1ull<<3 /* sli */; 6271215976Sjmallett info.func = __cvmx_error_display; 6272215976Sjmallett info.user_info = (long) 6273215976Sjmallett "ERROR PEXP_SLI_INT_SUM[M1_UN_WI]: Received Unsupported N-TLP for Window Register\n" 6274215976Sjmallett " from MAC 1. This occurs when the window registers\n" 6275215976Sjmallett " are disabeld and a window register access occurs.\n"; 6276215976Sjmallett fail |= cvmx_error_add(&info); 6277215976Sjmallett 6278215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6279215976Sjmallett info.status_addr = CVMX_PEXP_SLI_INT_SUM; 6280215976Sjmallett info.status_mask = 1ull<<48 /* pidbof */; 6281215976Sjmallett info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU; 6282215976Sjmallett info.enable_mask = 1ull<<48 /* pidbof */; 6283215976Sjmallett info.flags = 0; 6284215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6285215976Sjmallett info.group_index = 0; 6286215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6287215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 6288215976Sjmallett info.parent.status_mask = 1ull<<3 /* sli */; 6289215976Sjmallett info.func = __cvmx_error_display; 6290215976Sjmallett info.user_info = (long) 6291215976Sjmallett "ERROR PEXP_SLI_INT_SUM[PIDBOF]: Packet Instruction Doorbell count overflowed. Which\n" 6292215976Sjmallett " doorbell can be found in DPI_PINT_INFO[PIDBOF]\n"; 6293215976Sjmallett fail |= cvmx_error_add(&info); 6294215976Sjmallett 6295215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6296215976Sjmallett info.status_addr = CVMX_PEXP_SLI_INT_SUM; 6297215976Sjmallett info.status_mask = 1ull<<49 /* psldbof */; 6298215976Sjmallett info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU; 6299215976Sjmallett info.enable_mask = 1ull<<49 /* psldbof */; 6300215976Sjmallett info.flags = 0; 6301215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6302215976Sjmallett info.group_index = 0; 6303215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6304215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 6305215976Sjmallett info.parent.status_mask = 1ull<<3 /* sli */; 6306215976Sjmallett info.func = __cvmx_error_display; 6307215976Sjmallett info.user_info = (long) 6308215976Sjmallett "ERROR PEXP_SLI_INT_SUM[PSLDBOF]: Packet Scatterlist Doorbell count overflowed. Which\n" 6309215976Sjmallett " doorbell can be found in DPI_PINT_INFO[PSLDBOF]\n"; 6310215976Sjmallett fail |= cvmx_error_add(&info); 6311215976Sjmallett 6312215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6313215976Sjmallett info.status_addr = CVMX_PEXP_SLI_INT_SUM; 6314215976Sjmallett info.status_mask = 1ull<<50 /* pout_err */; 6315215976Sjmallett info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU; 6316215976Sjmallett info.enable_mask = 1ull<<50 /* pout_err */; 6317215976Sjmallett info.flags = 0; 6318215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6319215976Sjmallett info.group_index = 0; 6320215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6321215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 6322215976Sjmallett info.parent.status_mask = 1ull<<3 /* sli */; 6323215976Sjmallett info.func = __cvmx_error_display; 6324215976Sjmallett info.user_info = (long) 6325215976Sjmallett "ERROR PEXP_SLI_INT_SUM[POUT_ERR]: Set when PKO sends packet data with the error bit\n" 6326215976Sjmallett " set.\n"; 6327215976Sjmallett fail |= cvmx_error_add(&info); 6328215976Sjmallett 6329215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6330215976Sjmallett info.status_addr = CVMX_PEXP_SLI_INT_SUM; 6331215976Sjmallett info.status_mask = 1ull<<51 /* pin_bp */; 6332215976Sjmallett info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU; 6333215976Sjmallett info.enable_mask = 1ull<<51 /* pin_bp */; 6334215976Sjmallett info.flags = 0; 6335215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6336215976Sjmallett info.group_index = 0; 6337215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6338215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 6339215976Sjmallett info.parent.status_mask = 1ull<<3 /* sli */; 6340215976Sjmallett info.func = __cvmx_error_display; 6341215976Sjmallett info.user_info = (long) 6342215976Sjmallett "ERROR PEXP_SLI_INT_SUM[PIN_BP]: Packet input count has exceeded the WMARK.\n" 6343215976Sjmallett " See SLI_PKT_IN_BP\n"; 6344215976Sjmallett fail |= cvmx_error_add(&info); 6345215976Sjmallett 6346215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6347215976Sjmallett info.status_addr = CVMX_PEXP_SLI_INT_SUM; 6348215976Sjmallett info.status_mask = 1ull<<52 /* pgl_err */; 6349215976Sjmallett info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU; 6350215976Sjmallett info.enable_mask = 1ull<<52 /* pgl_err */; 6351215976Sjmallett info.flags = 0; 6352215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6353215976Sjmallett info.group_index = 0; 6354215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6355215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 6356215976Sjmallett info.parent.status_mask = 1ull<<3 /* sli */; 6357215976Sjmallett info.func = __cvmx_error_display; 6358215976Sjmallett info.user_info = (long) 6359215976Sjmallett "ERROR PEXP_SLI_INT_SUM[PGL_ERR]: When a read error occurs on a packet gather list\n" 6360215976Sjmallett " read this bit is set.\n"; 6361215976Sjmallett fail |= cvmx_error_add(&info); 6362215976Sjmallett 6363215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6364215976Sjmallett info.status_addr = CVMX_PEXP_SLI_INT_SUM; 6365215976Sjmallett info.status_mask = 1ull<<53 /* pdi_err */; 6366215976Sjmallett info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU; 6367215976Sjmallett info.enable_mask = 1ull<<53 /* pdi_err */; 6368215976Sjmallett info.flags = 0; 6369215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6370215976Sjmallett info.group_index = 0; 6371215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6372215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 6373215976Sjmallett info.parent.status_mask = 1ull<<3 /* sli */; 6374215976Sjmallett info.func = __cvmx_error_display; 6375215976Sjmallett info.user_info = (long) 6376215976Sjmallett "ERROR PEXP_SLI_INT_SUM[PDI_ERR]: When a read error occurs on a packet data read\n" 6377215976Sjmallett " this bit is set.\n"; 6378215976Sjmallett fail |= cvmx_error_add(&info); 6379215976Sjmallett 6380215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6381215976Sjmallett info.status_addr = CVMX_PEXP_SLI_INT_SUM; 6382215976Sjmallett info.status_mask = 1ull<<54 /* pop_err */; 6383215976Sjmallett info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU; 6384215976Sjmallett info.enable_mask = 1ull<<54 /* pop_err */; 6385215976Sjmallett info.flags = 0; 6386215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6387215976Sjmallett info.group_index = 0; 6388215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6389215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 6390215976Sjmallett info.parent.status_mask = 1ull<<3 /* sli */; 6391215976Sjmallett info.func = __cvmx_error_display; 6392215976Sjmallett info.user_info = (long) 6393215976Sjmallett "ERROR PEXP_SLI_INT_SUM[POP_ERR]: When a read error occurs on a packet scatter\n" 6394215976Sjmallett " pointer pair this bit is set.\n"; 6395215976Sjmallett fail |= cvmx_error_add(&info); 6396215976Sjmallett 6397215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6398215976Sjmallett info.status_addr = CVMX_PEXP_SLI_INT_SUM; 6399215976Sjmallett info.status_mask = 1ull<<55 /* pins_err */; 6400215976Sjmallett info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU; 6401215976Sjmallett info.enable_mask = 1ull<<55 /* pins_err */; 6402215976Sjmallett info.flags = 0; 6403215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6404215976Sjmallett info.group_index = 0; 6405215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6406215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 6407215976Sjmallett info.parent.status_mask = 1ull<<3 /* sli */; 6408215976Sjmallett info.func = __cvmx_error_display; 6409215976Sjmallett info.user_info = (long) 6410215976Sjmallett "ERROR PEXP_SLI_INT_SUM[PINS_ERR]: When a read error occurs on a packet instruction\n" 6411215976Sjmallett " this bit is set.\n"; 6412215976Sjmallett fail |= cvmx_error_add(&info); 6413215976Sjmallett 6414215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6415215976Sjmallett info.status_addr = CVMX_PEXP_SLI_INT_SUM; 6416215976Sjmallett info.status_mask = 1ull<<56 /* sprt0_err */; 6417215976Sjmallett info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU; 6418215976Sjmallett info.enable_mask = 1ull<<56 /* sprt0_err */; 6419215976Sjmallett info.flags = 0; 6420215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6421215976Sjmallett info.group_index = 0; 6422215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6423215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 6424215976Sjmallett info.parent.status_mask = 1ull<<3 /* sli */; 6425215976Sjmallett info.func = __cvmx_error_display; 6426215976Sjmallett info.user_info = (long) 6427215976Sjmallett "ERROR PEXP_SLI_INT_SUM[SPRT0_ERR]: When an error response received on SLI port 0\n" 6428215976Sjmallett " this bit is set.\n"; 6429215976Sjmallett fail |= cvmx_error_add(&info); 6430215976Sjmallett 6431215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6432215976Sjmallett info.status_addr = CVMX_PEXP_SLI_INT_SUM; 6433215976Sjmallett info.status_mask = 1ull<<57 /* sprt1_err */; 6434215976Sjmallett info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU; 6435215976Sjmallett info.enable_mask = 1ull<<57 /* sprt1_err */; 6436215976Sjmallett info.flags = 0; 6437215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6438215976Sjmallett info.group_index = 0; 6439215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6440215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 6441215976Sjmallett info.parent.status_mask = 1ull<<3 /* sli */; 6442215976Sjmallett info.func = __cvmx_error_display; 6443215976Sjmallett info.user_info = (long) 6444215976Sjmallett "ERROR PEXP_SLI_INT_SUM[SPRT1_ERR]: When an error response received on SLI port 1\n" 6445215976Sjmallett " this bit is set.\n"; 6446215976Sjmallett fail |= cvmx_error_add(&info); 6447215976Sjmallett 6448215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6449215976Sjmallett info.status_addr = CVMX_PEXP_SLI_INT_SUM; 6450215976Sjmallett info.status_mask = 1ull<<60 /* ill_pad */; 6451215976Sjmallett info.enable_addr = CVMX_PEXP_SLI_INT_ENB_CIU; 6452215976Sjmallett info.enable_mask = 1ull<<60 /* ill_pad */; 6453215976Sjmallett info.flags = 0; 6454215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6455215976Sjmallett info.group_index = 0; 6456215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6457215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 6458215976Sjmallett info.parent.status_mask = 1ull<<3 /* sli */; 6459215976Sjmallett info.func = __cvmx_error_display; 6460215976Sjmallett info.user_info = (long) 6461215976Sjmallett "ERROR PEXP_SLI_INT_SUM[ILL_PAD]: Set when a BAR0 address R/W falls into theaddress\n" 6462215976Sjmallett " range of the Packet-CSR, but for an unused\n" 6463215976Sjmallett " address.\n"; 6464215976Sjmallett fail |= cvmx_error_add(&info); 6465215976Sjmallett 6466215976Sjmallett /* CVMX_DPI_INT_REG */ 6467215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6468215976Sjmallett info.status_addr = CVMX_DPI_INT_REG; 6469215976Sjmallett info.status_mask = 1ull<<0 /* nderr */; 6470215976Sjmallett info.enable_addr = CVMX_DPI_INT_EN; 6471215976Sjmallett info.enable_mask = 1ull<<0 /* nderr */; 6472215976Sjmallett info.flags = 0; 6473215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6474215976Sjmallett info.group_index = 0; 6475215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6476215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 6477215976Sjmallett info.parent.status_mask = 1ull<<41 /* dpi */; 6478215976Sjmallett info.func = __cvmx_error_display; 6479215976Sjmallett info.user_info = (long) 6480215976Sjmallett "ERROR DPI_INT_REG[NDERR]: NCB Decode Error\n" 6481215976Sjmallett " DPI received a NCB transaction on the outbound\n" 6482215976Sjmallett " bus to the DPI deviceID, but the command was not\n" 6483215976Sjmallett " recognized.\n"; 6484215976Sjmallett fail |= cvmx_error_add(&info); 6485215976Sjmallett 6486215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6487215976Sjmallett info.status_addr = CVMX_DPI_INT_REG; 6488215976Sjmallett info.status_mask = 1ull<<1 /* nfovr */; 6489215976Sjmallett info.enable_addr = CVMX_DPI_INT_EN; 6490215976Sjmallett info.enable_mask = 1ull<<1 /* nfovr */; 6491215976Sjmallett info.flags = 0; 6492215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6493215976Sjmallett info.group_index = 0; 6494215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6495215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 6496215976Sjmallett info.parent.status_mask = 1ull<<41 /* dpi */; 6497215976Sjmallett info.func = __cvmx_error_display; 6498215976Sjmallett info.user_info = (long) 6499215976Sjmallett "ERROR DPI_INT_REG[NFOVR]: CSR Fifo Overflow\n" 6500215976Sjmallett " DPI can store upto 16 CSR request. The FIFO will\n" 6501215976Sjmallett " overflow if that number is exceeded.\n"; 6502215976Sjmallett fail |= cvmx_error_add(&info); 6503215976Sjmallett 6504215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6505215976Sjmallett info.status_addr = CVMX_DPI_INT_REG; 6506215976Sjmallett info.status_mask = 0xffull<<8 /* dmadbo */; 6507215976Sjmallett info.enable_addr = CVMX_DPI_INT_EN; 6508215976Sjmallett info.enable_mask = 0xffull<<8 /* dmadbo */; 6509215976Sjmallett info.flags = 0; 6510215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6511215976Sjmallett info.group_index = 0; 6512215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6513215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 6514215976Sjmallett info.parent.status_mask = 1ull<<41 /* dpi */; 6515215976Sjmallett info.func = __cvmx_error_display; 6516215976Sjmallett info.user_info = (long) 6517215976Sjmallett "ERROR DPI_INT_REG[DMADBO]: DMAx doorbell overflow.\n" 6518215976Sjmallett " DPI has a 32-bit counter for each request's queue\n" 6519215976Sjmallett " outstanding doorbell counts. Interrupt will fire\n" 6520215976Sjmallett " if the count overflows.\n"; 6521215976Sjmallett fail |= cvmx_error_add(&info); 6522215976Sjmallett 6523215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6524215976Sjmallett info.status_addr = CVMX_DPI_INT_REG; 6525215976Sjmallett info.status_mask = 1ull<<16 /* req_badadr */; 6526215976Sjmallett info.enable_addr = CVMX_DPI_INT_EN; 6527215976Sjmallett info.enable_mask = 1ull<<16 /* req_badadr */; 6528215976Sjmallett info.flags = 0; 6529215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6530215976Sjmallett info.group_index = 0; 6531215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6532215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 6533215976Sjmallett info.parent.status_mask = 1ull<<41 /* dpi */; 6534215976Sjmallett info.func = __cvmx_error_display; 6535215976Sjmallett info.user_info = (long) 6536215976Sjmallett "ERROR DPI_INT_REG[REQ_BADADR]: DMA instruction fetch with bad pointer\n" 6537215976Sjmallett " Interrupt will fire if DPI forms an instruction\n" 6538215976Sjmallett " fetch to the NULL pointer.\n"; 6539215976Sjmallett fail |= cvmx_error_add(&info); 6540215976Sjmallett 6541215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6542215976Sjmallett info.status_addr = CVMX_DPI_INT_REG; 6543215976Sjmallett info.status_mask = 1ull<<17 /* req_badlen */; 6544215976Sjmallett info.enable_addr = CVMX_DPI_INT_EN; 6545215976Sjmallett info.enable_mask = 1ull<<17 /* req_badlen */; 6546215976Sjmallett info.flags = 0; 6547215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6548215976Sjmallett info.group_index = 0; 6549215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6550215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 6551215976Sjmallett info.parent.status_mask = 1ull<<41 /* dpi */; 6552215976Sjmallett info.func = __cvmx_error_display; 6553215976Sjmallett info.user_info = (long) 6554215976Sjmallett "ERROR DPI_INT_REG[REQ_BADLEN]: DMA instruction fetch with length\n" 6555215976Sjmallett " Interrupt will fire if DPI forms an instruction\n" 6556215976Sjmallett " fetch with length of zero.\n"; 6557215976Sjmallett fail |= cvmx_error_add(&info); 6558215976Sjmallett 6559215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6560215976Sjmallett info.status_addr = CVMX_DPI_INT_REG; 6561215976Sjmallett info.status_mask = 1ull<<18 /* req_ovrflw */; 6562215976Sjmallett info.enable_addr = CVMX_DPI_INT_EN; 6563215976Sjmallett info.enable_mask = 1ull<<18 /* req_ovrflw */; 6564215976Sjmallett info.flags = 0; 6565215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6566215976Sjmallett info.group_index = 0; 6567215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6568215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 6569215976Sjmallett info.parent.status_mask = 1ull<<41 /* dpi */; 6570215976Sjmallett info.func = __cvmx_error_display; 6571215976Sjmallett info.user_info = (long) 6572215976Sjmallett "ERROR DPI_INT_REG[REQ_OVRFLW]: DMA instruction FIFO overflow\n" 6573215976Sjmallett " DPI tracks outstanding instructions fetches.\n" 6574215976Sjmallett " Interrupt will fire when FIFO overflows.\n"; 6575215976Sjmallett fail |= cvmx_error_add(&info); 6576215976Sjmallett 6577215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6578215976Sjmallett info.status_addr = CVMX_DPI_INT_REG; 6579215976Sjmallett info.status_mask = 1ull<<19 /* req_undflw */; 6580215976Sjmallett info.enable_addr = CVMX_DPI_INT_EN; 6581215976Sjmallett info.enable_mask = 1ull<<19 /* req_undflw */; 6582215976Sjmallett info.flags = 0; 6583215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6584215976Sjmallett info.group_index = 0; 6585215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6586215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 6587215976Sjmallett info.parent.status_mask = 1ull<<41 /* dpi */; 6588215976Sjmallett info.func = __cvmx_error_display; 6589215976Sjmallett info.user_info = (long) 6590215976Sjmallett "ERROR DPI_INT_REG[REQ_UNDFLW]: DMA instruction FIFO underflow\n" 6591215976Sjmallett " DPI tracks outstanding instructions fetches.\n" 6592215976Sjmallett " Interrupt will fire when FIFO underflows.\n"; 6593215976Sjmallett fail |= cvmx_error_add(&info); 6594215976Sjmallett 6595215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6596215976Sjmallett info.status_addr = CVMX_DPI_INT_REG; 6597215976Sjmallett info.status_mask = 1ull<<20 /* req_anull */; 6598215976Sjmallett info.enable_addr = CVMX_DPI_INT_EN; 6599215976Sjmallett info.enable_mask = 1ull<<20 /* req_anull */; 6600215976Sjmallett info.flags = 0; 6601215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6602215976Sjmallett info.group_index = 0; 6603215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6604215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 6605215976Sjmallett info.parent.status_mask = 1ull<<41 /* dpi */; 6606215976Sjmallett info.func = __cvmx_error_display; 6607215976Sjmallett info.user_info = (long) 6608215976Sjmallett "ERROR DPI_INT_REG[REQ_ANULL]: DMA instruction filled with bad instruction\n" 6609215976Sjmallett " Fetched instruction word was 0.\n"; 6610215976Sjmallett fail |= cvmx_error_add(&info); 6611215976Sjmallett 6612215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6613215976Sjmallett info.status_addr = CVMX_DPI_INT_REG; 6614215976Sjmallett info.status_mask = 1ull<<21 /* req_inull */; 6615215976Sjmallett info.enable_addr = CVMX_DPI_INT_EN; 6616215976Sjmallett info.enable_mask = 1ull<<21 /* req_inull */; 6617215976Sjmallett info.flags = 0; 6618215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6619215976Sjmallett info.group_index = 0; 6620215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6621215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 6622215976Sjmallett info.parent.status_mask = 1ull<<41 /* dpi */; 6623215976Sjmallett info.func = __cvmx_error_display; 6624215976Sjmallett info.user_info = (long) 6625215976Sjmallett "ERROR DPI_INT_REG[REQ_INULL]: DMA instruction filled with NULL pointer\n" 6626215976Sjmallett " Next pointer was NULL.\n"; 6627215976Sjmallett fail |= cvmx_error_add(&info); 6628215976Sjmallett 6629215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6630215976Sjmallett info.status_addr = CVMX_DPI_INT_REG; 6631215976Sjmallett info.status_mask = 1ull<<22 /* req_badfil */; 6632215976Sjmallett info.enable_addr = CVMX_DPI_INT_EN; 6633215976Sjmallett info.enable_mask = 1ull<<22 /* req_badfil */; 6634215976Sjmallett info.flags = 0; 6635215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6636215976Sjmallett info.group_index = 0; 6637215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6638215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 6639215976Sjmallett info.parent.status_mask = 1ull<<41 /* dpi */; 6640215976Sjmallett info.func = __cvmx_error_display; 6641215976Sjmallett info.user_info = (long) 6642215976Sjmallett "ERROR DPI_INT_REG[REQ_BADFIL]: DMA instruction unexpected fill\n" 6643215976Sjmallett " Instruction fill when none outstanding.\n"; 6644215976Sjmallett fail |= cvmx_error_add(&info); 6645215976Sjmallett 6646215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6647215976Sjmallett info.status_addr = CVMX_DPI_INT_REG; 6648215976Sjmallett info.status_mask = 1ull<<24 /* sprt0_rst */; 6649215976Sjmallett info.enable_addr = CVMX_DPI_INT_EN; 6650215976Sjmallett info.enable_mask = 1ull<<24 /* sprt0_rst */; 6651215976Sjmallett info.flags = 0; 6652215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6653215976Sjmallett info.group_index = 0; 6654215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6655215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 6656215976Sjmallett info.parent.status_mask = 1ull<<41 /* dpi */; 6657215976Sjmallett info.func = __cvmx_error_display; 6658215976Sjmallett info.user_info = (long) 6659215976Sjmallett "ERROR DPI_INT_REG[SPRT0_RST]: DMA instruction was dropped because the source or\n" 6660215976Sjmallett " destination port was in reset.\n" 6661215976Sjmallett " this bit is set.\n"; 6662215976Sjmallett fail |= cvmx_error_add(&info); 6663215976Sjmallett 6664215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6665215976Sjmallett info.status_addr = CVMX_DPI_INT_REG; 6666215976Sjmallett info.status_mask = 1ull<<25 /* sprt1_rst */; 6667215976Sjmallett info.enable_addr = CVMX_DPI_INT_EN; 6668215976Sjmallett info.enable_mask = 1ull<<25 /* sprt1_rst */; 6669215976Sjmallett info.flags = 0; 6670215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6671215976Sjmallett info.group_index = 0; 6672215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6673215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 6674215976Sjmallett info.parent.status_mask = 1ull<<41 /* dpi */; 6675215976Sjmallett info.func = __cvmx_error_display; 6676215976Sjmallett info.user_info = (long) 6677215976Sjmallett "ERROR DPI_INT_REG[SPRT1_RST]: DMA instruction was dropped because the source or\n" 6678215976Sjmallett " destination port was in reset.\n" 6679215976Sjmallett " this bit is set.\n"; 6680215976Sjmallett fail |= cvmx_error_add(&info); 6681215976Sjmallett 6682215976Sjmallett /* CVMX_DPI_PKT_ERR_RSP */ 6683215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6684215976Sjmallett info.status_addr = CVMX_DPI_PKT_ERR_RSP; 6685215976Sjmallett info.status_mask = 1ull<<0 /* pkterr */; 6686215976Sjmallett info.enable_addr = 0; 6687215976Sjmallett info.enable_mask = 0; 6688215976Sjmallett info.flags = 0; 6689215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6690215976Sjmallett info.group_index = 0; 6691215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6692215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 6693215976Sjmallett info.parent.status_mask = 1ull<<41 /* dpi */; 6694215976Sjmallett info.func = __cvmx_error_display; 6695215976Sjmallett info.user_info = (long) 6696215976Sjmallett "ERROR DPI_PKT_ERR_RSP[PKTERR]: Indicates that an ErrorResponse was received from\n" 6697215976Sjmallett " the I/O subsystem.\n"; 6698215976Sjmallett fail |= cvmx_error_add(&info); 6699215976Sjmallett 6700215976Sjmallett /* CVMX_DPI_REQ_ERR_RSP */ 6701215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6702215976Sjmallett info.status_addr = CVMX_DPI_REQ_ERR_RSP; 6703215976Sjmallett info.status_mask = 0xffull<<0 /* qerr */; 6704215976Sjmallett info.enable_addr = 0; 6705215976Sjmallett info.enable_mask = 0; 6706215976Sjmallett info.flags = 0; 6707215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6708215976Sjmallett info.group_index = 0; 6709215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6710215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 6711215976Sjmallett info.parent.status_mask = 1ull<<41 /* dpi */; 6712215976Sjmallett info.func = __cvmx_error_display; 6713215976Sjmallett info.user_info = (long) 6714215976Sjmallett "ERROR DPI_REQ_ERR_RSP[QERR]: Indicates which instruction queue received an\n" 6715215976Sjmallett " ErrorResponse from the I/O subsystem.\n" 6716215976Sjmallett " SW must clear the bit before the the cooresponding\n" 6717215976Sjmallett " instruction queue will continue processing\n" 6718215976Sjmallett " instructions if DPI_REQ_ERR_RSP_EN[EN] is set.\n"; 6719215976Sjmallett fail |= cvmx_error_add(&info); 6720215976Sjmallett 6721215976Sjmallett /* CVMX_DPI_REQ_ERR_RST */ 6722215976Sjmallett info.reg_type = CVMX_ERROR_REGISTER_IO64; 6723215976Sjmallett info.status_addr = CVMX_DPI_REQ_ERR_RST; 6724215976Sjmallett info.status_mask = 0xffull<<0 /* qerr */; 6725215976Sjmallett info.enable_addr = 0; 6726215976Sjmallett info.enable_mask = 0; 6727215976Sjmallett info.flags = 0; 6728215976Sjmallett info.group = CVMX_ERROR_GROUP_INTERNAL; 6729215976Sjmallett info.group_index = 0; 6730215976Sjmallett info.parent.reg_type = CVMX_ERROR_REGISTER_IO64; 6731215976Sjmallett info.parent.status_addr = CVMX_CIU_BLOCK_INT; 6732215976Sjmallett info.parent.status_mask = 1ull<<41 /* dpi */; 6733215976Sjmallett info.func = __cvmx_error_display; 6734215976Sjmallett info.user_info = (long) 6735215976Sjmallett "ERROR DPI_REQ_ERR_RST[QERR]: Indicates which instruction queue dropped an\n" 6736215976Sjmallett " instruction because the source or destination\n" 6737215976Sjmallett " was in reset.\n" 6738215976Sjmallett " SW must clear the bit before the the cooresponding\n" 6739215976Sjmallett " instruction queue will continue processing\n" 6740215976Sjmallett " instructions if DPI_REQ_ERR_RST_EN[EN] is set.\n"; 6741215976Sjmallett fail |= cvmx_error_add(&info); 6742215976Sjmallett 6743215976Sjmallett return fail; 6744215976Sjmallett} 6745215976Sjmallett 6746