1/***********************license start*************** 2 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Networks nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41 42 43 44 45 46 47/** 48 * @file 49 * 50 * Interface to the Trace buffer hardware. 51 * 52 * WRITING THE TRACE BUFFER 53 * 54 * When the trace is enabled, commands are traced continuously (wrapping) or until the buffer is filled once 55 * (no wrapping). Additionally and independent of wrapping, tracing can be temporarily enabled and disabled 56 * by the tracing triggers. All XMC commands can be traced except for IDLE and IOBRSP. The subset of XMC 57 * commands that are traced is determined by the filter and the two triggers, each of which is comprised of 58 * masks for command, sid, did, and address). If triggers are disabled, then only those commands matching 59 * the filter are traced. If triggers are enabled, then only those commands matching the filter, the start 60 * trigger, or the stop trigger are traced during the time between a start trigger and a stop trigger. 61 * 62 * For a given command, its XMC data is written immediately to the buffer. If the command has XMD data, 63 * then that data comes in-order at some later time. The XMD data is accumulated across all valid 64 * XMD cycles and written to the buffer or to a shallow fifo. Data from the fifo is written to the buffer 65 * as soon as it gets access to write the buffer (i.e. the buffer is not currently being written with XMC 66 * data). If the fifo overflows, it simply overwrites itself and the previous XMD data is lost. 67 * 68 * 69 * READING THE TRACE BUFFER 70 * 71 * Each entry of the trace buffer is read by a CSR read command. The trace buffer services each read in order, 72 * as soon as it has access to the (single-ported) trace buffer. 73 * 74 * On Octeon2, each entry of the trace buffer is read by two CSR memory read operations. The first read accesses 75 * bits 63:0 of the buffer entry, and the second read accesses bits 68:64 of the buffer entry. The trace buffer 76 * services each read in order, as soon as it has access to the (single-ported) trace buffer. Buffer's read pointer 77 * increments after two CSR memory read operations. 78 * 79 * 80 * OVERFLOW, UNDERFLOW AND THRESHOLD EVENTS 81 * 82 * The trace buffer maintains a write pointer and a read pointer and detects both the overflow and underflow 83 * conditions. Each time a new trace is enabled, both pointers are reset to entry 0. Normally, each write 84 * (traced event) increments the write pointer and each read increments the read pointer. During the overflow 85 * condition, writing (tracing) is disabled. Tracing will continue as soon as the overflow condition is 86 * resolved. The first entry that is written immediately following the overflow condition may be marked to 87 * indicate that a tracing discontinuity has occurred before this entry. During the underflow condition, 88 * reading does not increment the read pointer and the read data is marked to indicate that no read data is 89 * available. 90 * 91 * The full threshold events are defined to signal an interrupt a certain levels of "fullness" (1/2, 3/4, 4/4). 92 * "fullness" is defined as the relative distance between the write and read pointers (i.e. not defined as the 93 * absolute distance between the write pointer and entry 0). When enabled, the full threshold event occurs 94 * every time the desired level of "fullness" is achieved. 95 * 96 * 97 * Trace buffer entry format 98 * @verbatim 99 * 6 5 4 3 2 1 0 100 * 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 101 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 102 * |sta| address[35:3] | 0 | src id | 0 | DWB | diff timestamp| 103 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 104 * |sta| address[35:3] | 0 | src id | 0 | PL2 | diff timestamp| 105 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 106 * |sta| address[35:3] | 0 | src id | 0 | PSL1 | diff timestamp| 107 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 108 * |sta| address[35:3] | 0 | src id | 0 | LDD | diff timestamp| 109 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 110 * |sta| address[35:3] | 0 | src id | 0 | LDI | diff timestamp| 111 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 112 * |sta| address[35:3] | 0 | src id | 0 | LDT | diff timestamp| 113 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 114 * |sta| address[35:3] | * or 16B mask | src id | 0 | STC | diff timestamp| 115 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 116 * |sta| address[35:3] | * or 16B mask | src id | 0 | STF | diff timestamp| 117 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 118 * |sta| address[35:3] | * or 16B mask | src id | 0 | STP | diff timestamp| 119 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 120 * |sta| address[35:3] | * or 16B mask | src id | 0 | STT | diff timestamp| 121 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 122 * |sta| address[35:0] | 0 | src id| dest id |IOBLD8 | diff timestamp| 123 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 124 * |sta| address[35:1] | 0 | src id| dest id |IOBLD16| diff timestamp| 125 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 126 * |sta| address[35:2] | 0 | src id| dest id |IOBLD32| diff timestamp| 127 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 128 * |sta| address[35:3] | 0 | src id| dest id |IOBLD64| diff timestamp| 129 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 130 * |sta| address[35:3] | * or 16B mask | src id| dest id |IOBST | diff timestamp| 131 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 132 * |sta| * or address[35:3] | * or length | src id| dest id |IOBDMA | diff timestamp| 133 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 134 * 135 * 136 * Trace buffer entry format in Octeon2 is different 137 * 138 * 6 5 4 3 2 1 0 139 * 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 140 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 141 * |sta| address[37:0] | 0 | src id | Group 1 | diff timestamp| 142 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 143 * |sta| address[37:0] | 0 | xmd mask | src id | Group 2 | diff timestamp| 144 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 145 * |sta| address[37:0] | 0 |s-did| dest id | src id | Group 3 | diff timestamp| 146 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 147 * |sta| *address[37:3] | *Length | dest id | src id | Group 4 | diff timestamp| 148 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 149 * 150 * notes: 151 * - diff timestamp is the difference in time from the previous trace event to this event - 1. the granularity of the timestamp is programmable 152 * - Fields marked as '*' are first filled with '0' at XMC time and may be filled with real data later at XMD time. Note that the 153 * XMD write may be dropped if the shallow FIFO overflows which leaves the '*' fields as '0'. 154 * - 2 bits (sta) are used not to trace, but to return global state information with each read, encoded as follows: 155 * 0x0-0x1=not valid 156 * 0x2=valid, no discontinuity 157 * 0x3=valid, discontinuity 158 * - commands are encoded as follows: 159 * 0x0=DWB 160 * 0x1=PL2 161 * 0x2=PSL1 162 * 0x3=LDD 163 * 0x4=LDI 164 * 0x5=LDT 165 * 0x6=STF 166 * 0x7=STC 167 * 0x8=STP 168 * 0x9=STT 169 * 0xa=IOBLD8 170 * 0xb=IOBLD16 171 * 0xc=IOBLD32 172 * 0xd=IOBLD64 173 * 0xe=IOBST 174 * 0xf=IOBDMA 175 * - In Octeon2 the commands are grouped as follows: 176 * Group1: 177 * XMC_LDT, XMC_LDI, XMC_PL2, XMC_RPL2, XMC_DWB, XMC_WBL2, 178 * XMC_SET8, XMC_SET16, XMC_SET32, XMC_SET64, 179 * XMC_CLR8, XMC_CLR16, XMC_CLR32, XMC_CLR64, 180 * XMC_INCR8, XMC_INCR16, XMC_INCR32, XMC_INCR64, 181 * XMC_DECR8, XMC_DECR16, XMC_DECR32, XMC_DECR64 182 * Group2: 183 * XMC_STF, XMC_STT, XMC_STP, XMC_STC, 184 * XMC_LDD, XMC_PSL1 185 * XMC_SAA32, XMC_SAA64, 186 * XMC_FAA32, XMC_FAA64, 187 * XMC_FAS32, XMC_FAS64 188 * Group3: 189 * XMC_IOBLD8, XMC_IOBLD16, XMC_IOBLD32, XMC_IOBLD64, 190 * XMC_IOBST8, XMC_IOBST16, XMC_IOBST32, XMC_IOBST64 191 * Group4: 192 * XMC_IOBDMA 193 * - For non IOB* commands 194 * - source id is encoded as follows: 195 * 0x00-0x0f=PP[n] 196 * 0x10=IOB(Packet) 197 * 0x11=IOB(PKO) 198 * 0x12=IOB(ReqLoad, ReqStore) 199 * 0x13=IOB(DWB) 200 * 0x14-0x1e=illegal 201 * 0x1f=IOB(generic) 202 * - dest id is unused (can only be L2c) 203 * - For IOB* commands 204 * - source id is encoded as follows: 205 * 0x00-0x0f = PP[n] 206 * - dest id is encoded as follows: 207 * 0 = CIU/GPIO (for CSRs) 208 * 1-2 = illegal 209 * 3 = PCIe (access to RSL-type CSRs) 210 * 4 = KEY (read/write operations) 211 * 5 = FPA (free pool allocate/free operations) 212 * 6 = DFA 213 * 7 = ZIP (doorbell operations) 214 * 8 = RNG (load/IOBDMA operations) 215 * 10 = PKO (doorbell operations) 216 * 11 = illegal 217 * 12 = POW (get work, add work, status/memory/index loads, NULLrd load operations, CSR operations) 218 * 13-31 = illegal 219 * @endverbatim 220 * 221 * <hr>$Revision: 49484 $<hr> 222 */ 223 224#ifndef __CVMX_TRA_H__ 225#define __CVMX_TRA_H__ 226 227#include "cvmx.h" 228#ifdef CVMX_BUILD_FOR_LINUX_KERNEL 229#include "cvmx-tra-defs.h" 230#endif 231 232#ifdef __cplusplus 233extern "C" { 234#endif 235 236 237/* CSR typedefs have been moved to cvmx-tra-defs.h */ 238 239/* The 'saa' filter command is renamed as 'saa64' */ 240#define CVMX_TRA_FILT_SAA CVMX_TRA_FILT_SAA64 241/* The 'iobst' filter command is renamed as 'iobst64' */ 242#define CVMX_TRA_FILT_IOBST CVMX_TRA_FILT_IOBST64 243 244/** 245 * Enumeration of the bitmask of all the filter commands. The bit positions 246 * correspond to Octeon2 model. 247 */ 248typedef enum 249{ 250 CVMX_TRA_FILT_NOP = 1ull<<0, /**< none */ 251 CVMX_TRA_FILT_LDT = 1ull<<1, /**< don't allocate L2 or L1 */ 252 CVMX_TRA_FILT_LDI = 1ull<<2, /**< don't allocate L1 */ 253 CVMX_TRA_FILT_PL2 = 1ull<<3, /**< pref L2 */ 254 CVMX_TRA_FILT_RPL2 = 1ull<<4, /**< mark for replacement in L2 */ 255 CVMX_TRA_FILT_DWB = 1ull<<5, /**< clear L2 dirty bit (no writeback) + RPL2 */ 256 CVMX_TRA_FILT_LDD = 1ull<<8, /**< normal load */ 257 CVMX_TRA_FILT_PSL1 = 1ull<<9, /**< pref L1, bypass L2 */ 258 CVMX_TRA_FILT_IOBDMA = 1ull<<15, /**< store reflection by IOB for prior load */ 259 CVMX_TRA_FILT_STF = 1ull<<16, /**< full block store to L2, fill 0's */ 260 CVMX_TRA_FILT_STT = 1ull<<17, /**< full block store bypass-L2, fill 0's */ 261 CVMX_TRA_FILT_STP = 1ull<<18, /**< partial store to L2 */ 262 CVMX_TRA_FILT_STC = 1ull<<19, /**< partial store to L2, if duptag valid */ 263 CVMX_TRA_FILT_STFIL1 = 1ull<<20, /**< full block store to L2, fill 0's, invalidate L1 */ 264 CVMX_TRA_FILT_STTIL1 = 1ull<<21, /**< full block store bypass-L2, fill 0's, invalidate L1 */ 265 CVMX_TRA_FILT_FAS32 = 1ull<<22, /**< to load from and write a word of memory atomically */ 266 CVMX_TRA_FILT_FAS64 = 1ull<<23, /**< to load from and write a doubleword of memory atomically */ 267 CVMX_TRA_FILT_WBIL2I = 1ull<<24, /**< writeback if dirty, invalidate, clear use bit, by index/way */ 268 CVMX_TRA_FILT_LTGL2I = 1ull<<25, /**< read tag @ index/way into CSR */ 269 CVMX_TRA_FILT_STGL2I = 1ull<<26, /**< write tag @ index/way from CSR */ 270 CVMX_TRA_FILT_INVL2 = 1ull<<28, /**< invalidate, clear use bit, by address (dirty data is LOST) */ 271 CVMX_TRA_FILT_WBIL2 = 1ull<<29, /**< writeback if dirty, invalidate, clear use bit, by address */ 272 CVMX_TRA_FILT_WBL2 = 1ull<<30, /**< writeback if dirty, make clean, clear use bit, by address */ 273 CVMX_TRA_FILT_LCKL2 = 1ull<<31, /**< allocate (if miss), set lock bit, set use bit, by address */ 274 CVMX_TRA_FILT_IOBLD8 = 1ull<<32, /**< load reflection 8bit */ 275 CVMX_TRA_FILT_IOBLD16 = 1ull<<33, /**< load reflection 16bit */ 276 CVMX_TRA_FILT_IOBLD32 = 1ull<<34, /**< load reflection 32bit */ 277 CVMX_TRA_FILT_IOBLD64 = 1ull<<35, /**< load reflection 64bit */ 278 CVMX_TRA_FILT_IOBST8 = 1ull<<36, /**< store reflection 8bit */ 279 CVMX_TRA_FILT_IOBST16 = 1ull<<37, /**< store reflection 16bit */ 280 CVMX_TRA_FILT_IOBST32 = 1ull<<38, /**< store reflection 32bit */ 281 CVMX_TRA_FILT_IOBST64 = 1ull<<39, /**< store reflection 64bit */ 282 CVMX_TRA_FILT_SET8 = 1ull<<40, /**< to load from and write 1's to 8bit of memory atomically */ 283 CVMX_TRA_FILT_SET16 = 1ull<<41, /**< to load from and write 1's to 16bit of memory atomically */ 284 CVMX_TRA_FILT_SET32 = 1ull<<42, /**< to load from and write 1's to 32bit of memory atomically */ 285 CVMX_TRA_FILT_SET64 = 1ull<<43, /**< to load from and write 1's to 64bit of memory atomically */ 286 CVMX_TRA_FILT_CLR8 = 1ull<<44, /**< to load from and write 0's to 8bit of memory atomically */ 287 CVMX_TRA_FILT_CLR16 = 1ull<<45, /**< to load from and write 0's to 16bit of memory atomically */ 288 CVMX_TRA_FILT_CLR32 = 1ull<<46, /**< to load from and write 0's to 32bit of memory atomically */ 289 CVMX_TRA_FILT_CLR64 = 1ull<<47, /**< to load from and write 0's to 64bit of memory atomically */ 290 CVMX_TRA_FILT_INCR8 = 1ull<<48, /**< to load and increment 8bit of memory atomically */ 291 CVMX_TRA_FILT_INCR16 = 1ull<<49, /**< to load and increment 16bit of memory atomically */ 292 CVMX_TRA_FILT_INCR32 = 1ull<<50, /**< to load and increment 32bit of memory atomically */ 293 CVMX_TRA_FILT_INCR64 = 1ull<<51, /**< to load and increment 64bit of memory atomically */ 294 CVMX_TRA_FILT_DECR8 = 1ull<<52, /**< to load and decrement 8bit of memory atomically */ 295 CVMX_TRA_FILT_DECR16 = 1ull<<53, /**< to load and decrement 16bit of memory atomically */ 296 CVMX_TRA_FILT_DECR32 = 1ull<<54, /**< to load and decrement 32bit of memory atomically */ 297 CVMX_TRA_FILT_DECR64 = 1ull<<55, /**< to load and decrement 64bit of memory atomically */ 298 CVMX_TRA_FILT_FAA32 = 1ull<<58, /**< to load from and add to a word of memory atomically */ 299 CVMX_TRA_FILT_FAA64 = 1ull<<59, /**< to load from and add to a doubleword of memory atomically */ 300 CVMX_TRA_FILT_SAA32 = 1ull<<62, /**< to atomically add a word to a memory location */ 301 CVMX_TRA_FILT_SAA64 = 1ull<<63, /**< to atomically add a doubleword to a memory location */ 302 CVMX_TRA_FILT_ALL = -1ull /**< all the above filter commands */ 303} cvmx_tra_filt_t; 304 305/* 306 * Enumeration of the bitmask of all source commands. 307 */ 308typedef enum 309{ 310 CVMX_TRA_SID_PP0 = 1ull<<0, /**< Enable tracing from PP0 with matching sourceID */ 311 CVMX_TRA_SID_PP1 = 1ull<<1, /**< Enable tracing from PP1 with matching sourceID */ 312 CVMX_TRA_SID_PP2 = 1ull<<2, /**< Enable tracing from PP2 with matching sourceID */ 313 CVMX_TRA_SID_PP3 = 1ull<<3, /**< Enable tracing from PP3 with matching sourceID */ 314 CVMX_TRA_SID_PP4 = 1ull<<4, /**< Enable tracing from PP4 with matching sourceID */ 315 CVMX_TRA_SID_PP5 = 1ull<<5, /**< Enable tracing from PP5 with matching sourceID */ 316 CVMX_TRA_SID_PP6 = 1ull<<6, /**< Enable tracing from PP6 with matching sourceID */ 317 CVMX_TRA_SID_PP7 = 1ull<<7, /**< Enable tracing from PP7 with matching sourceID */ 318 CVMX_TRA_SID_PP8 = 1ull<<8, /**< Enable tracing from PP8 with matching sourceID */ 319 CVMX_TRA_SID_PP9 = 1ull<<9, /**< Enable tracing from PP9 with matching sourceID */ 320 CVMX_TRA_SID_PP10 = 1ull<<10, /**< Enable tracing from PP10 with matching sourceID */ 321 CVMX_TRA_SID_PP11 = 1ull<<11, /**< Enable tracing from PP11 with matching sourceID */ 322 CVMX_TRA_SID_PP12 = 1ull<<12, /**< Enable tracing from PP12 with matching sourceID */ 323 CVMX_TRA_SID_PP13 = 1ull<<13, /**< Enable tracing from PP13 with matching sourceID */ 324 CVMX_TRA_SID_PP14 = 1ull<<14, /**< Enable tracing from PP14 with matching sourceID */ 325 CVMX_TRA_SID_PP15 = 1ull<<15, /**< Enable tracing from PP15 with matching sourceID */ 326 CVMX_TRA_SID_PKI = 1ull<<16, /**< Enable tracing of write requests from PIP/IPD */ 327 CVMX_TRA_SID_PKO = 1ull<<17, /**< Enable tracing of write requests from PKO */ 328 CVMX_TRA_SID_IOBREQ = 1ull<<18, /**< Enable tracing of write requests from FPA,TIM,DFA,PCI,ZIP,POW, and PKO (writes) */ 329 CVMX_TRA_SID_DWB = 1ull<<19, /**< Enable tracing of write requests from IOB DWB engine */ 330 CVMX_TRA_SID_ALL = -1ull /**< Enable tracing all the above source commands */ 331} cvmx_tra_sid_t; 332 333 334#define CVMX_TRA_DID_SLI CVMX_TRA_DID_PCI /**< Enable tracing of requests to SLI and RSL-type CSRs. */ 335/* 336 * Enumeration of the bitmask of all destination commands. 337 */ 338typedef enum 339{ 340 CVMX_TRA_DID_MIO = 1ull<<0, /**< Enable tracing of CIU and GPIO CSR's */ 341 CVMX_TRA_DID_PCI = 1ull<<3, /**< Enable tracing of requests to PCI and RSL type CSR's */ 342 CVMX_TRA_DID_KEY = 1ull<<4, /**< Enable tracing of requests to KEY memory */ 343 CVMX_TRA_DID_FPA = 1ull<<5, /**< Enable tracing of requests to FPA */ 344 CVMX_TRA_DID_DFA = 1ull<<6, /**< Enable tracing of requests to DFA */ 345 CVMX_TRA_DID_ZIP = 1ull<<7, /**< Enable tracing of requests to ZIP */ 346 CVMX_TRA_DID_RNG = 1ull<<8, /**< Enable tracing of requests to RNG */ 347 CVMX_TRA_DID_IPD = 1ull<<9, /**< Enable tracing of IPD CSR accesses */ 348 CVMX_TRA_DID_PKO = 1ull<<10, /**< Enable tracing of PKO accesses (doorbells) */ 349 CVMX_TRA_DID_POW = 1ull<<12, /**< Enable tracing of requests to RNG */ 350 CVMX_TRA_DID_USB0 = 1ull<<13, /**< Enable tracing of USB0 accesses (UAHC0 EHCI and OHCI NCB CSRs) */ 351 CVMX_TRA_DID_RAD = 1ull<<14, /**< Enable tracing of RAD accesses (doorbells) */ 352 CVMX_TRA_DID_DPI = 1ull<<27, /**< Enable tracing of DPI accesses (DPI NCD CSRs) */ 353 CVMX_TRA_DID_FAU = 1ull<<30, /**< Enable tracing FAU accesses */ 354 CVMX_TRA_DID_ALL = -1ull /**< Enable tracing all the above destination commands */ 355} cvmx_tra_did_t; 356 357/** 358 * TRA data format definition. Use the type field to 359 * determine which union element to use. 360 * 361 * In Octeon 2, the trace buffer is 69 bits, 362 * the first read accesses bits 63:0 of the trace buffer entry, and 363 * the second read accesses bits 68:64 of the trace buffer entry. 364 */ 365typedef union 366{ 367 struct 368 { 369#if __BYTE_ORDER == __BIG_ENDIAN 370 uint64_t datahi; 371 uint64_t data; 372#else 373 uint64_t data; 374 uint64_t datahi; 375#endif 376 } u128; 377 378 struct 379 { 380#if __BYTE_ORDER == __BIG_ENDIAN 381 uint64_t reserved3 : 64; 382 uint64_t valid : 1; 383 uint64_t discontinuity:1; 384 uint64_t address : 36; 385 uint64_t reserved : 5; 386 uint64_t source : 5; 387 uint64_t reserved2 : 3; 388 uint64_t type : 5; 389 uint64_t timestamp : 8; 390#else 391 uint64_t timestamp : 8; 392 uint64_t type : 5; 393 uint64_t reserved2 : 3; 394 uint64_t source : 5; 395 uint64_t reserved : 5; 396 uint64_t address : 36; 397 uint64_t discontinuity:1; 398 uint64_t valid : 1; 399 uint64_t reserved3 : 64; 400#endif 401 } cmn; /**< for DWB, PL2, PSL1, LDD, LDI, LDT */ 402 struct 403 { 404#if __BYTE_ORDER == __BIG_ENDIAN 405 uint64_t reserved3 : 64; 406 uint64_t valid : 1; 407 uint64_t discontinuity:1; 408 uint64_t address : 33; 409 uint64_t mask : 8; 410 uint64_t source : 5; 411 uint64_t reserved2 : 3; 412 uint64_t type : 5; 413 uint64_t timestamp : 8; 414#else 415 uint64_t timestamp : 8; 416 uint64_t type : 5; 417 uint64_t reserved2 : 3; 418 uint64_t source : 5; 419 uint64_t mask : 8; 420 uint64_t address : 33; 421 uint64_t discontinuity:1; 422 uint64_t valid : 1; 423 uint64_t reserved3 : 64; 424#endif 425 } store; /**< STC, STF, STP, STT */ 426 struct 427 { 428#if __BYTE_ORDER == __BIG_ENDIAN 429 uint64_t reserved3 : 64; 430 uint64_t valid : 1; 431 uint64_t discontinuity:1; 432 uint64_t address : 36; 433 uint64_t reserved : 2; 434 uint64_t subid : 3; 435 uint64_t source : 4; 436 uint64_t dest : 5; 437 uint64_t type : 4; 438 uint64_t timestamp : 8; 439#else 440 uint64_t timestamp : 8; 441 uint64_t type : 4; 442 uint64_t dest : 5; 443 uint64_t source : 4; 444 uint64_t subid : 3; 445 uint64_t reserved : 2; 446 uint64_t address : 36; 447 uint64_t discontinuity:1; 448 uint64_t valid : 1; 449 uint64_t reserved3 : 64; 450#endif 451 } iobld; /**< for IOBLD8, IOBLD16, IOBLD32, IOBLD64, IOBST, SAA */ 452 struct 453 { 454#if __BYTE_ORDER == __BIG_ENDIAN 455 uint64_t reserved3 : 64; 456 uint64_t valid : 1; 457 uint64_t discontinuity:1; 458 uint64_t address : 33; 459 uint64_t mask : 8; 460 uint64_t source : 4; 461 uint64_t dest : 5; 462 uint64_t type : 4; 463 uint64_t timestamp : 8; 464#else 465 uint64_t timestamp : 8; 466 uint64_t type : 4; 467 uint64_t dest : 5; 468 uint64_t source : 4; 469 uint64_t mask : 8; 470 uint64_t address : 33; 471 uint64_t discontinuity:1; 472 uint64_t valid : 1; 473 uint64_t reserved3 : 64; 474#endif 475 } iob; /**< for IOBDMA */ 476 477 struct 478 { 479#if __BYTE_ORDER == __BIG_ENDIAN 480 uint64_t reserved1 : 59; 481 uint64_t valid : 1; 482 uint64_t discontinuity:1; 483 uint64_t addresshi : 3; /* Split the address to fit in upper 64 bits */ 484 uint64_t addresslo : 35; /* and lower 64-bits. */ 485 uint64_t reserved : 10; 486 uint64_t source : 5; 487 uint64_t type : 6; 488 uint64_t timestamp : 8; 489#else 490 uint64_t timestamp : 8; 491 uint64_t type : 6; 492 uint64_t source : 5; 493 uint64_t reserved : 10; 494 uint64_t addresslo : 35; 495 uint64_t addresshi : 3; 496 uint64_t discontinuity:1; 497 uint64_t valid : 1; 498 uint64_t reserved1 : 59; 499#endif 500 } cmn2; /**< for LDT, LDI, PL2, RPL2, DWB, WBL2, SET*, CLR*, INCR*, DECR* */ 501 struct 502 { 503#if __BYTE_ORDER == __BIG_ENDIAN 504 uint64_t reserved1 : 59; 505 uint64_t valid : 1; 506 uint64_t discontinuity:1; 507 uint64_t addresshi : 3; /* Split the address to fit in upper 64 bits */ 508 uint64_t addresslo : 35; /* and lower 64-bits */ 509 uint64_t reserved : 2; 510 uint64_t mask : 8; 511 uint64_t source : 5; 512 uint64_t type : 6; 513 uint64_t timestamp : 8; 514#else 515 uint64_t timestamp : 8; 516 uint64_t type : 6; 517 uint64_t source : 5; 518 uint64_t mask : 8; 519 uint64_t reserved : 2; 520 uint64_t addresslo : 35; 521 uint64_t addresshi : 3; 522 uint64_t discontinuity:1; 523 uint64_t valid : 1; 524 uint64_t reserved1 : 59; 525#endif 526 } store2; /**< for STC, STF, STP, STT, LDD, PSL1, SAA32, SAA64, FAA32, FAA64, FAS32, FAS64 */ 527 struct 528 { 529#if __BYTE_ORDER == __BIG_ENDIAN 530 uint64_t reserved1 : 59; 531 uint64_t valid : 1; 532 uint64_t discontinuity:1; 533 uint64_t addresshi : 3; /* Split the address to fit in upper 64 bits */ 534 uint64_t addresslo : 35; /* and lower 64-bits */ 535 uint64_t reserved : 2; 536 uint64_t subid : 3; 537 uint64_t dest : 5; 538 uint64_t source : 5; 539 uint64_t type : 6; 540 uint64_t timestamp : 8; 541#else 542 uint64_t timestamp : 8; 543 uint64_t type : 6; 544 uint64_t source : 5; 545 uint64_t dest : 5; 546 uint64_t subid : 3; 547 uint64_t reserved : 2; 548 uint64_t addresslo : 35; 549 uint64_t addresshi : 3; 550 uint64_t discontinuity:1; 551 uint64_t valid : 1; 552 uint64_t reserved1 : 59; 553#endif 554 } iobld2; /**< for IOBLD8, IOBLD16, IOBLD32, IOBLD64, IOBST64, IOBST32, IOBST16, IOBST8 */ 555 struct 556 { 557#if __BYTE_ORDER == __BIG_ENDIAN 558 uint64_t reserved1 : 59; 559 uint64_t valid : 1; 560 uint64_t discontinuity:1; 561 uint64_t addresshi : 3; /* Split the address to fit in upper 64 bits */ 562 uint64_t addresslo : 32; /* and lower 64-bits */ 563 uint64_t mask : 8; 564 uint64_t dest : 5; 565 uint64_t source : 5; 566 uint64_t type : 6; 567 uint64_t timestamp : 8; 568#else 569 uint64_t timestamp : 8; 570 uint64_t type : 6; 571 uint64_t source : 5; 572 uint64_t dest : 5; 573 uint64_t mask : 8; 574 uint64_t addresslo : 32; 575 uint64_t addresshi : 3; 576 uint64_t discontinuity:1; 577 uint64_t valid : 1; 578 uint64_t reserved1 : 59; 579#endif 580 } iob2; /**< for IOBDMA */ 581} cvmx_tra_data_t; 582 583 584/** 585 * Setup the TRA buffer for use 586 * 587 * @param control TRA control setup 588 * @param filter Which events to log 589 * @param source_filter 590 * Source match 591 * @param dest_filter 592 * Destination match 593 * @param address Address compare 594 * @param address_mask 595 * Address mask 596 */ 597extern void cvmx_tra_setup(cvmx_tra_ctl_t control, cvmx_tra_filt_t filter, 598 cvmx_tra_sid_t source_filter, cvmx_tra_did_t dest_filter, 599 uint64_t address, uint64_t address_mask); 600 601/** 602 * Setup a TRA trigger. How the triggers are used should be 603 * setup using cvmx_tra_setup. 604 * 605 * @param trigger Trigger to setup (0 or 1) 606 * @param filter Which types of events to trigger on 607 * @param source_filter 608 * Source trigger match 609 * @param dest_filter 610 * Destination trigger match 611 * @param address Trigger address compare 612 * @param address_mask 613 * Trigger address mask 614 */ 615extern void cvmx_tra_trig_setup(uint64_t trigger, cvmx_tra_filt_t filter, 616 cvmx_tra_sid_t source_filter, cvmx_tra_did_t dest_filter, 617 uint64_t address, uint64_t address_mask); 618 619/** 620 * Read an entry from the TRA buffer. The trace buffer format is 621 * different in Octeon2, need to read twice from TRA_READ_DAT. 622 * 623 * @return Value return. High bit will be zero if there wasn't any data 624 */ 625extern cvmx_tra_data_t cvmx_tra_read(void); 626 627/** 628 * Decode a TRA entry into human readable output 629 * 630 * @param tra_ctl Trace control setup 631 * @param data Data to decode 632 */ 633extern void cvmx_tra_decode_text(cvmx_tra_ctl_t tra_ctl, cvmx_tra_data_t data); 634 635/** 636 * Display the entire trace buffer. It is advised that you 637 * disable the trace buffer before calling this routine 638 * otherwise it could infinitely loop displaying trace data 639 * that it created. 640 */ 641extern void cvmx_tra_display(void); 642 643/** 644 * Enable or disable the TRA hardware 645 * 646 * @param enable 1=enable, 0=disable 647 */ 648static inline void cvmx_tra_enable(int enable) 649{ 650 cvmx_tra_ctl_t control; 651 control.u64 = cvmx_read_csr(CVMX_TRA_CTL); 652 control.s.ena = enable; 653 cvmx_write_csr(CVMX_TRA_CTL, control.u64); 654 cvmx_read_csr(CVMX_TRA_CTL); 655} 656 657#ifdef __cplusplus 658} 659#endif 660 661#endif 662 663