/freebsd-9.3-release/sys/arm/at91/ |
H A D | at91_pit.c | 60 RD4(struct pit_softc *sc, bus_size_t off) function 165 if (RD4(sc, PIT_SR) & PIT_PITS_DONE) { 166 icnt = RD4(sc, PIT_PIVR) >> 20; 169 timecount += PIT_PIV(RD4(sc, PIT_MR)) * icnt; 182 piir = RD4(sc, PIT_PIIR); /* Current count | over flows */ 184 return (timecount + PIT_PIV(piir) + PIT_PIV(RD4(sc, PIT_MR)) * icnt); 194 last = PIT_PIV(RD4(sc, PIT_PIIR)); 202 piv = PIT_PIV(RD4(sc, PIT_PIIR));
|
H A D | if_ate.c | 158 RD4(struct ate_softc *sc, bus_size_t off) function 279 (RD4(sc, ETH_CFG) & ETH_CFG_RMII) == ETH_CFG_RMII; 282 (RD4(sc, ETHB_UIO) & ETHB_UIO_RMII) == ETHB_UIO_RMII; 613 WR4(sc, ETHB_UIO, RD4(sc, ETHB_UIO) | ETHB_UIO_CLKE); 679 WR4(sc, ETHB_UIO, RD4(sc, ETHB_UIO) & ~ETHB_UIO_CLKE); 724 reg = RD4(sc, ETH_CFG); 768 sc->mibdata.dot3StatsAlignmentErrors += RD4(sc, ETH_ALE); 769 sc->mibdata.dot3StatsFCSErrors += RD4(sc, ETH_SEQE); 770 c = RD4(sc, ETH_SCOL); 773 c = RD4(s [all...] |
H A D | at91_rst.c | 57 RD4(struct rst_softc *sc, bus_size_t off) function 118 switch (RD4(sc, RST_SR) & RST_SR_RST_MASK) { 154 } else if ((RD4(sc, RST_SR) & RST_SR_NRSTL)) { 169 if (RD4(sc, RST_SR) & RST_SR_URSTS) {
|
H A D | at91_st.c | 57 #define RD4(off) \ macro 69 cur1 = RD4(ST_CRTR); 70 cur2 = RD4(ST_CRTR); 179 if (RD4(ST_SR) & ST_SR_PITS) {
|
H A D | at91_wdt.c | 60 RD4(struct wdt_softc *sc, bus_size_t off) function 79 if (RD4(sc, WDT_SR) & (WDT_WDUNF | WDT_WDERR)) { 164 wdt_mr = RD4(sc, WDT_MR); 182 wdt_mr = RD4(sc, WDT_MR);
|
H A D | at91_pmc.c | 163 RD4(struct at91_pmc_softc *sc, bus_size_t off) function 190 ((value ^ RD4(sc, CKGR_PLLBR)) & 0x03f0ff) != 0) { 192 while ((RD4(sc, PMC_SR) & PMC_IER_LOCKB) != on) 197 while ((RD4(sc, PMC_SR) & PMC_IER_LOCKB) != on) 208 while ((RD4(sc, PMC_SCSR) & clk->pmc_mask) != clk->pmc_mask) 211 while ((RD4(sc, PMC_SCSR) & clk->pmc_mask) == clk->pmc_mask) 222 while ((RD4(sc, PMC_PCSR) & clk->pmc_mask) != clk->pmc_mask) 225 while ((RD4(sc, PMC_PCSR) & clk->pmc_mask) == clk->pmc_mask) 414 mckr = RD4(sc, PMC_MCKR); 418 at91_pmc_pll_rate(&plla, RD4(s [all...] |
H A D | at91_pio.c | 59 RD4(struct at91_pio_softc *sc, bus_size_t off) function 147 RD4(sc, PIO_ABSR), RD4(sc, PIO_OSR), RD4(sc, PIO_PSR), 148 RD4(sc, PIO_ODSR)); 232 status = RD4(sc, PIO_SR);
|
H A D | at91_twi.c | 68 RD4(struct at91_twi_softc *sc, bus_size_t off) function 217 status = RD4(sc, TWI_SR); 242 while (!((sr = RD4(sc, TWI_SR)) & bit) && counter-- > 0 && 348 sr = RD4(sc, TWI_SR); 350 if ((sr = RD4(sc, TWI_SR)) & TWI_SR_RXRDY) { 352 *buf++ = RD4(sc, TWI_RHR) & 0xff;
|
H A D | at91_rtc.c | 57 RD4(struct at91_rtc_softc *sc, bus_size_t off) function 185 status = RD4(sc, RTC_SR); 207 timr = RD4(sc, RTC_TIMR); 208 calr = RD4(sc, RTC_CALR);
|
H A D | uart_dev_at91usart.c | 74 #define RD4(bas, reg) \ macro 253 while (!(RD4(bas, USART_CSR) & USART_CSR_TXRDY)) 265 return ((RD4(bas, USART_CSR) & USART_CSR_RXRDY) != 0 ? 1 : 0); 277 while (!(RD4(bas, USART_CSR) & USART_CSR_RXRDY)) { 282 c = RD4(bas, USART_RHR) & 0xff; 350 if (RD4(&sc->sc_bas, USART_IMR) & USART_CSR_TIMEOUT) 547 csr = RD4(&sc->sc_bas, USART_CSR); 624 len = sc->sc_rxfifosz - RD4(&sc->sc_bas, PDC_RCR); 640 at91_rx_put(sc, RD4(&sc->sc_bas, USART_RHR) & 0xff); 665 csr = RD4( [all...] |
H A D | at91_spi.c | 67 RD4(struct at91_spi_softc *sc, bus_size_t off) function 166 RD4(sc, SPI_RDR); 167 RD4(sc, SPI_SR); 306 WR4(sc, SPI_MR, (RD4(sc, SPI_MR) & ~0x000f0000) | CS_TO_MR(cmd->cs)); 385 sr = RD4(sc, SPI_SR) & RD4(sc, SPI_IMR);
|
H A D | at91_mci.c | 96 RD4(struct at91_mci_softc *sc, bus_size_t off) function 366 WR4(sc, MCI_SDCR, RD4(sc, MCI_SDCR) | MCI_SDCR_SDCBUS); 368 WR4(sc, MCI_SDCR, RD4(sc, MCI_SDCR) & ~MCI_SDCR_SDCBUS); 369 WR4(sc, MCI_MR, (RD4(sc, MCI_MR) & ~MCI_MR_CLKDIV) | clkdiv); 426 mr = RD4(sc, MCI_MR) & ~MCI_MR_BLKLEN; 619 sr = RD4(sc, MCI_SR) & RD4(sc, MCI_IMR); 685 cmd->resp[i] = RD4(sc, MCI_RSPR + i * 4);
|
H A D | at91_ssc.c | 55 RD4(struct at91_ssc_softc *sc, bus_size_t off) function
|
/freebsd-9.3-release/sys/dev/sdhci/ |
H A D | sdhci.c | 200 RD4(struct sdhci_slot *slot, bus_size_t off) function 268 RD4(slot, SDHCI_DMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION)); 272 RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE)); 274 RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL)); 280 RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS)); 282 RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE)); 286 RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_MAX_CURRENT)); 299 if (!(RD4(slo [all...] |
/freebsd-9.3-release/sys/arm/xscale/ixp425/ |
H A D | ixp425_wdog.c | 55 RD4(struct ixpwdog_softc *sc, bus_size_t off) function
|
H A D | if_npe.c | 199 RD4(struct npe_softc *sc, bus_size_t off) function 978 eaddr[0] = RD4(sc, NPE_MAC_UNI_ADDR_1) & 0xff; 979 eaddr[1] = RD4(sc, NPE_MAC_UNI_ADDR_2) & 0xff; 980 eaddr[2] = RD4(sc, NPE_MAC_UNI_ADDR_3) & 0xff; 981 eaddr[3] = RD4(sc, NPE_MAC_UNI_ADDR_4) & 0xff; 982 eaddr[4] = RD4(sc, NPE_MAC_UNI_ADDR_5) & 0xff; 983 eaddr[5] = RD4(sc, NPE_MAC_UNI_ADDR_6) & 0xff; 1229 RD4(sc, NPE_MAC_RX_CNTRL1) &~ NPE_RX_CNTRL1_RX_EN); 1231 RD4(sc, NPE_MAC_TX_CNTRL1) &~ NPE_TX_CNTRL1_TX_EN); 1272 RD4(s [all...] |
/freebsd-9.3-release/sys/dev/mwl/ |
H A D | mwlhal.c | 215 RD4(struct mwl_hal_priv *mh, bus_size_t off) function 494 cause = RD4(mh, MACREG_REG_A2H_INTERRUPT_CAUSE); 502 RD4(mh, MACREG_REG_INT_CODE); /* XXX flush write? */ 517 RD4(mh, MACREG_REG_INT_CODE); 521 RD4(mh, MACREG_REG_INT_CODE); 538 dummy = RD4(mh, MACREG_REG_INT_CODE); 680 mh->mh_RTSSuccesses += RD4(mh, 0xa834); 681 mh->mh_RTSFailures += RD4(mh, 0xa830); 682 mh->mh_RxDuplicateFrames += RD4(mh, 0xa84c); 683 mh->mh_FCSErrorCount += RD4(m [all...] |
H A D | if_mwl.c | 285 RD4(struct mwl_softc *sc, bus_size_t off) function 2722 __func__, npending, RD4(sc, sc->sc_hwspecs.rxDescRead), 2723 RD4(sc, sc->sc_hwspecs.rxDescWrite));
|