Searched refs:FSUB (Results 1 - 25 of 26) sorted by relevance

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/freebsd-9.3-release/bin/pax/
H A Doptions.c98 FSUB fsub[] = {
191 FSUB tmp;
368 if ((frmt = (FSUB *)bsearch((void *)&tmp, (void *)fsub,
369 sizeof(fsub)/sizeof(FSUB), sizeof(FSUB), c_frmt)) != NULL) {
375 for (i = 0; i < (sizeof(fsub)/sizeof(FSUB)); ++i)
1018 FSUB tmp;
1184 if ((frmt = (FSUB *)bsearch((void *)&tmp, (void *)fsub,
1185 sizeof(fsub)/sizeof(FSUB), sizeof(FSUB), c_frm
[all...]
H A Dpax.h72 typedef struct fsub FSUB; typedef in typeref:struct:fsub
H A Dextern.h183 extern FSUB fsub[];
206 extern FSUB *frmt;
H A Dpax.c74 FSUB *frmt = NULL; /* archive format type */
H A Dar_subs.c568 FSUB *orgfrmt;
/freebsd-9.3-release/contrib/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h222 FADD, FSUB, FMUL, FMA, FDIV, FREM, enumerator in enum:llvm::ISD::NodeType
/freebsd-9.3-release/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp59 // Implements expansion for FNEG; falls back to UnrollVectorOp if FSUB
201 case ISD::FSUB:
743 if (TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) {
745 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
H A DSelectionDAGBuilder.cpp2739 visitBinary(I, ISD::FSUB);
3835 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3951 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3968 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3974 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3993 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3999 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4005 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
4045 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4062 SDValue t3 = DAG.getNode(ISD::FSUB, d
[all...]
H A DSelectionDAGDumper.cpp175 case ISD::FSUB: return "fsub";
H A DLegalizeFloatTypes.cpp94 case ISD::FSUB: R = SoftenFloatRes_FSUB(N); break;
836 case ISD::FSUB: ExpandFloatRes_FSUB(N, Lo, Hi); break;
1413 DAG.getNode(ISD::FSUB, dl,
H A DDAGCombiner.cpp452 !TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType()))
462 case ISD::FSUB:
515 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
520 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
524 case ISD::FSUB:
534 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
1168 case ISD::FSUB: return visitFSUB(N);
5998 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) &&
6000 return DAG.getNode(ISD::FSUB, SDLoc(N), VT, N0,
6003 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, V
[all...]
H A DLegalizeVectorTypes.cpp106 case ISD::FSUB:
567 case ISD::FSUB:
1489 case ISD::FSUB:
H A DLegalizeDAG.cpp2298 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
2336 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt,
3003 DAG.getNode(ISD::FSUB, dl, VT,
3208 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
3356 case ISD::FSUB: {
H A DSelectionDAG.cpp2732 if (getTarget().Options.UnsafeFPMath && OpOpcode == ISD::FSUB)
2733 return getNode(ISD::FSUB, DL, VT, Operand.getNode()->getOperand(1),
2943 case ISD::FSUB:
2957 } else if (Opcode == ISD::FSUB) {
3205 case ISD::FSUB:
3252 case ISD::FSUB:
3291 case ISD::FSUB:
H A DFastISel.cpp989 return SelectBinaryOp(I, ISD::FSUB);
/freebsd-9.3-release/contrib/llvm/lib/Target/R600/
H A DAMDGPUISelLowering.cpp191 setOperationAction(ISD::FSUB, VT, Expand);
419 SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT,
H A DAMDILISelLowering.cpp173 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
H A DR600ISelLowering.cpp69 setOperationAction(ISD::FSUB, MVT::f32, Expand);
/freebsd-9.3-release/contrib/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp4759 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
4769 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
4775 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
4781 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
4787 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
6786 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPOne, NewEst);
6849 HalfArg = DAG.getNode(ISD::FSUB, dl, VT, HalfArg, Op);
6860 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPThreeHalves, NewEst);
/freebsd-9.3-release/contrib/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp233 setOperationAction(ISD::FSUB, Ty, Legal);
1749 return DAG.getNode(ISD::FSUB, SDLoc(Op), ResTy, Op->getOperand(1),
1761 return DAG.getNode(ISD::FSUB, DL, Op->getValueType(0), Op->getOperand(1),
/freebsd-9.3-release/contrib/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1595 setOperationAction(ISD::FSUB, MVT::f128, Legal);
1620 setOperationAction(ISD::FSUB, MVT::f128, Custom);
2821 case ISD::FSUB: return LowerF128Op(Op, DAG,
/freebsd-9.3-release/contrib/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1257 case FSub: return ISD::FSUB;
/freebsd-9.3-release/contrib/llvm/lib/Target/ARM/
H A DARMFastISel.cpp1890 case ISD::FSUB:
2921 return SelectBinaryFPOp(I, ISD::FSUB);
/freebsd-9.3-release/contrib/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp802 setOperationAction(ISD::FSUB, VT, Expand);
915 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
950 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
1129 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1142 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1320 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1327 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1515 setTargetDAGCombine(ISD::FSUB);
8619 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
8670 SDValue Sub = DAG.getNode(ISD::FSUB, d
[all...]
/freebsd-9.3-release/contrib/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp241 setOperationAction(ISD::FSUB, MVT::f128, Custom);
2867 case ISD::FSUB: return LowerF128ToCall(Op, DAG, RTLIB::SUB_F128);

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