Searched refs:CVMX_CIU_INTX_EN1 (Results 1 - 5 of 5) sorted by relevance

/freebsd-9.3-release/sys/contrib/octeon-sdk/
H A Dcvmx-interrupt.h247 uint64_t mask = cvmx_read_csr(CVMX_CIU_INTX_EN1(ciu_offset));
249 cvmx_write_csr(CVMX_CIU_INTX_EN1(ciu_offset), mask);
282 uint64_t mask = cvmx_read_csr(CVMX_CIU_INTX_EN1(ciu_offset));
284 cvmx_write_csr(CVMX_CIU_INTX_EN1(ciu_offset), mask);
H A Dcvmx-interrupt.c331 irq_mask = cvmx_read_csr(CVMX_CIU_INT_SUM1) & cvmx_read_csr(CVMX_CIU_INTX_EN1(ciu_offset));
460 cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num()*2), 0);
461 cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num()*2+1), 0);
H A Dcvmx-ciu-defs.h128 static inline uint64_t CVMX_CIU_INTX_EN1(unsigned long offset) function
139 cvmx_warn("CVMX_CIU_INTX_EN1(%lu) is invalid on this chip\n", offset);
143 #define CVMX_CIU_INTX_EN1(offset) (CVMX_ADD_IO_SEG(0x0001070000000208ull) + ((offset) & 63) * 16) macro
/freebsd-9.3-release/sys/mips/cavium/
H A Dciu.c373 mask = cvmx_read_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num()*2));
375 cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num()*2), mask);
385 mask = cvmx_read_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num()*2));
387 cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num()*2), mask);
400 mask = cvmx_read_csr(CVMX_CIU_INTX_EN1(core*2));
405 cvmx_write_csr(CVMX_CIU_INTX_EN1(core*2), mask);
428 en1_mask = cvmx_read_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num()*2));
H A Docteon_machdep.c254 cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num()*2), 0);
255 cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num()*2+1), 0);

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