1194140Simp/*- 2194140Simp * Copyright (c) 2006 Wojciech A. Koszek <wkoszek@FreeBSD.org> 3194140Simp * All rights reserved. 4194140Simp * 5194140Simp * Redistribution and use in source and binary forms, with or without 6194140Simp * modification, are permitted provided that the following conditions 7194140Simp * are met: 8194140Simp * 1. Redistributions of source code must retain the above copyright 9194140Simp * notice, this list of conditions and the following disclaimer. 10194140Simp * 2. Redistributions in binary form must reproduce the above copyright 11194140Simp * notice, this list of conditions and the following disclaimer in the 12194140Simp * documentation and/or other materials provided with the distribution. 13194140Simp * 14194140Simp * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15194140Simp * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16194140Simp * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17194140Simp * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18194140Simp * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19194140Simp * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20194140Simp * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21194140Simp * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22194140Simp * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23194140Simp * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24194140Simp * SUCH DAMAGE. 25194140Simp * 26194140Simp * $FreeBSD$ 27194140Simp */ 28194140Simp#include <sys/cdefs.h> 29194140Simp__FBSDID("$FreeBSD$"); 30194140Simp 31194140Simp#include <sys/param.h> 32196262Simp#include <sys/conf.h> 33196262Simp#include <sys/kernel.h> 34194140Simp#include <sys/systm.h> 35196262Simp#include <sys/imgact.h> 36196262Simp#include <sys/bio.h> 37196262Simp#include <sys/buf.h> 38196262Simp#include <sys/bus.h> 39196262Simp#include <sys/cpu.h> 40196262Simp#include <sys/cons.h> 41196262Simp#include <sys/exec.h> 42196262Simp#include <sys/ucontext.h> 43196262Simp#include <sys/proc.h> 44196262Simp#include <sys/kdb.h> 45196262Simp#include <sys/ptrace.h> 46196262Simp#include <sys/reboot.h> 47196262Simp#include <sys/signalvar.h> 48196262Simp#include <sys/sysent.h> 49196262Simp#include <sys/sysproto.h> 50210311Sjmallett#include <sys/time.h> 51210311Sjmallett#include <sys/timetc.h> 52196262Simp#include <sys/user.h> 53196262Simp 54196262Simp#include <vm/vm.h> 55196262Simp#include <vm/vm_object.h> 56196262Simp#include <vm/vm_page.h> 57196262Simp#include <vm/vm_pager.h> 58196262Simp 59196262Simp#include <machine/atomic.h> 60196262Simp#include <machine/cache.h> 61196262Simp#include <machine/clock.h> 62196262Simp#include <machine/cpu.h> 63194140Simp#include <machine/cpuregs.h> 64194140Simp#include <machine/cpufunc.h> 65202063Simp#include <mips/cavium/octeon_pcmap_regs.h> 66196262Simp#include <machine/hwfunc.h> 67196262Simp#include <machine/intr_machdep.h> 68196262Simp#include <machine/locore.h> 69196262Simp#include <machine/md_var.h> 70194140Simp#include <machine/pcpu.h> 71196262Simp#include <machine/pte.h> 72196262Simp#include <machine/trap.h> 73196262Simp#include <machine/vmparam.h> 74194140Simp 75210311Sjmallett#include <contrib/octeon-sdk/cvmx.h> 76210311Sjmallett#include <contrib/octeon-sdk/cvmx-bootmem.h> 77210311Sjmallett#include <contrib/octeon-sdk/cvmx-interrupt.h> 78210311Sjmallett#include <contrib/octeon-sdk/cvmx-version.h> 79210311Sjmallett 80194140Simp#if defined(__mips_n64) 81196262Simp#define MAX_APP_DESC_ADDR 0xffffffffafffffff 82194140Simp#else 83196262Simp#define MAX_APP_DESC_ADDR 0xafffffff 84194140Simp#endif 85194140Simp 86210311Sjmallett#define OCTEON_CLOCK_DEFAULT (500 * 1000 * 1000) 87210311Sjmallett 88210311Sjmallettstruct octeon_feature_description { 89210311Sjmallett octeon_feature_t ofd_feature; 90210311Sjmallett const char *ofd_string; 91210311Sjmallett}; 92210311Sjmallett 93196262Simpextern int *edata; 94196262Simpextern int *end; 95217518Simpextern char cpu_model[]; 96217518Simpextern char cpu_board[]; 97194140Simp 98210311Sjmallettstatic const struct octeon_feature_description octeon_feature_descriptions[] = { 99210311Sjmallett { OCTEON_FEATURE_SAAD, "SAAD" }, 100210311Sjmallett { OCTEON_FEATURE_ZIP, "ZIP" }, 101210311Sjmallett { OCTEON_FEATURE_CRYPTO, "CRYPTO" }, 102216069Sjmallett { OCTEON_FEATURE_DORM_CRYPTO, "DORM_CRYPTO" }, 103210311Sjmallett { OCTEON_FEATURE_PCIE, "PCIE" }, 104216069Sjmallett { OCTEON_FEATURE_SRIO, "SRIO" }, 105210311Sjmallett { OCTEON_FEATURE_KEY_MEMORY, "KEY_MEMORY" }, 106210311Sjmallett { OCTEON_FEATURE_LED_CONTROLLER, "LED_CONTROLLER" }, 107210311Sjmallett { OCTEON_FEATURE_TRA, "TRA" }, 108210311Sjmallett { OCTEON_FEATURE_MGMT_PORT, "MGMT_PORT" }, 109210311Sjmallett { OCTEON_FEATURE_RAID, "RAID" }, 110210311Sjmallett { OCTEON_FEATURE_USB, "USB" }, 111210311Sjmallett { OCTEON_FEATURE_NO_WPTR, "NO_WPTR" }, 112210311Sjmallett { OCTEON_FEATURE_DFA, "DFA" }, 113210311Sjmallett { OCTEON_FEATURE_MDIO_CLAUSE_45, "MDIO_CLAUSE_45" }, 114216069Sjmallett { OCTEON_FEATURE_NPEI, "NPEI" }, 115210311Sjmallett { 0, NULL } 116210311Sjmallett}; 117210311Sjmallett 118201530Simpuint64_t ciu_get_en_reg_addr_new(int corenum, int intx, int enx, int ciu_ip); 119201530Simpvoid ciu_dump_interrutps_enabled(int core_num, int intx, int enx, int ciu_ip); 120201530Simp 121210311Sjmallettstatic uint64_t octeon_get_ticks(void); 122210311Sjmallettstatic unsigned octeon_get_timecount(struct timecounter *tc); 123210311Sjmallett 124200344Simpstatic void octeon_boot_params_init(register_t ptr); 125200344Simp 126210311Sjmallettstatic struct timecounter octeon_timecounter = { 127210311Sjmallett octeon_get_timecount, /* get_timecount */ 128210311Sjmallett 0, /* no poll_pps */ 129210311Sjmallett 0xffffffffu, /* octeon_mask */ 130210311Sjmallett 0, /* frequency */ 131210311Sjmallett "Octeon", /* name */ 132210311Sjmallett 900, /* quality (adjusted in code) */ 133210311Sjmallett}; 134210311Sjmallett 135198669Srrsvoid 136198669Srrsplatform_cpu_init() 137198669Srrs{ 138198669Srrs /* Nothing special yet */ 139198669Srrs} 140196262Simp 141194140Simp/* 142194140Simp * Perform a board-level soft-reset. 143194140Simp */ 144196314Simpvoid 145196314Simpplatform_reset(void) 146194140Simp{ 147210311Sjmallett cvmx_write_csr(CVMX_CIU_SOFT_RST, 1); 148194140Simp} 149194140Simp 150201530Simpvoid 151201530Simpocteon_led_write_char(int char_position, char val) 152194140Simp{ 153201530Simp uint64_t ptr = (OCTEON_CHAR_LED_BASE_ADDR | 0xf8); 154194140Simp 155210311Sjmallett if (octeon_is_simulation()) 156201530Simp return; 157194140Simp 158201530Simp char_position &= 0x7; /* only 8 chars */ 159201530Simp ptr += char_position; 160201530Simp oct_write8_x8(ptr, val); 161194140Simp} 162194140Simp 163201530Simpvoid 164201530Simpocteon_led_write_char0(char val) 165194140Simp{ 166201530Simp uint64_t ptr = (OCTEON_CHAR_LED_BASE_ADDR | 0xf8); 167194140Simp 168210311Sjmallett if (octeon_is_simulation()) 169201530Simp return; 170201530Simp oct_write8_x8(ptr, val); 171194140Simp} 172194140Simp 173201530Simpvoid 174201530Simpocteon_led_write_hexchar(int char_position, char hexval) 175194140Simp{ 176201530Simp uint64_t ptr = (OCTEON_CHAR_LED_BASE_ADDR | 0xf8); 177201530Simp char char1, char2; 178194140Simp 179210311Sjmallett if (octeon_is_simulation()) 180201530Simp return; 181194140Simp 182201530Simp char1 = (hexval >> 4) & 0x0f; char1 = (char1 < 10)?char1+'0':char1+'7'; 183201530Simp char2 = (hexval & 0x0f); char2 = (char2 < 10)?char2+'0':char2+'7'; 184201530Simp char_position &= 0x7; /* only 8 chars */ 185201530Simp if (char_position > 6) 186201530Simp char_position = 6; 187201530Simp ptr += char_position; 188201530Simp oct_write8_x8(ptr, char1); 189201530Simp ptr++; 190201530Simp oct_write8_x8(ptr, char2); 191194140Simp} 192194140Simp 193201530Simpvoid 194201530Simpocteon_led_write_string(const char *str) 195194140Simp{ 196201530Simp uint64_t ptr = (OCTEON_CHAR_LED_BASE_ADDR | 0xf8); 197201530Simp int i; 198194140Simp 199210311Sjmallett if (octeon_is_simulation()) 200201530Simp return; 201194140Simp 202201530Simp for (i=0; i<8; i++, ptr++) { 203201530Simp if (str && *str) 204201530Simp oct_write8_x8(ptr, *str++); 205201530Simp else 206201530Simp oct_write8_x8(ptr, ' '); 207210311Sjmallett (void)cvmx_read_csr(CVMX_MIO_BOOT_BIST_STAT); 208201530Simp } 209194140Simp} 210194140Simp 211194140Simpstatic char progress[8] = { '-', '/', '|', '\\', '-', '/', '|', '\\'}; 212194140Simp 213201530Simpvoid 214201530Simpocteon_led_run_wheel(int *prog_count, int led_position) 215194140Simp{ 216210311Sjmallett if (octeon_is_simulation()) 217201530Simp return; 218201530Simp octeon_led_write_char(led_position, progress[*prog_count]); 219201530Simp *prog_count += 1; 220201530Simp *prog_count &= 0x7; 221194140Simp} 222194140Simp 223201530Simpvoid 224201530Simpocteon_led_write_hex(uint32_t wl) 225194140Simp{ 226201530Simp char nbuf[80]; 227194140Simp 228201530Simp sprintf(nbuf, "%X", wl); 229201530Simp octeon_led_write_string(nbuf); 230194140Simp} 231194140Simp 232194140Simp/* 233194140Simp * octeon_debug_symbol 234194140Simp * 235194140Simp * Does nothing. 236194140Simp * Used to mark the point for simulator to begin tracing 237194140Simp */ 238201530Simpvoid 239201530Simpocteon_debug_symbol(void) 240194140Simp{ 241194140Simp} 242194140Simp 243194140Simp/* 244194140Simp * octeon_ciu_reset 245194140Simp * 246194140Simp * Shutdown all CIU to IP2, IP3 mappings 247194140Simp */ 248201530Simpvoid 249201530Simpocteon_ciu_reset(void) 250194140Simp{ 251210311Sjmallett /* Disable all CIU interrupts by default */ 252210311Sjmallett cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2), 0); 253210311Sjmallett cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2+1), 0); 254210311Sjmallett cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num()*2), 0); 255210311Sjmallett cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num()*2+1), 0); 256194140Simp 257210311Sjmallett#ifdef SMP 258210311Sjmallett /* Enable the MBOX interrupts. */ 259210311Sjmallett cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2+1), 260210311Sjmallett (1ull << (CVMX_IRQ_MBOX0 - 8)) | 261210311Sjmallett (1ull << (CVMX_IRQ_MBOX1 - 8))); 262210311Sjmallett#endif 263194140Simp} 264194140Simp 265210311Sjmallettstatic void 266210311Sjmallettocteon_memory_init(void) 267194140Simp{ 268210311Sjmallett vm_paddr_t phys_end; 269210311Sjmallett int64_t addr; 270216318Sgonzo unsigned i, j; 271194140Simp 272210311Sjmallett phys_end = round_page(MIPS_KSEG0_TO_PHYS((vm_offset_t)&end)); 273194140Simp 274210311Sjmallett if (octeon_is_simulation()) { 275210311Sjmallett /* Simulator we limit to 96 meg */ 276210311Sjmallett phys_avail[0] = phys_end; 277210311Sjmallett phys_avail[1] = 96 << 20; 278194140Simp 279216318Sgonzo dump_avail[0] = phys_avail[0]; 280216320Sgonzo dump_avail[1] = phys_avail[1]; 281216318Sgonzo 282210311Sjmallett realmem = physmem = btoc(phys_avail[1] - phys_avail[0]); 283210311Sjmallett return; 284201530Simp } 285194140Simp 286210311Sjmallett /* 287210311Sjmallett * Allocate memory from bootmem 1MB at a time and merge 288210311Sjmallett * adjacent entries. 289210311Sjmallett */ 290210311Sjmallett i = 0; 291210311Sjmallett while (i < PHYS_AVAIL_ENTRIES) { 292216773Sjmallett /* 293216773Sjmallett * If there is less than 2MB of memory available in 128-byte 294216773Sjmallett * blocks, do not steal any more memory. We need to leave some 295216773Sjmallett * memory for the command queues to be allocated out of. 296216773Sjmallett */ 297216773Sjmallett if (cvmx_bootmem_available_mem(128) < 2 << 20) 298216773Sjmallett break; 299216773Sjmallett 300210311Sjmallett addr = cvmx_bootmem_phy_alloc(1 << 20, phys_end, 301210311Sjmallett ~(vm_paddr_t)0, PAGE_SIZE, 0); 302210311Sjmallett if (addr == -1) 303210311Sjmallett break; 304194140Simp 305212842Sjmallett /* 306212842Sjmallett * The SDK needs to be able to easily map any memory that might 307212842Sjmallett * come to it e.g. in the form of an mbuf. Because on !n64 we 308212842Sjmallett * can't direct-map some addresses and we don't want to manage 309212842Sjmallett * temporary mappings within the SDK, don't feed memory that 310212842Sjmallett * can't be direct-mapped to the kernel. 311212842Sjmallett */ 312212842Sjmallett#if !defined(__mips_n64) 313212842Sjmallett if (!MIPS_DIRECT_MAPPABLE(addr + (1 << 20) - 1)) 314212842Sjmallett continue; 315212842Sjmallett#endif 316212842Sjmallett 317210311Sjmallett physmem += btoc(1 << 20); 318194140Simp 319210311Sjmallett if (i > 0 && phys_avail[i - 1] == addr) { 320210311Sjmallett phys_avail[i - 1] += 1 << 20; 321210311Sjmallett continue; 322210311Sjmallett } 323194140Simp 324210311Sjmallett phys_avail[i + 0] = addr; 325210311Sjmallett phys_avail[i + 1] = addr + (1 << 20); 326194140Simp 327210311Sjmallett i += 2; 328201530Simp } 329194140Simp 330216320Sgonzo for (j = 0; j < i; j++) 331216318Sgonzo dump_avail[j] = phys_avail[j]; 332216318Sgonzo 333202831Simp realmem = physmem; 334202831Simp} 335202831Simp 336196262Simpvoid 337201530Simpplatform_start(__register_t a0, __register_t a1, __register_t a2 __unused, 338201530Simp __register_t a3) 339196262Simp{ 340210311Sjmallett const struct octeon_feature_description *ofd; 341196262Simp uint64_t platform_counter_freq; 342194140Simp 343210311Sjmallett /* 344210311Sjmallett * XXX 345210311Sjmallett * octeon_boot_params_init() should be called before anything else, 346210311Sjmallett * certainly before any output; we may find out from the boot 347210311Sjmallett * descriptor's flags that we're supposed to use the PCI or UART1 348210311Sjmallett * consoles rather than UART0. No point doing that reorganization 349210311Sjmallett * until we actually intercept UART_DEV_CONSOLE for the UART1 case 350210311Sjmallett * and somehow handle the PCI console, which we lack code for 351210311Sjmallett * entirely. 352210311Sjmallett */ 353210311Sjmallett 354201845Simp /* Initialize pcpu stuff */ 355201881Simp mips_pcpu0_init(); 356202831Simp mips_timer_early_init(OCTEON_CLOCK_DEFAULT); 357202831Simp cninit(); 358201845Simp 359202831Simp octeon_ciu_reset(); 360200344Simp octeon_boot_params_init(a3); 361210311Sjmallett /* 362210311Sjmallett * XXX 363210311Sjmallett * We can certainly parse command line arguments or U-Boot environment 364210311Sjmallett * to determine whether to bootverbose / single user / ... I think 365210311Sjmallett * stass has patches to add support for loader things to U-Boot even. 366210311Sjmallett */ 367196262Simp bootverbose = 1; 368194140Simp 369202831Simp /* 370202831Simp * For some reason on the cn38xx simulator ebase register is set to 371202831Simp * 0x80001000 at bootup time. Move it back to the default, but 372202831Simp * when we move to having support for multiple executives, we need 373202831Simp * to rethink this. 374202831Simp */ 375202831Simp mips_wr_ebase(0x80000000); 376196262Simp 377202831Simp octeon_memory_init(); 378196262Simp init_param1(); 379196262Simp init_param2(physmem); 380196262Simp mips_cpu_init(); 381202831Simp pmap_bootstrap(); 382202831Simp mips_proc0_init(); 383196262Simp mutex_init(); 384196262Simp kdb_init(); 385202850Simp#ifdef KDB 386202850Simp if (boothowto & RB_KDB) 387202850Simp kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger"); 388196262Simp#endif 389217518Simp cpu_clock = cvmx_sysinfo_get()->cpu_clock_hz; 390217518Simp platform_counter_freq = cpu_clock; 391217518Simp octeon_timecounter.tc_frequency = cpu_clock; 392210311Sjmallett platform_timecounter = &octeon_timecounter; 393206721Sjmallett mips_timer_init_params(platform_counter_freq, 0); 394217518Simp set_cputicker(octeon_get_ticks, cpu_clock, 0); 395206721Sjmallett 396206721Sjmallett#ifdef SMP 397206721Sjmallett /* 398210311Sjmallett * Clear any pending IPIs. 399206721Sjmallett */ 400210311Sjmallett cvmx_write_csr(CVMX_CIU_MBOX_CLRX(0), 0xffffffff); 401206721Sjmallett#endif 402210311Sjmallett 403210311Sjmallett printf("Octeon SDK: %s\n", OCTEON_SDK_VERSION_STRING); 404210311Sjmallett printf("Available Octeon features:"); 405210311Sjmallett for (ofd = octeon_feature_descriptions; ofd->ofd_string != NULL; ofd++) 406210311Sjmallett if (octeon_has_feature(ofd->ofd_feature)) 407210311Sjmallett printf(" %s", ofd->ofd_string); 408210311Sjmallett printf("\n"); 409196262Simp} 410196262Simp 411210311Sjmallettstatic uint64_t 412210311Sjmallettocteon_get_ticks(void) 413210311Sjmallett{ 414210311Sjmallett uint64_t cvmcount; 415210311Sjmallett 416210311Sjmallett CVMX_MF_CYCLE(cvmcount); 417210311Sjmallett return (cvmcount); 418210311Sjmallett} 419210311Sjmallett 420210311Sjmallettstatic unsigned 421210311Sjmallettocteon_get_timecount(struct timecounter *tc) 422210311Sjmallett{ 423210311Sjmallett return ((unsigned)octeon_get_ticks()); 424210311Sjmallett} 425210311Sjmallett 426215990Sjmallett/** 427215990Sjmallett * version of printf that works better in exception context. 428215990Sjmallett * 429215990Sjmallett * @param format 430215990Sjmallett * 431215990Sjmallett * XXX If this function weren't in cvmx-interrupt.c, we'd use the SDK version. 432215990Sjmallett */ 433215990Sjmallettvoid cvmx_safe_printf(const char *format, ...) 434215990Sjmallett{ 435215990Sjmallett char buffer[256]; 436215990Sjmallett char *ptr = buffer; 437215990Sjmallett int count; 438215990Sjmallett va_list args; 439215990Sjmallett 440215990Sjmallett va_start(args, format); 441215990Sjmallett#ifndef __U_BOOT__ 442215990Sjmallett count = vsnprintf(buffer, sizeof(buffer), format, args); 443215990Sjmallett#else 444215990Sjmallett count = vsprintf(buffer, format, args); 445215990Sjmallett#endif 446215990Sjmallett va_end(args); 447215990Sjmallett 448215990Sjmallett while (count-- > 0) 449215990Sjmallett { 450215990Sjmallett cvmx_uart_lsr_t lsrval; 451215990Sjmallett 452215990Sjmallett /* Spin until there is room */ 453215990Sjmallett do 454215990Sjmallett { 455215990Sjmallett lsrval.u64 = cvmx_read_csr(CVMX_MIO_UARTX_LSR(0)); 456215990Sjmallett#if !defined(CONFIG_OCTEON_SIM_SPEED) 457215990Sjmallett if (lsrval.s.temt == 0) 458215990Sjmallett cvmx_wait(10000); /* Just to reduce the load on the system */ 459215990Sjmallett#endif 460215990Sjmallett } 461215990Sjmallett while (lsrval.s.temt == 0); 462215990Sjmallett 463215990Sjmallett if (*ptr == '\n') 464215990Sjmallett cvmx_write_csr(CVMX_MIO_UARTX_THR(0), '\r'); 465215990Sjmallett cvmx_write_csr(CVMX_MIO_UARTX_THR(0), *ptr++); 466215990Sjmallett } 467215990Sjmallett} 468215990Sjmallett 469202831Simp/* impSTART: This stuff should move back into the Cavium SDK */ 470194140Simp/* 471194140Simp **************************************************************************************** 472194140Simp * 473194140Simp * APP/BOOT DESCRIPTOR STUFF 474194140Simp * 475194140Simp **************************************************************************************** 476194140Simp */ 477194140Simp 478194140Simp/* Define the struct that is initialized by the bootloader used by the 479194140Simp * startup code. 480194140Simp * 481194140Simp * Copyright (c) 2004, 2005, 2006 Cavium Networks. 482194140Simp * 483194140Simp * The authors hereby grant permission to use, copy, modify, distribute, 484194140Simp * and license this software and its documentation for any purpose, provided 485194140Simp * that existing copyright notices are retained in all copies and that this 486194140Simp * notice is included verbatim in any distributions. No written agreement, 487194140Simp * license, or royalty fee is required for any of the authorized uses. 488194140Simp * Modifications to this software may be copyrighted by their authors 489194140Simp * and need not follow the licensing terms described here, provided that 490194140Simp * the new terms are clearly indicated on the first page of each file where 491194140Simp * they apply. 492194140Simp */ 493194140Simp 494194140Simp#define OCTEON_CURRENT_DESC_VERSION 6 495194140Simp#define OCTEON_ARGV_MAX_ARGS (64) 496194140Simp#define OCTOEN_SERIAL_LEN 20 497194140Simp 498194140Simptypedef struct { 499200344Simp /* Start of block referenced by assembly code - do not change! */ 500200344Simp uint32_t desc_version; 501200344Simp uint32_t desc_size; 502194140Simp 503200344Simp uint64_t stack_top; 504200344Simp uint64_t heap_base; 505200344Simp uint64_t heap_end; 506200344Simp uint64_t entry_point; /* Only used by bootloader */ 507200344Simp uint64_t desc_vaddr; 508200344Simp /* End of This block referenced by assembly code - do not change! */ 509194140Simp 510200344Simp uint32_t exception_base_addr; 511200344Simp uint32_t stack_size; 512200344Simp uint32_t heap_size; 513200344Simp uint32_t argc; /* Argc count for application */ 514200344Simp uint32_t argv[OCTEON_ARGV_MAX_ARGS]; 515200344Simp uint32_t flags; 516200344Simp uint32_t core_mask; 517200344Simp uint32_t dram_size; /**< DRAM size in megabyes */ 518200344Simp uint32_t phy_mem_desc_addr; /**< physical address of free memory descriptor block*/ 519200344Simp uint32_t debugger_flags_base_addr; /**< used to pass flags from app to debugger */ 520200344Simp uint32_t eclock_hz; /**< CPU clock speed, in hz */ 521200344Simp uint32_t dclock_hz; /**< DRAM clock speed, in hz */ 522200344Simp uint32_t spi_clock_hz; /**< SPI4 clock in hz */ 523200344Simp uint16_t board_type; 524200344Simp uint8_t board_rev_major; 525200344Simp uint8_t board_rev_minor; 526200344Simp uint16_t chip_type; 527200344Simp uint8_t chip_rev_major; 528200344Simp uint8_t chip_rev_minor; 529200344Simp char board_serial_number[OCTOEN_SERIAL_LEN]; 530200344Simp uint8_t mac_addr_base[6]; 531200344Simp uint8_t mac_addr_count; 532200344Simp uint64_t cvmx_desc_vaddr; 533194140Simp} octeon_boot_descriptor_t; 534194140Simp 535210311Sjmallettcvmx_bootinfo_t *octeon_bootinfo; 536194140Simp 537194140Simpstatic octeon_boot_descriptor_t *app_desc_ptr; 538194140Simp 539200344Simpint 540210311Sjmallettocteon_is_simulation(void) 541194140Simp{ 542210311Sjmallett switch (cvmx_sysinfo_get()->board_type) { 543210311Sjmallett case CVMX_BOARD_TYPE_SIM: 544204777Sjmallett return 1; 545204777Sjmallett default: 546210311Sjmallett return 0; 547204777Sjmallett } 548194140Simp} 549194140Simp 550200344Simpstatic void 551210311Sjmallettocteon_process_app_desc_ver_6(void) 552194140Simp{ 553200344Simp /* XXX Why is 0x00000000ffffffffULL a bad value? */ 554200344Simp if (app_desc_ptr->cvmx_desc_vaddr == 0 || 555210311Sjmallett app_desc_ptr->cvmx_desc_vaddr == 0xfffffffful) 556210311Sjmallett panic("Bad octeon_bootinfo %p", octeon_bootinfo); 557210311Sjmallett 558210311Sjmallett octeon_bootinfo = 559200344Simp (cvmx_bootinfo_t *)(intptr_t)app_desc_ptr->cvmx_desc_vaddr; 560210311Sjmallett octeon_bootinfo = 561210311Sjmallett (cvmx_bootinfo_t *) ((intptr_t)octeon_bootinfo | MIPS_KSEG0_START); 562210311Sjmallett if (octeon_bootinfo->major_version != 1) 563210311Sjmallett panic("Incompatible CVMX descriptor from bootloader: %d.%d %p", 564210311Sjmallett (int) octeon_bootinfo->major_version, 565210311Sjmallett (int) octeon_bootinfo->minor_version, octeon_bootinfo); 566194140Simp 567215990Sjmallett cvmx_sysinfo_minimal_initialize(octeon_bootinfo->phy_mem_desc_addr, 568210311Sjmallett octeon_bootinfo->board_type, 569210311Sjmallett octeon_bootinfo->board_rev_major, 570210311Sjmallett octeon_bootinfo->board_rev_minor, 571210311Sjmallett octeon_bootinfo->eclock_hz); 572194140Simp} 573194140Simp 574200344Simpstatic void 575200344Simpocteon_boot_params_init(register_t ptr) 576194140Simp{ 577210311Sjmallett if (ptr == 0 || ptr >= MAX_APP_DESC_ADDR) 578210311Sjmallett panic("app descriptor passed at invalid address %#jx", 579210311Sjmallett (uintmax_t)ptr); 580194140Simp 581210311Sjmallett app_desc_ptr = (octeon_boot_descriptor_t *)(intptr_t)ptr; 582210311Sjmallett if (app_desc_ptr->desc_version < 6) 583210311Sjmallett panic("Your boot code is too old to be supported."); 584210311Sjmallett octeon_process_app_desc_ver_6(); 585210311Sjmallett 586210311Sjmallett KASSERT(octeon_bootinfo != NULL, ("octeon_bootinfo should be set")); 587210311Sjmallett 588215990Sjmallett if (cvmx_sysinfo_get()->phy_mem_desc_addr == (uint64_t)0) 589210311Sjmallett panic("Your boot loader did not supply a memory descriptor."); 590215990Sjmallett cvmx_bootmem_init(cvmx_sysinfo_get()->phy_mem_desc_addr); 591210311Sjmallett 592194140Simp printf("Boot Descriptor Ver: %u -> %u/%u", 593210311Sjmallett app_desc_ptr->desc_version, octeon_bootinfo->major_version, 594210311Sjmallett octeon_bootinfo->minor_version); 595210311Sjmallett printf(" CPU clock: %uMHz Core Mask: %#x\n", 596210311Sjmallett cvmx_sysinfo_get()->cpu_clock_hz / 1000000, 597210311Sjmallett cvmx_sysinfo_get()->core_mask); 598194140Simp printf(" Board Type: %u Revision: %u/%u\n", 599210311Sjmallett cvmx_sysinfo_get()->board_type, 600210311Sjmallett cvmx_sysinfo_get()->board_rev_major, 601210311Sjmallett cvmx_sysinfo_get()->board_rev_minor); 602194140Simp 603202831Simp printf(" Mac Address %02X.%02X.%02X.%02X.%02X.%02X (%d)\n", 604210311Sjmallett octeon_bootinfo->mac_addr_base[0], 605210311Sjmallett octeon_bootinfo->mac_addr_base[1], 606210311Sjmallett octeon_bootinfo->mac_addr_base[2], 607210311Sjmallett octeon_bootinfo->mac_addr_base[3], 608210311Sjmallett octeon_bootinfo->mac_addr_base[4], 609210311Sjmallett octeon_bootinfo->mac_addr_base[5], 610210311Sjmallett octeon_bootinfo->mac_addr_count); 611210311Sjmallett 612210311Sjmallett#if defined(OCTEON_BOARD_CAPK_0100ND) 613217518Simp strcpy(cpu_board, "CAPK-0100ND"); 614217518Simp if (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_CN3010_EVB_HS5) { 615210311Sjmallett printf("Compiled for CAPK-0100ND, but board type is %s\n", 616210311Sjmallett cvmx_board_type_to_string(cvmx_sysinfo_get()->board_type)); 617217518Simp strcat(cpu_board, " hardwired, but type is "); 618217518Simp strcat(cpu_board, 619217518Simp cvmx_board_type_to_string(cvmx_sysinfo_get()->board_type)); 620217518Simp } 621210311Sjmallett#else 622217518Simp strcpy(cpu_board, 623210311Sjmallett cvmx_board_type_to_string(cvmx_sysinfo_get()->board_type)); 624217518Simp printf("Board: %s\n", cpu_board); 625210311Sjmallett#endif 626217518Simp strcpy(cpu_model, octeon_model_get_string(cvmx_get_proc_id())); 627217518Simp printf("Model: %s\n", cpu_model); 628194140Simp} 629202831Simp/* impEND: This stuff should move back into the Cavium SDK */ 630