1/***********************license start*************** 2 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Networks nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41/** 42 * cvmx-ciu-defs.h 43 * 44 * Configuration and status register (CSR) type definitions for 45 * Octeon ciu. 46 * 47 * This file is auto generated. Do not edit. 48 * 49 * <hr>$Revision$<hr> 50 * 51 */ 52#ifndef __CVMX_CIU_TYPEDEFS_H__ 53#define __CVMX_CIU_TYPEDEFS_H__ 54 55#define CVMX_CIU_BIST (CVMX_ADD_IO_SEG(0x0001070000000730ull)) 56#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 57#define CVMX_CIU_BLOCK_INT CVMX_CIU_BLOCK_INT_FUNC() 58static inline uint64_t CVMX_CIU_BLOCK_INT_FUNC(void) 59{ 60 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 61 cvmx_warn("CVMX_CIU_BLOCK_INT not supported on this chip\n"); 62 return CVMX_ADD_IO_SEG(0x00010700000007C0ull); 63} 64#else 65#define CVMX_CIU_BLOCK_INT (CVMX_ADD_IO_SEG(0x00010700000007C0ull)) 66#endif 67#define CVMX_CIU_DINT (CVMX_ADD_IO_SEG(0x0001070000000720ull)) 68#define CVMX_CIU_FUSE (CVMX_ADD_IO_SEG(0x0001070000000728ull)) 69#define CVMX_CIU_GSTOP (CVMX_ADD_IO_SEG(0x0001070000000710ull)) 70#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 71#define CVMX_CIU_INT33_SUM0 CVMX_CIU_INT33_SUM0_FUNC() 72static inline uint64_t CVMX_CIU_INT33_SUM0_FUNC(void) 73{ 74 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 75 cvmx_warn("CVMX_CIU_INT33_SUM0 not supported on this chip\n"); 76 return CVMX_ADD_IO_SEG(0x0001070000000110ull); 77} 78#else 79#define CVMX_CIU_INT33_SUM0 (CVMX_ADD_IO_SEG(0x0001070000000110ull)) 80#endif 81#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 82static inline uint64_t CVMX_CIU_INTX_EN0(unsigned long offset) 83{ 84 if (!( 85 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1) || (offset == 32))) || 86 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3) || (offset == 32))) || 87 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 32))) || 88 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3) || (offset == 32))) || 89 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7) || (offset == 32))) || 90 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 23) || (offset == 32))) || 91 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32))) || 92 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 11) || ((offset >= 32) && (offset <= 33)))))) 93 cvmx_warn("CVMX_CIU_INTX_EN0(%lu) is invalid on this chip\n", offset); 94 return CVMX_ADD_IO_SEG(0x0001070000000200ull) + ((offset) & 63) * 16; 95} 96#else 97#define CVMX_CIU_INTX_EN0(offset) (CVMX_ADD_IO_SEG(0x0001070000000200ull) + ((offset) & 63) * 16) 98#endif 99#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 100static inline uint64_t CVMX_CIU_INTX_EN0_W1C(unsigned long offset) 101{ 102 if (!( 103 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7) || (offset == 32))) || 104 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 23) || (offset == 32))) || 105 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32))) || 106 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 11) || ((offset >= 32) && (offset <= 33)))))) 107 cvmx_warn("CVMX_CIU_INTX_EN0_W1C(%lu) is invalid on this chip\n", offset); 108 return CVMX_ADD_IO_SEG(0x0001070000002200ull) + ((offset) & 63) * 16; 109} 110#else 111#define CVMX_CIU_INTX_EN0_W1C(offset) (CVMX_ADD_IO_SEG(0x0001070000002200ull) + ((offset) & 63) * 16) 112#endif 113#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 114static inline uint64_t CVMX_CIU_INTX_EN0_W1S(unsigned long offset) 115{ 116 if (!( 117 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7) || (offset == 32))) || 118 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 23) || (offset == 32))) || 119 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32))) || 120 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 11) || ((offset >= 32) && (offset <= 33)))))) 121 cvmx_warn("CVMX_CIU_INTX_EN0_W1S(%lu) is invalid on this chip\n", offset); 122 return CVMX_ADD_IO_SEG(0x0001070000006200ull) + ((offset) & 63) * 16; 123} 124#else 125#define CVMX_CIU_INTX_EN0_W1S(offset) (CVMX_ADD_IO_SEG(0x0001070000006200ull) + ((offset) & 63) * 16) 126#endif 127#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 128static inline uint64_t CVMX_CIU_INTX_EN1(unsigned long offset) 129{ 130 if (!( 131 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1) || (offset == 32))) || 132 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3) || (offset == 32))) || 133 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 32))) || 134 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3) || (offset == 32))) || 135 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7) || (offset == 32))) || 136 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 23) || (offset == 32))) || 137 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32))) || 138 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 11) || ((offset >= 32) && (offset <= 33)))))) 139 cvmx_warn("CVMX_CIU_INTX_EN1(%lu) is invalid on this chip\n", offset); 140 return CVMX_ADD_IO_SEG(0x0001070000000208ull) + ((offset) & 63) * 16; 141} 142#else 143#define CVMX_CIU_INTX_EN1(offset) (CVMX_ADD_IO_SEG(0x0001070000000208ull) + ((offset) & 63) * 16) 144#endif 145#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 146static inline uint64_t CVMX_CIU_INTX_EN1_W1C(unsigned long offset) 147{ 148 if (!( 149 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7) || (offset == 32))) || 150 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 23) || (offset == 32))) || 151 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32))) || 152 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 11) || ((offset >= 32) && (offset <= 33)))))) 153 cvmx_warn("CVMX_CIU_INTX_EN1_W1C(%lu) is invalid on this chip\n", offset); 154 return CVMX_ADD_IO_SEG(0x0001070000002208ull) + ((offset) & 63) * 16; 155} 156#else 157#define CVMX_CIU_INTX_EN1_W1C(offset) (CVMX_ADD_IO_SEG(0x0001070000002208ull) + ((offset) & 63) * 16) 158#endif 159#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 160static inline uint64_t CVMX_CIU_INTX_EN1_W1S(unsigned long offset) 161{ 162 if (!( 163 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7) || (offset == 32))) || 164 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 23) || (offset == 32))) || 165 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32))) || 166 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 11) || ((offset >= 32) && (offset <= 33)))))) 167 cvmx_warn("CVMX_CIU_INTX_EN1_W1S(%lu) is invalid on this chip\n", offset); 168 return CVMX_ADD_IO_SEG(0x0001070000006208ull) + ((offset) & 63) * 16; 169} 170#else 171#define CVMX_CIU_INTX_EN1_W1S(offset) (CVMX_ADD_IO_SEG(0x0001070000006208ull) + ((offset) & 63) * 16) 172#endif 173#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 174static inline uint64_t CVMX_CIU_INTX_EN4_0(unsigned long offset) 175{ 176 if (!( 177 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 178 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) || 179 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) || 180 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) || 181 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5))))) 182 cvmx_warn("CVMX_CIU_INTX_EN4_0(%lu) is invalid on this chip\n", offset); 183 return CVMX_ADD_IO_SEG(0x0001070000000C80ull) + ((offset) & 15) * 16; 184} 185#else 186#define CVMX_CIU_INTX_EN4_0(offset) (CVMX_ADD_IO_SEG(0x0001070000000C80ull) + ((offset) & 15) * 16) 187#endif 188#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 189static inline uint64_t CVMX_CIU_INTX_EN4_0_W1C(unsigned long offset) 190{ 191 if (!( 192 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) || 193 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) || 194 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) || 195 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5))))) 196 cvmx_warn("CVMX_CIU_INTX_EN4_0_W1C(%lu) is invalid on this chip\n", offset); 197 return CVMX_ADD_IO_SEG(0x0001070000002C80ull) + ((offset) & 15) * 16; 198} 199#else 200#define CVMX_CIU_INTX_EN4_0_W1C(offset) (CVMX_ADD_IO_SEG(0x0001070000002C80ull) + ((offset) & 15) * 16) 201#endif 202#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 203static inline uint64_t CVMX_CIU_INTX_EN4_0_W1S(unsigned long offset) 204{ 205 if (!( 206 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) || 207 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) || 208 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) || 209 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5))))) 210 cvmx_warn("CVMX_CIU_INTX_EN4_0_W1S(%lu) is invalid on this chip\n", offset); 211 return CVMX_ADD_IO_SEG(0x0001070000006C80ull) + ((offset) & 15) * 16; 212} 213#else 214#define CVMX_CIU_INTX_EN4_0_W1S(offset) (CVMX_ADD_IO_SEG(0x0001070000006C80ull) + ((offset) & 15) * 16) 215#endif 216#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 217static inline uint64_t CVMX_CIU_INTX_EN4_1(unsigned long offset) 218{ 219 if (!( 220 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 221 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) || 222 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) || 223 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) || 224 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5))))) 225 cvmx_warn("CVMX_CIU_INTX_EN4_1(%lu) is invalid on this chip\n", offset); 226 return CVMX_ADD_IO_SEG(0x0001070000000C88ull) + ((offset) & 15) * 16; 227} 228#else 229#define CVMX_CIU_INTX_EN4_1(offset) (CVMX_ADD_IO_SEG(0x0001070000000C88ull) + ((offset) & 15) * 16) 230#endif 231#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 232static inline uint64_t CVMX_CIU_INTX_EN4_1_W1C(unsigned long offset) 233{ 234 if (!( 235 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) || 236 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) || 237 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) || 238 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5))))) 239 cvmx_warn("CVMX_CIU_INTX_EN4_1_W1C(%lu) is invalid on this chip\n", offset); 240 return CVMX_ADD_IO_SEG(0x0001070000002C88ull) + ((offset) & 15) * 16; 241} 242#else 243#define CVMX_CIU_INTX_EN4_1_W1C(offset) (CVMX_ADD_IO_SEG(0x0001070000002C88ull) + ((offset) & 15) * 16) 244#endif 245#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 246static inline uint64_t CVMX_CIU_INTX_EN4_1_W1S(unsigned long offset) 247{ 248 if (!( 249 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) || 250 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) || 251 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) || 252 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5))))) 253 cvmx_warn("CVMX_CIU_INTX_EN4_1_W1S(%lu) is invalid on this chip\n", offset); 254 return CVMX_ADD_IO_SEG(0x0001070000006C88ull) + ((offset) & 15) * 16; 255} 256#else 257#define CVMX_CIU_INTX_EN4_1_W1S(offset) (CVMX_ADD_IO_SEG(0x0001070000006C88ull) + ((offset) & 15) * 16) 258#endif 259#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 260static inline uint64_t CVMX_CIU_INTX_SUM0(unsigned long offset) 261{ 262 if (!( 263 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1) || (offset == 32))) || 264 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3) || (offset == 32))) || 265 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 32))) || 266 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3) || (offset == 32))) || 267 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7) || (offset == 32))) || 268 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 23) || (offset == 32))) || 269 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 32))) || 270 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 11) || (offset == 32))))) 271 cvmx_warn("CVMX_CIU_INTX_SUM0(%lu) is invalid on this chip\n", offset); 272 return CVMX_ADD_IO_SEG(0x0001070000000000ull) + ((offset) & 63) * 8; 273} 274#else 275#define CVMX_CIU_INTX_SUM0(offset) (CVMX_ADD_IO_SEG(0x0001070000000000ull) + ((offset) & 63) * 8) 276#endif 277#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 278static inline uint64_t CVMX_CIU_INTX_SUM4(unsigned long offset) 279{ 280 if (!( 281 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 282 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) || 283 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) || 284 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) || 285 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5))))) 286 cvmx_warn("CVMX_CIU_INTX_SUM4(%lu) is invalid on this chip\n", offset); 287 return CVMX_ADD_IO_SEG(0x0001070000000C00ull) + ((offset) & 15) * 8; 288} 289#else 290#define CVMX_CIU_INTX_SUM4(offset) (CVMX_ADD_IO_SEG(0x0001070000000C00ull) + ((offset) & 15) * 8) 291#endif 292#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 293#define CVMX_CIU_INT_DBG_SEL CVMX_CIU_INT_DBG_SEL_FUNC() 294static inline uint64_t CVMX_CIU_INT_DBG_SEL_FUNC(void) 295{ 296 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 297 cvmx_warn("CVMX_CIU_INT_DBG_SEL not supported on this chip\n"); 298 return CVMX_ADD_IO_SEG(0x00010700000007D0ull); 299} 300#else 301#define CVMX_CIU_INT_DBG_SEL (CVMX_ADD_IO_SEG(0x00010700000007D0ull)) 302#endif 303#define CVMX_CIU_INT_SUM1 (CVMX_ADD_IO_SEG(0x0001070000000108ull)) 304#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 305static inline uint64_t CVMX_CIU_MBOX_CLRX(unsigned long offset) 306{ 307 if (!( 308 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) || 309 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 310 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) || 311 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 312 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) || 313 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) || 314 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) || 315 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5))))) 316 cvmx_warn("CVMX_CIU_MBOX_CLRX(%lu) is invalid on this chip\n", offset); 317 return CVMX_ADD_IO_SEG(0x0001070000000680ull) + ((offset) & 15) * 8; 318} 319#else 320#define CVMX_CIU_MBOX_CLRX(offset) (CVMX_ADD_IO_SEG(0x0001070000000680ull) + ((offset) & 15) * 8) 321#endif 322#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 323static inline uint64_t CVMX_CIU_MBOX_SETX(unsigned long offset) 324{ 325 if (!( 326 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) || 327 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 328 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) || 329 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 330 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) || 331 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) || 332 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) || 333 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5))))) 334 cvmx_warn("CVMX_CIU_MBOX_SETX(%lu) is invalid on this chip\n", offset); 335 return CVMX_ADD_IO_SEG(0x0001070000000600ull) + ((offset) & 15) * 8; 336} 337#else 338#define CVMX_CIU_MBOX_SETX(offset) (CVMX_ADD_IO_SEG(0x0001070000000600ull) + ((offset) & 15) * 8) 339#endif 340#define CVMX_CIU_NMI (CVMX_ADD_IO_SEG(0x0001070000000718ull)) 341#define CVMX_CIU_PCI_INTA (CVMX_ADD_IO_SEG(0x0001070000000750ull)) 342#define CVMX_CIU_PP_DBG (CVMX_ADD_IO_SEG(0x0001070000000708ull)) 343#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 344static inline uint64_t CVMX_CIU_PP_POKEX(unsigned long offset) 345{ 346 if (!( 347 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) || 348 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 349 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) || 350 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 351 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) || 352 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) || 353 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) || 354 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5))))) 355 cvmx_warn("CVMX_CIU_PP_POKEX(%lu) is invalid on this chip\n", offset); 356 return CVMX_ADD_IO_SEG(0x0001070000000580ull) + ((offset) & 15) * 8; 357} 358#else 359#define CVMX_CIU_PP_POKEX(offset) (CVMX_ADD_IO_SEG(0x0001070000000580ull) + ((offset) & 15) * 8) 360#endif 361#define CVMX_CIU_PP_RST (CVMX_ADD_IO_SEG(0x0001070000000700ull)) 362#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 363#define CVMX_CIU_QLM0 CVMX_CIU_QLM0_FUNC() 364static inline uint64_t CVMX_CIU_QLM0_FUNC(void) 365{ 366 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 367 cvmx_warn("CVMX_CIU_QLM0 not supported on this chip\n"); 368 return CVMX_ADD_IO_SEG(0x0001070000000780ull); 369} 370#else 371#define CVMX_CIU_QLM0 (CVMX_ADD_IO_SEG(0x0001070000000780ull)) 372#endif 373#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 374#define CVMX_CIU_QLM1 CVMX_CIU_QLM1_FUNC() 375static inline uint64_t CVMX_CIU_QLM1_FUNC(void) 376{ 377 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 378 cvmx_warn("CVMX_CIU_QLM1 not supported on this chip\n"); 379 return CVMX_ADD_IO_SEG(0x0001070000000788ull); 380} 381#else 382#define CVMX_CIU_QLM1 (CVMX_ADD_IO_SEG(0x0001070000000788ull)) 383#endif 384#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 385#define CVMX_CIU_QLM2 CVMX_CIU_QLM2_FUNC() 386static inline uint64_t CVMX_CIU_QLM2_FUNC(void) 387{ 388 if (!(OCTEON_IS_MODEL(OCTEON_CN63XX))) 389 cvmx_warn("CVMX_CIU_QLM2 not supported on this chip\n"); 390 return CVMX_ADD_IO_SEG(0x0001070000000790ull); 391} 392#else 393#define CVMX_CIU_QLM2 (CVMX_ADD_IO_SEG(0x0001070000000790ull)) 394#endif 395#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 396#define CVMX_CIU_QLM_DCOK CVMX_CIU_QLM_DCOK_FUNC() 397static inline uint64_t CVMX_CIU_QLM_DCOK_FUNC(void) 398{ 399 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX))) 400 cvmx_warn("CVMX_CIU_QLM_DCOK not supported on this chip\n"); 401 return CVMX_ADD_IO_SEG(0x0001070000000760ull); 402} 403#else 404#define CVMX_CIU_QLM_DCOK (CVMX_ADD_IO_SEG(0x0001070000000760ull)) 405#endif 406#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 407#define CVMX_CIU_QLM_JTGC CVMX_CIU_QLM_JTGC_FUNC() 408static inline uint64_t CVMX_CIU_QLM_JTGC_FUNC(void) 409{ 410 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 411 cvmx_warn("CVMX_CIU_QLM_JTGC not supported on this chip\n"); 412 return CVMX_ADD_IO_SEG(0x0001070000000768ull); 413} 414#else 415#define CVMX_CIU_QLM_JTGC (CVMX_ADD_IO_SEG(0x0001070000000768ull)) 416#endif 417#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 418#define CVMX_CIU_QLM_JTGD CVMX_CIU_QLM_JTGD_FUNC() 419static inline uint64_t CVMX_CIU_QLM_JTGD_FUNC(void) 420{ 421 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 422 cvmx_warn("CVMX_CIU_QLM_JTGD not supported on this chip\n"); 423 return CVMX_ADD_IO_SEG(0x0001070000000770ull); 424} 425#else 426#define CVMX_CIU_QLM_JTGD (CVMX_ADD_IO_SEG(0x0001070000000770ull)) 427#endif 428#define CVMX_CIU_SOFT_BIST (CVMX_ADD_IO_SEG(0x0001070000000738ull)) 429#define CVMX_CIU_SOFT_PRST (CVMX_ADD_IO_SEG(0x0001070000000748ull)) 430#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 431#define CVMX_CIU_SOFT_PRST1 CVMX_CIU_SOFT_PRST1_FUNC() 432static inline uint64_t CVMX_CIU_SOFT_PRST1_FUNC(void) 433{ 434 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))) 435 cvmx_warn("CVMX_CIU_SOFT_PRST1 not supported on this chip\n"); 436 return CVMX_ADD_IO_SEG(0x0001070000000758ull); 437} 438#else 439#define CVMX_CIU_SOFT_PRST1 (CVMX_ADD_IO_SEG(0x0001070000000758ull)) 440#endif 441#define CVMX_CIU_SOFT_RST (CVMX_ADD_IO_SEG(0x0001070000000740ull)) 442#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 443static inline uint64_t CVMX_CIU_TIMX(unsigned long offset) 444{ 445 if (!( 446 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 3))) || 447 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 3))) || 448 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) || 449 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) || 450 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) || 451 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3))) || 452 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))) || 453 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3))))) 454 cvmx_warn("CVMX_CIU_TIMX(%lu) is invalid on this chip\n", offset); 455 return CVMX_ADD_IO_SEG(0x0001070000000480ull) + ((offset) & 3) * 8; 456} 457#else 458#define CVMX_CIU_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001070000000480ull) + ((offset) & 3) * 8) 459#endif 460#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 461static inline uint64_t CVMX_CIU_WDOGX(unsigned long offset) 462{ 463 if (!( 464 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) || 465 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 466 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) || 467 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 468 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) || 469 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) || 470 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) || 471 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5))))) 472 cvmx_warn("CVMX_CIU_WDOGX(%lu) is invalid on this chip\n", offset); 473 return CVMX_ADD_IO_SEG(0x0001070000000500ull) + ((offset) & 15) * 8; 474} 475#else 476#define CVMX_CIU_WDOGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000500ull) + ((offset) & 15) * 8) 477#endif 478 479/** 480 * cvmx_ciu_bist 481 */ 482union cvmx_ciu_bist 483{ 484 uint64_t u64; 485 struct cvmx_ciu_bist_s 486 { 487#if __BYTE_ORDER == __BIG_ENDIAN 488 uint64_t reserved_5_63 : 59; 489 uint64_t bist : 5; /**< BIST Results. 490 HW sets a bit in BIST for for memory that fails 491 BIST. */ 492#else 493 uint64_t bist : 5; 494 uint64_t reserved_5_63 : 59; 495#endif 496 } s; 497 struct cvmx_ciu_bist_cn30xx 498 { 499#if __BYTE_ORDER == __BIG_ENDIAN 500 uint64_t reserved_4_63 : 60; 501 uint64_t bist : 4; /**< BIST Results. 502 HW sets a bit in BIST for for memory that fails 503 BIST. */ 504#else 505 uint64_t bist : 4; 506 uint64_t reserved_4_63 : 60; 507#endif 508 } cn30xx; 509 struct cvmx_ciu_bist_cn30xx cn31xx; 510 struct cvmx_ciu_bist_cn30xx cn38xx; 511 struct cvmx_ciu_bist_cn30xx cn38xxp2; 512 struct cvmx_ciu_bist_cn50xx 513 { 514#if __BYTE_ORDER == __BIG_ENDIAN 515 uint64_t reserved_2_63 : 62; 516 uint64_t bist : 2; /**< BIST Results. 517 HW sets a bit in BIST for for memory that fails 518 BIST. */ 519#else 520 uint64_t bist : 2; 521 uint64_t reserved_2_63 : 62; 522#endif 523 } cn50xx; 524 struct cvmx_ciu_bist_cn52xx 525 { 526#if __BYTE_ORDER == __BIG_ENDIAN 527 uint64_t reserved_3_63 : 61; 528 uint64_t bist : 3; /**< BIST Results. 529 HW sets a bit in BIST for for memory that fails 530 BIST. */ 531#else 532 uint64_t bist : 3; 533 uint64_t reserved_3_63 : 61; 534#endif 535 } cn52xx; 536 struct cvmx_ciu_bist_cn52xx cn52xxp1; 537 struct cvmx_ciu_bist_cn30xx cn56xx; 538 struct cvmx_ciu_bist_cn30xx cn56xxp1; 539 struct cvmx_ciu_bist_cn30xx cn58xx; 540 struct cvmx_ciu_bist_cn30xx cn58xxp1; 541 struct cvmx_ciu_bist_s cn63xx; 542 struct cvmx_ciu_bist_s cn63xxp1; 543}; 544typedef union cvmx_ciu_bist cvmx_ciu_bist_t; 545 546/** 547 * cvmx_ciu_block_int 548 * 549 * CIU_BLOCK_INT = CIU Blocks Interrupt 550 * 551 * The interrupt lines from the various chip blocks. 552 */ 553union cvmx_ciu_block_int 554{ 555 uint64_t u64; 556 struct cvmx_ciu_block_int_s 557 { 558#if __BYTE_ORDER == __BIG_ENDIAN 559 uint64_t reserved_43_63 : 21; 560 uint64_t ptp : 1; /**< PTP interrupt 561 See CIU_INT_SUM1[PTP] */ 562 uint64_t dpi : 1; /**< DPI interrupt 563 See DPI_INT_REG */ 564 uint64_t dfm : 1; /**< DFM interrupt 565 See DFM_FNT_STAT */ 566 uint64_t reserved_34_39 : 6; 567 uint64_t srio1 : 1; /**< SRIO1 interrupt 568 See SRIO1_INT_REG */ 569 uint64_t srio0 : 1; /**< SRIO0 interrupt 570 See SRIO0_INT_REG */ 571 uint64_t reserved_31_31 : 1; 572 uint64_t iob : 1; /**< IOB interrupt 573 See IOB_INT_SUM */ 574 uint64_t reserved_29_29 : 1; 575 uint64_t agl : 1; /**< AGL interrupt 576 See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */ 577 uint64_t reserved_27_27 : 1; 578 uint64_t pem1 : 1; /**< PEM1 interrupt 579 See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */ 580 uint64_t pem0 : 1; /**< PEM0 interrupt 581 See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */ 582 uint64_t reserved_23_24 : 2; 583 uint64_t asxpcs0 : 1; /**< See PCS0_INT*_REG, PCSX0_INT_REG */ 584 uint64_t reserved_21_21 : 1; 585 uint64_t pip : 1; /**< PIP interrupt 586 See PIP_INT_REG */ 587 uint64_t reserved_18_19 : 2; 588 uint64_t lmc0 : 1; /**< LMC0 interrupt 589 See LMC0_INT */ 590 uint64_t l2c : 1; /**< L2C interrupt 591 See L2C_INT_REG */ 592 uint64_t reserved_15_15 : 1; 593 uint64_t rad : 1; /**< RAD interrupt 594 See RAD_REG_ERROR */ 595 uint64_t usb : 1; /**< USB UCTL0 interrupt 596 See UCTL0_INT_REG */ 597 uint64_t pow : 1; /**< POW err interrupt 598 See POW_ECC_ERR */ 599 uint64_t tim : 1; /**< TIM interrupt 600 See TIM_REG_ERROR */ 601 uint64_t pko : 1; /**< PKO interrupt 602 See PKO_REG_ERROR */ 603 uint64_t ipd : 1; /**< IPD interrupt 604 See IPD_INT_SUM */ 605 uint64_t reserved_8_8 : 1; 606 uint64_t zip : 1; /**< ZIP interrupt 607 See ZIP_ERROR */ 608 uint64_t dfa : 1; /**< DFA interrupt 609 See DFA_ERROR */ 610 uint64_t fpa : 1; /**< FPA interrupt 611 See FPA_INT_SUM */ 612 uint64_t key : 1; /**< KEY interrupt 613 See KEY_INT_SUM */ 614 uint64_t sli : 1; /**< SLI interrupt 615 See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */ 616 uint64_t reserved_2_2 : 1; 617 uint64_t gmx0 : 1; /**< GMX0 interrupt 618 See GMX0_RX*_INT_REG, GMX0_TX_INT_REG */ 619 uint64_t mio : 1; /**< MIO boot interrupt 620 See MIO_BOOT_ERR */ 621#else 622 uint64_t mio : 1; 623 uint64_t gmx0 : 1; 624 uint64_t reserved_2_2 : 1; 625 uint64_t sli : 1; 626 uint64_t key : 1; 627 uint64_t fpa : 1; 628 uint64_t dfa : 1; 629 uint64_t zip : 1; 630 uint64_t reserved_8_8 : 1; 631 uint64_t ipd : 1; 632 uint64_t pko : 1; 633 uint64_t tim : 1; 634 uint64_t pow : 1; 635 uint64_t usb : 1; 636 uint64_t rad : 1; 637 uint64_t reserved_15_15 : 1; 638 uint64_t l2c : 1; 639 uint64_t lmc0 : 1; 640 uint64_t reserved_18_19 : 2; 641 uint64_t pip : 1; 642 uint64_t reserved_21_21 : 1; 643 uint64_t asxpcs0 : 1; 644 uint64_t reserved_23_24 : 2; 645 uint64_t pem0 : 1; 646 uint64_t pem1 : 1; 647 uint64_t reserved_27_27 : 1; 648 uint64_t agl : 1; 649 uint64_t reserved_29_29 : 1; 650 uint64_t iob : 1; 651 uint64_t reserved_31_31 : 1; 652 uint64_t srio0 : 1; 653 uint64_t srio1 : 1; 654 uint64_t reserved_34_39 : 6; 655 uint64_t dfm : 1; 656 uint64_t dpi : 1; 657 uint64_t ptp : 1; 658 uint64_t reserved_43_63 : 21; 659#endif 660 } s; 661 struct cvmx_ciu_block_int_s cn63xx; 662 struct cvmx_ciu_block_int_s cn63xxp1; 663}; 664typedef union cvmx_ciu_block_int cvmx_ciu_block_int_t; 665 666/** 667 * cvmx_ciu_dint 668 */ 669union cvmx_ciu_dint 670{ 671 uint64_t u64; 672 struct cvmx_ciu_dint_s 673 { 674#if __BYTE_ORDER == __BIG_ENDIAN 675 uint64_t reserved_16_63 : 48; 676 uint64_t dint : 16; /**< Send DINT pulse to PP vector */ 677#else 678 uint64_t dint : 16; 679 uint64_t reserved_16_63 : 48; 680#endif 681 } s; 682 struct cvmx_ciu_dint_cn30xx 683 { 684#if __BYTE_ORDER == __BIG_ENDIAN 685 uint64_t reserved_1_63 : 63; 686 uint64_t dint : 1; /**< Send DINT pulse to PP vector */ 687#else 688 uint64_t dint : 1; 689 uint64_t reserved_1_63 : 63; 690#endif 691 } cn30xx; 692 struct cvmx_ciu_dint_cn31xx 693 { 694#if __BYTE_ORDER == __BIG_ENDIAN 695 uint64_t reserved_2_63 : 62; 696 uint64_t dint : 2; /**< Send DINT pulse to PP vector */ 697#else 698 uint64_t dint : 2; 699 uint64_t reserved_2_63 : 62; 700#endif 701 } cn31xx; 702 struct cvmx_ciu_dint_s cn38xx; 703 struct cvmx_ciu_dint_s cn38xxp2; 704 struct cvmx_ciu_dint_cn31xx cn50xx; 705 struct cvmx_ciu_dint_cn52xx 706 { 707#if __BYTE_ORDER == __BIG_ENDIAN 708 uint64_t reserved_4_63 : 60; 709 uint64_t dint : 4; /**< Send DINT pulse to PP vector */ 710#else 711 uint64_t dint : 4; 712 uint64_t reserved_4_63 : 60; 713#endif 714 } cn52xx; 715 struct cvmx_ciu_dint_cn52xx cn52xxp1; 716 struct cvmx_ciu_dint_cn56xx 717 { 718#if __BYTE_ORDER == __BIG_ENDIAN 719 uint64_t reserved_12_63 : 52; 720 uint64_t dint : 12; /**< Send DINT pulse to PP vector */ 721#else 722 uint64_t dint : 12; 723 uint64_t reserved_12_63 : 52; 724#endif 725 } cn56xx; 726 struct cvmx_ciu_dint_cn56xx cn56xxp1; 727 struct cvmx_ciu_dint_s cn58xx; 728 struct cvmx_ciu_dint_s cn58xxp1; 729 struct cvmx_ciu_dint_cn63xx 730 { 731#if __BYTE_ORDER == __BIG_ENDIAN 732 uint64_t reserved_6_63 : 58; 733 uint64_t dint : 6; /**< Send DINT pulse to PP vector */ 734#else 735 uint64_t dint : 6; 736 uint64_t reserved_6_63 : 58; 737#endif 738 } cn63xx; 739 struct cvmx_ciu_dint_cn63xx cn63xxp1; 740}; 741typedef union cvmx_ciu_dint cvmx_ciu_dint_t; 742 743/** 744 * cvmx_ciu_fuse 745 */ 746union cvmx_ciu_fuse 747{ 748 uint64_t u64; 749 struct cvmx_ciu_fuse_s 750 { 751#if __BYTE_ORDER == __BIG_ENDIAN 752 uint64_t reserved_16_63 : 48; 753 uint64_t fuse : 16; /**< Physical PP is present */ 754#else 755 uint64_t fuse : 16; 756 uint64_t reserved_16_63 : 48; 757#endif 758 } s; 759 struct cvmx_ciu_fuse_cn30xx 760 { 761#if __BYTE_ORDER == __BIG_ENDIAN 762 uint64_t reserved_1_63 : 63; 763 uint64_t fuse : 1; /**< Physical PP is present */ 764#else 765 uint64_t fuse : 1; 766 uint64_t reserved_1_63 : 63; 767#endif 768 } cn30xx; 769 struct cvmx_ciu_fuse_cn31xx 770 { 771#if __BYTE_ORDER == __BIG_ENDIAN 772 uint64_t reserved_2_63 : 62; 773 uint64_t fuse : 2; /**< Physical PP is present */ 774#else 775 uint64_t fuse : 2; 776 uint64_t reserved_2_63 : 62; 777#endif 778 } cn31xx; 779 struct cvmx_ciu_fuse_s cn38xx; 780 struct cvmx_ciu_fuse_s cn38xxp2; 781 struct cvmx_ciu_fuse_cn31xx cn50xx; 782 struct cvmx_ciu_fuse_cn52xx 783 { 784#if __BYTE_ORDER == __BIG_ENDIAN 785 uint64_t reserved_4_63 : 60; 786 uint64_t fuse : 4; /**< Physical PP is present */ 787#else 788 uint64_t fuse : 4; 789 uint64_t reserved_4_63 : 60; 790#endif 791 } cn52xx; 792 struct cvmx_ciu_fuse_cn52xx cn52xxp1; 793 struct cvmx_ciu_fuse_cn56xx 794 { 795#if __BYTE_ORDER == __BIG_ENDIAN 796 uint64_t reserved_12_63 : 52; 797 uint64_t fuse : 12; /**< Physical PP is present */ 798#else 799 uint64_t fuse : 12; 800 uint64_t reserved_12_63 : 52; 801#endif 802 } cn56xx; 803 struct cvmx_ciu_fuse_cn56xx cn56xxp1; 804 struct cvmx_ciu_fuse_s cn58xx; 805 struct cvmx_ciu_fuse_s cn58xxp1; 806 struct cvmx_ciu_fuse_cn63xx 807 { 808#if __BYTE_ORDER == __BIG_ENDIAN 809 uint64_t reserved_6_63 : 58; 810 uint64_t fuse : 6; /**< Physical PP is present */ 811#else 812 uint64_t fuse : 6; 813 uint64_t reserved_6_63 : 58; 814#endif 815 } cn63xx; 816 struct cvmx_ciu_fuse_cn63xx cn63xxp1; 817}; 818typedef union cvmx_ciu_fuse cvmx_ciu_fuse_t; 819 820/** 821 * cvmx_ciu_gstop 822 */ 823union cvmx_ciu_gstop 824{ 825 uint64_t u64; 826 struct cvmx_ciu_gstop_s 827 { 828#if __BYTE_ORDER == __BIG_ENDIAN 829 uint64_t reserved_1_63 : 63; 830 uint64_t gstop : 1; /**< GSTOP bit */ 831#else 832 uint64_t gstop : 1; 833 uint64_t reserved_1_63 : 63; 834#endif 835 } s; 836 struct cvmx_ciu_gstop_s cn30xx; 837 struct cvmx_ciu_gstop_s cn31xx; 838 struct cvmx_ciu_gstop_s cn38xx; 839 struct cvmx_ciu_gstop_s cn38xxp2; 840 struct cvmx_ciu_gstop_s cn50xx; 841 struct cvmx_ciu_gstop_s cn52xx; 842 struct cvmx_ciu_gstop_s cn52xxp1; 843 struct cvmx_ciu_gstop_s cn56xx; 844 struct cvmx_ciu_gstop_s cn56xxp1; 845 struct cvmx_ciu_gstop_s cn58xx; 846 struct cvmx_ciu_gstop_s cn58xxp1; 847 struct cvmx_ciu_gstop_s cn63xx; 848 struct cvmx_ciu_gstop_s cn63xxp1; 849}; 850typedef union cvmx_ciu_gstop cvmx_ciu_gstop_t; 851 852/** 853 * cvmx_ciu_int#_en0 854 * 855 * Notes: 856 * CIU_INT0_EN0: PP0 /IP2 857 * CIU_INT1_EN0: PP0 /IP3 858 * ... 859 * CIU_INT6_EN0: PP3/IP2 860 * CIU_INT7_EN0: PP3/IP3 861 * (hole) 862 * CIU_INT32_EN0: PCI /IP 863 */ 864union cvmx_ciu_intx_en0 865{ 866 uint64_t u64; 867 struct cvmx_ciu_intx_en0_s 868 { 869#if __BYTE_ORDER == __BIG_ENDIAN 870 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt enable */ 871 uint64_t mii : 1; /**< RGMII/MII/MIX Interface 0 Interrupt enable */ 872 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt enable */ 873 uint64_t powiq : 1; /**< POW IQ interrupt enable */ 874 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt enable */ 875 uint64_t mpi : 1; /**< MPI/SPI interrupt */ 876 uint64_t pcm : 1; /**< PCM/TDM interrupt */ 877 uint64_t usb : 1; /**< USB EHCI or OHCI Interrupt enable */ 878 uint64_t timer : 4; /**< General timer interrupt enables */ 879 uint64_t key_zero : 1; /**< Key Zeroization interrupt */ 880 uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt enable */ 881 uint64_t gmx_drp : 2; /**< GMX packet drop interrupt enable */ 882 uint64_t trace : 1; /**< Trace buffer interrupt enable */ 883 uint64_t rml : 1; /**< RML Interrupt enable */ 884 uint64_t twsi : 1; /**< TWSI Interrupt enable */ 885 uint64_t reserved_44_44 : 1; 886 uint64_t pci_msi : 4; /**< PCIe/sRIO MSI enables */ 887 uint64_t pci_int : 4; /**< PCIe INTA/B/C/D enables */ 888 uint64_t uart : 2; /**< Two UART interrupt enables */ 889 uint64_t mbox : 2; /**< Two mailbox/PCIe/sRIO interrupt enables */ 890 uint64_t gpio : 16; /**< 16 GPIO interrupt enables */ 891 uint64_t workq : 16; /**< 16 work queue interrupt enables */ 892#else 893 uint64_t workq : 16; 894 uint64_t gpio : 16; 895 uint64_t mbox : 2; 896 uint64_t uart : 2; 897 uint64_t pci_int : 4; 898 uint64_t pci_msi : 4; 899 uint64_t reserved_44_44 : 1; 900 uint64_t twsi : 1; 901 uint64_t rml : 1; 902 uint64_t trace : 1; 903 uint64_t gmx_drp : 2; 904 uint64_t ipd_drp : 1; 905 uint64_t key_zero : 1; 906 uint64_t timer : 4; 907 uint64_t usb : 1; 908 uint64_t pcm : 1; 909 uint64_t mpi : 1; 910 uint64_t twsi2 : 1; 911 uint64_t powiq : 1; 912 uint64_t ipdppthr : 1; 913 uint64_t mii : 1; 914 uint64_t bootdma : 1; 915#endif 916 } s; 917 struct cvmx_ciu_intx_en0_cn30xx 918 { 919#if __BYTE_ORDER == __BIG_ENDIAN 920 uint64_t reserved_59_63 : 5; 921 uint64_t mpi : 1; /**< MPI/SPI interrupt */ 922 uint64_t pcm : 1; /**< PCM/TDM interrupt */ 923 uint64_t usb : 1; /**< USB interrupt */ 924 uint64_t timer : 4; /**< General timer interrupts */ 925 uint64_t reserved_51_51 : 1; 926 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */ 927 uint64_t reserved_49_49 : 1; 928 uint64_t gmx_drp : 1; /**< GMX packet drop */ 929 uint64_t reserved_47_47 : 1; 930 uint64_t rml : 1; /**< RML Interrupt */ 931 uint64_t twsi : 1; /**< TWSI Interrupt */ 932 uint64_t reserved_44_44 : 1; 933 uint64_t pci_msi : 4; /**< PCI MSI */ 934 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */ 935 uint64_t uart : 2; /**< Two UART interrupts */ 936 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */ 937 uint64_t gpio : 16; /**< 16 GPIO interrupts */ 938 uint64_t workq : 16; /**< 16 work queue interrupts */ 939#else 940 uint64_t workq : 16; 941 uint64_t gpio : 16; 942 uint64_t mbox : 2; 943 uint64_t uart : 2; 944 uint64_t pci_int : 4; 945 uint64_t pci_msi : 4; 946 uint64_t reserved_44_44 : 1; 947 uint64_t twsi : 1; 948 uint64_t rml : 1; 949 uint64_t reserved_47_47 : 1; 950 uint64_t gmx_drp : 1; 951 uint64_t reserved_49_49 : 1; 952 uint64_t ipd_drp : 1; 953 uint64_t reserved_51_51 : 1; 954 uint64_t timer : 4; 955 uint64_t usb : 1; 956 uint64_t pcm : 1; 957 uint64_t mpi : 1; 958 uint64_t reserved_59_63 : 5; 959#endif 960 } cn30xx; 961 struct cvmx_ciu_intx_en0_cn31xx 962 { 963#if __BYTE_ORDER == __BIG_ENDIAN 964 uint64_t reserved_59_63 : 5; 965 uint64_t mpi : 1; /**< MPI/SPI interrupt */ 966 uint64_t pcm : 1; /**< PCM/TDM interrupt */ 967 uint64_t usb : 1; /**< USB interrupt */ 968 uint64_t timer : 4; /**< General timer interrupts */ 969 uint64_t reserved_51_51 : 1; 970 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */ 971 uint64_t reserved_49_49 : 1; 972 uint64_t gmx_drp : 1; /**< GMX packet drop */ 973 uint64_t trace : 1; /**< L2C has the CMB trace buffer */ 974 uint64_t rml : 1; /**< RML Interrupt */ 975 uint64_t twsi : 1; /**< TWSI Interrupt */ 976 uint64_t reserved_44_44 : 1; 977 uint64_t pci_msi : 4; /**< PCI MSI */ 978 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */ 979 uint64_t uart : 2; /**< Two UART interrupts */ 980 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */ 981 uint64_t gpio : 16; /**< 16 GPIO interrupts */ 982 uint64_t workq : 16; /**< 16 work queue interrupts */ 983#else 984 uint64_t workq : 16; 985 uint64_t gpio : 16; 986 uint64_t mbox : 2; 987 uint64_t uart : 2; 988 uint64_t pci_int : 4; 989 uint64_t pci_msi : 4; 990 uint64_t reserved_44_44 : 1; 991 uint64_t twsi : 1; 992 uint64_t rml : 1; 993 uint64_t trace : 1; 994 uint64_t gmx_drp : 1; 995 uint64_t reserved_49_49 : 1; 996 uint64_t ipd_drp : 1; 997 uint64_t reserved_51_51 : 1; 998 uint64_t timer : 4; 999 uint64_t usb : 1; 1000 uint64_t pcm : 1; 1001 uint64_t mpi : 1; 1002 uint64_t reserved_59_63 : 5; 1003#endif 1004 } cn31xx; 1005 struct cvmx_ciu_intx_en0_cn38xx 1006 { 1007#if __BYTE_ORDER == __BIG_ENDIAN 1008 uint64_t reserved_56_63 : 8; 1009 uint64_t timer : 4; /**< General timer interrupts */ 1010 uint64_t key_zero : 1; /**< Key Zeroization interrupt */ 1011 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */ 1012 uint64_t gmx_drp : 2; /**< GMX packet drop */ 1013 uint64_t trace : 1; /**< L2C has the CMB trace buffer */ 1014 uint64_t rml : 1; /**< RML Interrupt */ 1015 uint64_t twsi : 1; /**< TWSI Interrupt */ 1016 uint64_t reserved_44_44 : 1; 1017 uint64_t pci_msi : 4; /**< PCI MSI */ 1018 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */ 1019 uint64_t uart : 2; /**< Two UART interrupts */ 1020 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */ 1021 uint64_t gpio : 16; /**< 16 GPIO interrupts */ 1022 uint64_t workq : 16; /**< 16 work queue interrupts */ 1023#else 1024 uint64_t workq : 16; 1025 uint64_t gpio : 16; 1026 uint64_t mbox : 2; 1027 uint64_t uart : 2; 1028 uint64_t pci_int : 4; 1029 uint64_t pci_msi : 4; 1030 uint64_t reserved_44_44 : 1; 1031 uint64_t twsi : 1; 1032 uint64_t rml : 1; 1033 uint64_t trace : 1; 1034 uint64_t gmx_drp : 2; 1035 uint64_t ipd_drp : 1; 1036 uint64_t key_zero : 1; 1037 uint64_t timer : 4; 1038 uint64_t reserved_56_63 : 8; 1039#endif 1040 } cn38xx; 1041 struct cvmx_ciu_intx_en0_cn38xx cn38xxp2; 1042 struct cvmx_ciu_intx_en0_cn30xx cn50xx; 1043 struct cvmx_ciu_intx_en0_cn52xx 1044 { 1045#if __BYTE_ORDER == __BIG_ENDIAN 1046 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt */ 1047 uint64_t mii : 1; /**< MII Interface Interrupt */ 1048 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt */ 1049 uint64_t powiq : 1; /**< POW IQ interrupt */ 1050 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt */ 1051 uint64_t reserved_57_58 : 2; 1052 uint64_t usb : 1; /**< USB Interrupt */ 1053 uint64_t timer : 4; /**< General timer interrupts */ 1054 uint64_t reserved_51_51 : 1; 1055 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */ 1056 uint64_t reserved_49_49 : 1; 1057 uint64_t gmx_drp : 1; /**< GMX packet drop */ 1058 uint64_t trace : 1; /**< L2C has the CMB trace buffer */ 1059 uint64_t rml : 1; /**< RML Interrupt */ 1060 uint64_t twsi : 1; /**< TWSI Interrupt */ 1061 uint64_t reserved_44_44 : 1; 1062 uint64_t pci_msi : 4; /**< PCI MSI */ 1063 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */ 1064 uint64_t uart : 2; /**< Two UART interrupts */ 1065 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */ 1066 uint64_t gpio : 16; /**< 16 GPIO interrupts */ 1067 uint64_t workq : 16; /**< 16 work queue interrupts */ 1068#else 1069 uint64_t workq : 16; 1070 uint64_t gpio : 16; 1071 uint64_t mbox : 2; 1072 uint64_t uart : 2; 1073 uint64_t pci_int : 4; 1074 uint64_t pci_msi : 4; 1075 uint64_t reserved_44_44 : 1; 1076 uint64_t twsi : 1; 1077 uint64_t rml : 1; 1078 uint64_t trace : 1; 1079 uint64_t gmx_drp : 1; 1080 uint64_t reserved_49_49 : 1; 1081 uint64_t ipd_drp : 1; 1082 uint64_t reserved_51_51 : 1; 1083 uint64_t timer : 4; 1084 uint64_t usb : 1; 1085 uint64_t reserved_57_58 : 2; 1086 uint64_t twsi2 : 1; 1087 uint64_t powiq : 1; 1088 uint64_t ipdppthr : 1; 1089 uint64_t mii : 1; 1090 uint64_t bootdma : 1; 1091#endif 1092 } cn52xx; 1093 struct cvmx_ciu_intx_en0_cn52xx cn52xxp1; 1094 struct cvmx_ciu_intx_en0_cn56xx 1095 { 1096#if __BYTE_ORDER == __BIG_ENDIAN 1097 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt */ 1098 uint64_t mii : 1; /**< MII Interface Interrupt */ 1099 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt */ 1100 uint64_t powiq : 1; /**< POW IQ interrupt */ 1101 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt */ 1102 uint64_t reserved_57_58 : 2; 1103 uint64_t usb : 1; /**< USB Interrupt */ 1104 uint64_t timer : 4; /**< General timer interrupts */ 1105 uint64_t key_zero : 1; /**< Key Zeroization interrupt */ 1106 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */ 1107 uint64_t gmx_drp : 2; /**< GMX packet drop */ 1108 uint64_t trace : 1; /**< L2C has the CMB trace buffer */ 1109 uint64_t rml : 1; /**< RML Interrupt */ 1110 uint64_t twsi : 1; /**< TWSI Interrupt */ 1111 uint64_t reserved_44_44 : 1; 1112 uint64_t pci_msi : 4; /**< PCI MSI */ 1113 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */ 1114 uint64_t uart : 2; /**< Two UART interrupts */ 1115 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */ 1116 uint64_t gpio : 16; /**< 16 GPIO interrupts */ 1117 uint64_t workq : 16; /**< 16 work queue interrupts */ 1118#else 1119 uint64_t workq : 16; 1120 uint64_t gpio : 16; 1121 uint64_t mbox : 2; 1122 uint64_t uart : 2; 1123 uint64_t pci_int : 4; 1124 uint64_t pci_msi : 4; 1125 uint64_t reserved_44_44 : 1; 1126 uint64_t twsi : 1; 1127 uint64_t rml : 1; 1128 uint64_t trace : 1; 1129 uint64_t gmx_drp : 2; 1130 uint64_t ipd_drp : 1; 1131 uint64_t key_zero : 1; 1132 uint64_t timer : 4; 1133 uint64_t usb : 1; 1134 uint64_t reserved_57_58 : 2; 1135 uint64_t twsi2 : 1; 1136 uint64_t powiq : 1; 1137 uint64_t ipdppthr : 1; 1138 uint64_t mii : 1; 1139 uint64_t bootdma : 1; 1140#endif 1141 } cn56xx; 1142 struct cvmx_ciu_intx_en0_cn56xx cn56xxp1; 1143 struct cvmx_ciu_intx_en0_cn38xx cn58xx; 1144 struct cvmx_ciu_intx_en0_cn38xx cn58xxp1; 1145 struct cvmx_ciu_intx_en0_cn52xx cn63xx; 1146 struct cvmx_ciu_intx_en0_cn52xx cn63xxp1; 1147}; 1148typedef union cvmx_ciu_intx_en0 cvmx_ciu_intx_en0_t; 1149 1150/** 1151 * cvmx_ciu_int#_en0_w1c 1152 * 1153 * Notes: 1154 * Write-1-to-clear version of the CIU_INTx_EN0 register 1155 * 1156 */ 1157union cvmx_ciu_intx_en0_w1c 1158{ 1159 uint64_t u64; 1160 struct cvmx_ciu_intx_en0_w1c_s 1161 { 1162#if __BYTE_ORDER == __BIG_ENDIAN 1163 uint64_t bootdma : 1; /**< Write 1 to clear Boot bus DMA engines Interrupt 1164 enable */ 1165 uint64_t mii : 1; /**< Write 1 to clr RGMII/MII/MIX Interface 0 Interrupt 1166 enable */ 1167 uint64_t ipdppthr : 1; /**< Write 1 to clear IPD per-port counter threshold 1168 interrupt enable */ 1169 uint64_t powiq : 1; /**< Write 1 to clear POW IQ interrupt */ 1170 uint64_t twsi2 : 1; /**< Write 1 to clear 2nd TWSI Interrupt */ 1171 uint64_t reserved_57_58 : 2; 1172 uint64_t usb : 1; /**< Write 1 to clear USB EHCI or OHCI Interrupt */ 1173 uint64_t timer : 4; /**< Write 1 to clear General timer interrupts */ 1174 uint64_t key_zero : 1; /**< Key Zeroization interrupt */ 1175 uint64_t ipd_drp : 1; /**< Write 1 to clear IPD QOS packet drop interrupt 1176 enable */ 1177 uint64_t gmx_drp : 2; /**< Write 1 to clear GMX packet drop interrupt enable */ 1178 uint64_t trace : 1; /**< Write 1 to clear Trace buffer interrupt enable */ 1179 uint64_t rml : 1; /**< Write 1 to clear RML Interrupt enable */ 1180 uint64_t twsi : 1; /**< Write 1 to clear TWSI Interrupt enable */ 1181 uint64_t reserved_44_44 : 1; 1182 uint64_t pci_msi : 4; /**< Write 1s to clear PCIe/sRIO MSI enables */ 1183 uint64_t pci_int : 4; /**< Write 1s to clear PCIe INTA/B/C/D enables */ 1184 uint64_t uart : 2; /**< Write 1s to clear UART interrupt enables */ 1185 uint64_t mbox : 2; /**< Write 1s to clear mailbox/PCIe/sRIO interrupt 1186 enables */ 1187 uint64_t gpio : 16; /**< Write 1s to clear GPIO interrupt enables */ 1188 uint64_t workq : 16; /**< Write 1s to clear work queue interrupt enables */ 1189#else 1190 uint64_t workq : 16; 1191 uint64_t gpio : 16; 1192 uint64_t mbox : 2; 1193 uint64_t uart : 2; 1194 uint64_t pci_int : 4; 1195 uint64_t pci_msi : 4; 1196 uint64_t reserved_44_44 : 1; 1197 uint64_t twsi : 1; 1198 uint64_t rml : 1; 1199 uint64_t trace : 1; 1200 uint64_t gmx_drp : 2; 1201 uint64_t ipd_drp : 1; 1202 uint64_t key_zero : 1; 1203 uint64_t timer : 4; 1204 uint64_t usb : 1; 1205 uint64_t reserved_57_58 : 2; 1206 uint64_t twsi2 : 1; 1207 uint64_t powiq : 1; 1208 uint64_t ipdppthr : 1; 1209 uint64_t mii : 1; 1210 uint64_t bootdma : 1; 1211#endif 1212 } s; 1213 struct cvmx_ciu_intx_en0_w1c_cn52xx 1214 { 1215#if __BYTE_ORDER == __BIG_ENDIAN 1216 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt */ 1217 uint64_t mii : 1; /**< MII Interface Interrupt */ 1218 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt */ 1219 uint64_t powiq : 1; /**< POW IQ interrupt */ 1220 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt */ 1221 uint64_t reserved_57_58 : 2; 1222 uint64_t usb : 1; /**< USB Interrupt */ 1223 uint64_t timer : 4; /**< General timer interrupts */ 1224 uint64_t reserved_51_51 : 1; 1225 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */ 1226 uint64_t reserved_49_49 : 1; 1227 uint64_t gmx_drp : 1; /**< GMX packet drop */ 1228 uint64_t trace : 1; /**< L2C has the CMB trace buffer */ 1229 uint64_t rml : 1; /**< RML Interrupt */ 1230 uint64_t twsi : 1; /**< TWSI Interrupt */ 1231 uint64_t reserved_44_44 : 1; 1232 uint64_t pci_msi : 4; /**< PCI MSI */ 1233 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */ 1234 uint64_t uart : 2; /**< Two UART interrupts */ 1235 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */ 1236 uint64_t gpio : 16; /**< 16 GPIO interrupts */ 1237 uint64_t workq : 16; /**< 16 work queue interrupts */ 1238#else 1239 uint64_t workq : 16; 1240 uint64_t gpio : 16; 1241 uint64_t mbox : 2; 1242 uint64_t uart : 2; 1243 uint64_t pci_int : 4; 1244 uint64_t pci_msi : 4; 1245 uint64_t reserved_44_44 : 1; 1246 uint64_t twsi : 1; 1247 uint64_t rml : 1; 1248 uint64_t trace : 1; 1249 uint64_t gmx_drp : 1; 1250 uint64_t reserved_49_49 : 1; 1251 uint64_t ipd_drp : 1; 1252 uint64_t reserved_51_51 : 1; 1253 uint64_t timer : 4; 1254 uint64_t usb : 1; 1255 uint64_t reserved_57_58 : 2; 1256 uint64_t twsi2 : 1; 1257 uint64_t powiq : 1; 1258 uint64_t ipdppthr : 1; 1259 uint64_t mii : 1; 1260 uint64_t bootdma : 1; 1261#endif 1262 } cn52xx; 1263 struct cvmx_ciu_intx_en0_w1c_s cn56xx; 1264 struct cvmx_ciu_intx_en0_w1c_cn58xx 1265 { 1266#if __BYTE_ORDER == __BIG_ENDIAN 1267 uint64_t reserved_56_63 : 8; 1268 uint64_t timer : 4; /**< General timer interrupts */ 1269 uint64_t key_zero : 1; /**< Key Zeroization interrupt */ 1270 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */ 1271 uint64_t gmx_drp : 2; /**< GMX packet drop */ 1272 uint64_t trace : 1; /**< L2C has the CMB trace buffer */ 1273 uint64_t rml : 1; /**< RML Interrupt */ 1274 uint64_t twsi : 1; /**< TWSI Interrupt */ 1275 uint64_t reserved_44_44 : 1; 1276 uint64_t pci_msi : 4; /**< PCI MSI */ 1277 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */ 1278 uint64_t uart : 2; /**< Two UART interrupts */ 1279 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */ 1280 uint64_t gpio : 16; /**< 16 GPIO interrupts */ 1281 uint64_t workq : 16; /**< 16 work queue interrupts */ 1282#else 1283 uint64_t workq : 16; 1284 uint64_t gpio : 16; 1285 uint64_t mbox : 2; 1286 uint64_t uart : 2; 1287 uint64_t pci_int : 4; 1288 uint64_t pci_msi : 4; 1289 uint64_t reserved_44_44 : 1; 1290 uint64_t twsi : 1; 1291 uint64_t rml : 1; 1292 uint64_t trace : 1; 1293 uint64_t gmx_drp : 2; 1294 uint64_t ipd_drp : 1; 1295 uint64_t key_zero : 1; 1296 uint64_t timer : 4; 1297 uint64_t reserved_56_63 : 8; 1298#endif 1299 } cn58xx; 1300 struct cvmx_ciu_intx_en0_w1c_cn52xx cn63xx; 1301 struct cvmx_ciu_intx_en0_w1c_cn52xx cn63xxp1; 1302}; 1303typedef union cvmx_ciu_intx_en0_w1c cvmx_ciu_intx_en0_w1c_t; 1304 1305/** 1306 * cvmx_ciu_int#_en0_w1s 1307 * 1308 * Notes: 1309 * Write-1-to-set version of the CIU_INTx_EN0 register 1310 * 1311 */ 1312union cvmx_ciu_intx_en0_w1s 1313{ 1314 uint64_t u64; 1315 struct cvmx_ciu_intx_en0_w1s_s 1316 { 1317#if __BYTE_ORDER == __BIG_ENDIAN 1318 uint64_t bootdma : 1; /**< Write 1 to set Boot bus DMA engines Interrupt 1319 enable */ 1320 uint64_t mii : 1; /**< Write 1 to set RGMII/MII/MIX Interface 0 Interrupt 1321 enable */ 1322 uint64_t ipdppthr : 1; /**< Write 1 to set IPD per-port counter threshold 1323 interrupt enable */ 1324 uint64_t powiq : 1; /**< Write 1 to set POW IQ interrupt */ 1325 uint64_t twsi2 : 1; /**< Write 1 to set 2nd TWSI Interrupt */ 1326 uint64_t reserved_57_58 : 2; 1327 uint64_t usb : 1; /**< Write 1 to set USB EHCI or OHCI Interrupt */ 1328 uint64_t timer : 4; /**< Write 1 to set General timer interrupts */ 1329 uint64_t key_zero : 1; /**< Key Zeroization interrupt */ 1330 uint64_t ipd_drp : 1; /**< Write 1 to set IPD QOS packet drop interrupt 1331 enable */ 1332 uint64_t gmx_drp : 2; /**< Write 1 to set GMX packet drop interrupt enable */ 1333 uint64_t trace : 1; /**< Write 1 to set Trace buffer interrupt enable */ 1334 uint64_t rml : 1; /**< Write 1 to set RML Interrupt enable */ 1335 uint64_t twsi : 1; /**< Write 1 to set TWSI Interrupt enable */ 1336 uint64_t reserved_44_44 : 1; 1337 uint64_t pci_msi : 4; /**< Write 1s to set PCIe/sRIO MSI enables */ 1338 uint64_t pci_int : 4; /**< Write 1s to set PCIe INTA/B/C/D enables */ 1339 uint64_t uart : 2; /**< Write 1s to set UART interrupt enables */ 1340 uint64_t mbox : 2; /**< Write 1s to set mailbox/PCIe/sRIO interrupt 1341 enables */ 1342 uint64_t gpio : 16; /**< Write 1s to set GPIO interrupt enables */ 1343 uint64_t workq : 16; /**< Write 1s to set work queue interrupt enables */ 1344#else 1345 uint64_t workq : 16; 1346 uint64_t gpio : 16; 1347 uint64_t mbox : 2; 1348 uint64_t uart : 2; 1349 uint64_t pci_int : 4; 1350 uint64_t pci_msi : 4; 1351 uint64_t reserved_44_44 : 1; 1352 uint64_t twsi : 1; 1353 uint64_t rml : 1; 1354 uint64_t trace : 1; 1355 uint64_t gmx_drp : 2; 1356 uint64_t ipd_drp : 1; 1357 uint64_t key_zero : 1; 1358 uint64_t timer : 4; 1359 uint64_t usb : 1; 1360 uint64_t reserved_57_58 : 2; 1361 uint64_t twsi2 : 1; 1362 uint64_t powiq : 1; 1363 uint64_t ipdppthr : 1; 1364 uint64_t mii : 1; 1365 uint64_t bootdma : 1; 1366#endif 1367 } s; 1368 struct cvmx_ciu_intx_en0_w1s_cn52xx 1369 { 1370#if __BYTE_ORDER == __BIG_ENDIAN 1371 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt */ 1372 uint64_t mii : 1; /**< MII Interface Interrupt */ 1373 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt */ 1374 uint64_t powiq : 1; /**< POW IQ interrupt */ 1375 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt */ 1376 uint64_t reserved_57_58 : 2; 1377 uint64_t usb : 1; /**< USB Interrupt */ 1378 uint64_t timer : 4; /**< General timer interrupts */ 1379 uint64_t reserved_51_51 : 1; 1380 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */ 1381 uint64_t reserved_49_49 : 1; 1382 uint64_t gmx_drp : 1; /**< GMX packet drop */ 1383 uint64_t trace : 1; /**< L2C has the CMB trace buffer */ 1384 uint64_t rml : 1; /**< RML Interrupt */ 1385 uint64_t twsi : 1; /**< TWSI Interrupt */ 1386 uint64_t reserved_44_44 : 1; 1387 uint64_t pci_msi : 4; /**< PCI MSI */ 1388 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */ 1389 uint64_t uart : 2; /**< Two UART interrupts */ 1390 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */ 1391 uint64_t gpio : 16; /**< 16 GPIO interrupts */ 1392 uint64_t workq : 16; /**< 16 work queue interrupts */ 1393#else 1394 uint64_t workq : 16; 1395 uint64_t gpio : 16; 1396 uint64_t mbox : 2; 1397 uint64_t uart : 2; 1398 uint64_t pci_int : 4; 1399 uint64_t pci_msi : 4; 1400 uint64_t reserved_44_44 : 1; 1401 uint64_t twsi : 1; 1402 uint64_t rml : 1; 1403 uint64_t trace : 1; 1404 uint64_t gmx_drp : 1; 1405 uint64_t reserved_49_49 : 1; 1406 uint64_t ipd_drp : 1; 1407 uint64_t reserved_51_51 : 1; 1408 uint64_t timer : 4; 1409 uint64_t usb : 1; 1410 uint64_t reserved_57_58 : 2; 1411 uint64_t twsi2 : 1; 1412 uint64_t powiq : 1; 1413 uint64_t ipdppthr : 1; 1414 uint64_t mii : 1; 1415 uint64_t bootdma : 1; 1416#endif 1417 } cn52xx; 1418 struct cvmx_ciu_intx_en0_w1s_s cn56xx; 1419 struct cvmx_ciu_intx_en0_w1s_cn58xx 1420 { 1421#if __BYTE_ORDER == __BIG_ENDIAN 1422 uint64_t reserved_56_63 : 8; 1423 uint64_t timer : 4; /**< General timer interrupts */ 1424 uint64_t key_zero : 1; /**< Key Zeroization interrupt */ 1425 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */ 1426 uint64_t gmx_drp : 2; /**< GMX packet drop */ 1427 uint64_t trace : 1; /**< L2C has the CMB trace buffer */ 1428 uint64_t rml : 1; /**< RML Interrupt */ 1429 uint64_t twsi : 1; /**< TWSI Interrupt */ 1430 uint64_t reserved_44_44 : 1; 1431 uint64_t pci_msi : 4; /**< PCI MSI */ 1432 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */ 1433 uint64_t uart : 2; /**< Two UART interrupts */ 1434 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */ 1435 uint64_t gpio : 16; /**< 16 GPIO interrupts */ 1436 uint64_t workq : 16; /**< 16 work queue interrupts */ 1437#else 1438 uint64_t workq : 16; 1439 uint64_t gpio : 16; 1440 uint64_t mbox : 2; 1441 uint64_t uart : 2; 1442 uint64_t pci_int : 4; 1443 uint64_t pci_msi : 4; 1444 uint64_t reserved_44_44 : 1; 1445 uint64_t twsi : 1; 1446 uint64_t rml : 1; 1447 uint64_t trace : 1; 1448 uint64_t gmx_drp : 2; 1449 uint64_t ipd_drp : 1; 1450 uint64_t key_zero : 1; 1451 uint64_t timer : 4; 1452 uint64_t reserved_56_63 : 8; 1453#endif 1454 } cn58xx; 1455 struct cvmx_ciu_intx_en0_w1s_cn52xx cn63xx; 1456 struct cvmx_ciu_intx_en0_w1s_cn52xx cn63xxp1; 1457}; 1458typedef union cvmx_ciu_intx_en0_w1s cvmx_ciu_intx_en0_w1s_t; 1459 1460/** 1461 * cvmx_ciu_int#_en1 1462 * 1463 * Notes: 1464 * @verbatim 1465 * PPx/IP2 will be raised when... 1466 * 1467 * n = x*2 1468 * PPx/IP2 = |([CIU_INT_SUM1, CIU_INTn_SUM0] & [CIU_INTn_EN1, CIU_INTn_EN0]) 1469 * 1470 * PPx/IP3 will be raised when... 1471 * 1472 * n = x*2 + 1 1473 * PPx/IP3 = |([CIU_INT_SUM1, CIU_INTn_SUM0] & [CIU_INTn_EN1, CIU_INTn_EN0]) 1474 * 1475 * PCI/INT will be raised when... 1476 * 1477 * PCI/INT = |([CIU_INT_SUM1, CIU_INT32_SUM0] & [CIU_INT32_EN1, CIU_INT32_EN0]) 1478 * @endverbatim 1479 */ 1480union cvmx_ciu_intx_en1 1481{ 1482 uint64_t u64; 1483 struct cvmx_ciu_intx_en1_s 1484 { 1485#if __BYTE_ORDER == __BIG_ENDIAN 1486 uint64_t rst : 1; /**< MIO RST interrupt enable */ 1487 uint64_t reserved_57_62 : 6; 1488 uint64_t dfm : 1; /**< DFM interrupt enable */ 1489 uint64_t reserved_53_55 : 3; 1490 uint64_t lmc0 : 1; /**< LMC0 interrupt enable */ 1491 uint64_t srio1 : 1; /**< SRIO1 interrupt enable */ 1492 uint64_t srio0 : 1; /**< SRIO0 interrupt enable */ 1493 uint64_t pem1 : 1; /**< PEM1 interrupt enable */ 1494 uint64_t pem0 : 1; /**< PEM0 interrupt enable */ 1495 uint64_t ptp : 1; /**< PTP interrupt enable */ 1496 uint64_t agl : 1; /**< AGL interrupt enable */ 1497 uint64_t reserved_37_45 : 9; 1498 uint64_t agx0 : 1; /**< GMX0 interrupt enable */ 1499 uint64_t dpi : 1; /**< DPI interrupt enable */ 1500 uint64_t sli : 1; /**< SLI interrupt enable */ 1501 uint64_t usb : 1; /**< USB UCTL0 interrupt enable */ 1502 uint64_t dfa : 1; /**< DFA interrupt enable */ 1503 uint64_t key : 1; /**< KEY interrupt enable */ 1504 uint64_t rad : 1; /**< RAD interrupt enable */ 1505 uint64_t tim : 1; /**< TIM interrupt enable */ 1506 uint64_t zip : 1; /**< ZIP interrupt enable */ 1507 uint64_t pko : 1; /**< PKO interrupt enable */ 1508 uint64_t pip : 1; /**< PIP interrupt enable */ 1509 uint64_t ipd : 1; /**< IPD interrupt enable */ 1510 uint64_t l2c : 1; /**< L2C interrupt enable */ 1511 uint64_t pow : 1; /**< POW err interrupt enable */ 1512 uint64_t fpa : 1; /**< FPA interrupt enable */ 1513 uint64_t iob : 1; /**< IOB interrupt enable */ 1514 uint64_t mio : 1; /**< MIO boot interrupt enable */ 1515 uint64_t nand : 1; /**< NAND Flash Controller interrupt enable */ 1516 uint64_t mii1 : 1; /**< RGMII/MII/MIX Interface 1 Interrupt enable */ 1517 uint64_t usb1 : 1; /**< Second USB Interrupt */ 1518 uint64_t uart2 : 1; /**< Third UART interrupt */ 1519 uint64_t wdog : 16; /**< Watchdog summary interrupt enable vector */ 1520#else 1521 uint64_t wdog : 16; 1522 uint64_t uart2 : 1; 1523 uint64_t usb1 : 1; 1524 uint64_t mii1 : 1; 1525 uint64_t nand : 1; 1526 uint64_t mio : 1; 1527 uint64_t iob : 1; 1528 uint64_t fpa : 1; 1529 uint64_t pow : 1; 1530 uint64_t l2c : 1; 1531 uint64_t ipd : 1; 1532 uint64_t pip : 1; 1533 uint64_t pko : 1; 1534 uint64_t zip : 1; 1535 uint64_t tim : 1; 1536 uint64_t rad : 1; 1537 uint64_t key : 1; 1538 uint64_t dfa : 1; 1539 uint64_t usb : 1; 1540 uint64_t sli : 1; 1541 uint64_t dpi : 1; 1542 uint64_t agx0 : 1; 1543 uint64_t reserved_37_45 : 9; 1544 uint64_t agl : 1; 1545 uint64_t ptp : 1; 1546 uint64_t pem0 : 1; 1547 uint64_t pem1 : 1; 1548 uint64_t srio0 : 1; 1549 uint64_t srio1 : 1; 1550 uint64_t lmc0 : 1; 1551 uint64_t reserved_53_55 : 3; 1552 uint64_t dfm : 1; 1553 uint64_t reserved_57_62 : 6; 1554 uint64_t rst : 1; 1555#endif 1556 } s; 1557 struct cvmx_ciu_intx_en1_cn30xx 1558 { 1559#if __BYTE_ORDER == __BIG_ENDIAN 1560 uint64_t reserved_1_63 : 63; 1561 uint64_t wdog : 1; /**< Watchdog summary interrupt enable vector */ 1562#else 1563 uint64_t wdog : 1; 1564 uint64_t reserved_1_63 : 63; 1565#endif 1566 } cn30xx; 1567 struct cvmx_ciu_intx_en1_cn31xx 1568 { 1569#if __BYTE_ORDER == __BIG_ENDIAN 1570 uint64_t reserved_2_63 : 62; 1571 uint64_t wdog : 2; /**< Watchdog summary interrupt enable vectory */ 1572#else 1573 uint64_t wdog : 2; 1574 uint64_t reserved_2_63 : 62; 1575#endif 1576 } cn31xx; 1577 struct cvmx_ciu_intx_en1_cn38xx 1578 { 1579#if __BYTE_ORDER == __BIG_ENDIAN 1580 uint64_t reserved_16_63 : 48; 1581 uint64_t wdog : 16; /**< Watchdog summary interrupt enable vectory */ 1582#else 1583 uint64_t wdog : 16; 1584 uint64_t reserved_16_63 : 48; 1585#endif 1586 } cn38xx; 1587 struct cvmx_ciu_intx_en1_cn38xx cn38xxp2; 1588 struct cvmx_ciu_intx_en1_cn31xx cn50xx; 1589 struct cvmx_ciu_intx_en1_cn52xx 1590 { 1591#if __BYTE_ORDER == __BIG_ENDIAN 1592 uint64_t reserved_20_63 : 44; 1593 uint64_t nand : 1; /**< NAND Flash Controller */ 1594 uint64_t mii1 : 1; /**< Second MII Interrupt */ 1595 uint64_t usb1 : 1; /**< Second USB Interrupt */ 1596 uint64_t uart2 : 1; /**< Third UART interrupt */ 1597 uint64_t reserved_4_15 : 12; 1598 uint64_t wdog : 4; /**< Watchdog summary interrupt enable vector */ 1599#else 1600 uint64_t wdog : 4; 1601 uint64_t reserved_4_15 : 12; 1602 uint64_t uart2 : 1; 1603 uint64_t usb1 : 1; 1604 uint64_t mii1 : 1; 1605 uint64_t nand : 1; 1606 uint64_t reserved_20_63 : 44; 1607#endif 1608 } cn52xx; 1609 struct cvmx_ciu_intx_en1_cn52xxp1 1610 { 1611#if __BYTE_ORDER == __BIG_ENDIAN 1612 uint64_t reserved_19_63 : 45; 1613 uint64_t mii1 : 1; /**< Second MII Interrupt */ 1614 uint64_t usb1 : 1; /**< Second USB Interrupt */ 1615 uint64_t uart2 : 1; /**< Third UART interrupt */ 1616 uint64_t reserved_4_15 : 12; 1617 uint64_t wdog : 4; /**< Watchdog summary interrupt enable vector */ 1618#else 1619 uint64_t wdog : 4; 1620 uint64_t reserved_4_15 : 12; 1621 uint64_t uart2 : 1; 1622 uint64_t usb1 : 1; 1623 uint64_t mii1 : 1; 1624 uint64_t reserved_19_63 : 45; 1625#endif 1626 } cn52xxp1; 1627 struct cvmx_ciu_intx_en1_cn56xx 1628 { 1629#if __BYTE_ORDER == __BIG_ENDIAN 1630 uint64_t reserved_12_63 : 52; 1631 uint64_t wdog : 12; /**< Watchdog summary interrupt enable vectory */ 1632#else 1633 uint64_t wdog : 12; 1634 uint64_t reserved_12_63 : 52; 1635#endif 1636 } cn56xx; 1637 struct cvmx_ciu_intx_en1_cn56xx cn56xxp1; 1638 struct cvmx_ciu_intx_en1_cn38xx cn58xx; 1639 struct cvmx_ciu_intx_en1_cn38xx cn58xxp1; 1640 struct cvmx_ciu_intx_en1_cn63xx 1641 { 1642#if __BYTE_ORDER == __BIG_ENDIAN 1643 uint64_t rst : 1; /**< MIO RST interrupt enable */ 1644 uint64_t reserved_57_62 : 6; 1645 uint64_t dfm : 1; /**< DFM interrupt enable */ 1646 uint64_t reserved_53_55 : 3; 1647 uint64_t lmc0 : 1; /**< LMC0 interrupt enable */ 1648 uint64_t srio1 : 1; /**< SRIO1 interrupt enable */ 1649 uint64_t srio0 : 1; /**< SRIO0 interrupt enable */ 1650 uint64_t pem1 : 1; /**< PEM1 interrupt enable */ 1651 uint64_t pem0 : 1; /**< PEM0 interrupt enable */ 1652 uint64_t ptp : 1; /**< PTP interrupt enable */ 1653 uint64_t agl : 1; /**< AGL interrupt enable */ 1654 uint64_t reserved_37_45 : 9; 1655 uint64_t agx0 : 1; /**< GMX0 interrupt enable */ 1656 uint64_t dpi : 1; /**< DPI interrupt enable */ 1657 uint64_t sli : 1; /**< SLI interrupt enable */ 1658 uint64_t usb : 1; /**< USB UCTL0 interrupt enable */ 1659 uint64_t dfa : 1; /**< DFA interrupt enable */ 1660 uint64_t key : 1; /**< KEY interrupt enable */ 1661 uint64_t rad : 1; /**< RAD interrupt enable */ 1662 uint64_t tim : 1; /**< TIM interrupt enable */ 1663 uint64_t zip : 1; /**< ZIP interrupt enable */ 1664 uint64_t pko : 1; /**< PKO interrupt enable */ 1665 uint64_t pip : 1; /**< PIP interrupt enable */ 1666 uint64_t ipd : 1; /**< IPD interrupt enable */ 1667 uint64_t l2c : 1; /**< L2C interrupt enable */ 1668 uint64_t pow : 1; /**< POW err interrupt enable */ 1669 uint64_t fpa : 1; /**< FPA interrupt enable */ 1670 uint64_t iob : 1; /**< IOB interrupt enable */ 1671 uint64_t mio : 1; /**< MIO boot interrupt enable */ 1672 uint64_t nand : 1; /**< NAND Flash Controller interrupt enable */ 1673 uint64_t mii1 : 1; /**< RGMII/MII/MIX Interface 1 Interrupt enable */ 1674 uint64_t reserved_6_17 : 12; 1675 uint64_t wdog : 6; /**< Watchdog summary interrupt enable vector */ 1676#else 1677 uint64_t wdog : 6; 1678 uint64_t reserved_6_17 : 12; 1679 uint64_t mii1 : 1; 1680 uint64_t nand : 1; 1681 uint64_t mio : 1; 1682 uint64_t iob : 1; 1683 uint64_t fpa : 1; 1684 uint64_t pow : 1; 1685 uint64_t l2c : 1; 1686 uint64_t ipd : 1; 1687 uint64_t pip : 1; 1688 uint64_t pko : 1; 1689 uint64_t zip : 1; 1690 uint64_t tim : 1; 1691 uint64_t rad : 1; 1692 uint64_t key : 1; 1693 uint64_t dfa : 1; 1694 uint64_t usb : 1; 1695 uint64_t sli : 1; 1696 uint64_t dpi : 1; 1697 uint64_t agx0 : 1; 1698 uint64_t reserved_37_45 : 9; 1699 uint64_t agl : 1; 1700 uint64_t ptp : 1; 1701 uint64_t pem0 : 1; 1702 uint64_t pem1 : 1; 1703 uint64_t srio0 : 1; 1704 uint64_t srio1 : 1; 1705 uint64_t lmc0 : 1; 1706 uint64_t reserved_53_55 : 3; 1707 uint64_t dfm : 1; 1708 uint64_t reserved_57_62 : 6; 1709 uint64_t rst : 1; 1710#endif 1711 } cn63xx; 1712 struct cvmx_ciu_intx_en1_cn63xx cn63xxp1; 1713}; 1714typedef union cvmx_ciu_intx_en1 cvmx_ciu_intx_en1_t; 1715 1716/** 1717 * cvmx_ciu_int#_en1_w1c 1718 * 1719 * Notes: 1720 * Write-1-to-clear version of the CIU_INTx_EN1 register 1721 * 1722 */ 1723union cvmx_ciu_intx_en1_w1c 1724{ 1725 uint64_t u64; 1726 struct cvmx_ciu_intx_en1_w1c_s 1727 { 1728#if __BYTE_ORDER == __BIG_ENDIAN 1729 uint64_t rst : 1; /**< Write 1 to clear MIO RST interrupt enable */ 1730 uint64_t reserved_57_62 : 6; 1731 uint64_t dfm : 1; /**< Write 1 to clear DFM interrupt enable */ 1732 uint64_t reserved_53_55 : 3; 1733 uint64_t lmc0 : 1; /**< Write 1 to clear LMC0 interrupt enable */ 1734 uint64_t srio1 : 1; /**< Write 1 to clear SRIO1 interrupt enable */ 1735 uint64_t srio0 : 1; /**< Write 1 to clear SRIO0 interrupt enable */ 1736 uint64_t pem1 : 1; /**< Write 1 to clear PEM1 interrupt enable */ 1737 uint64_t pem0 : 1; /**< Write 1 to clear PEM0 interrupt enable */ 1738 uint64_t ptp : 1; /**< Write 1 to clear PTP interrupt enable */ 1739 uint64_t agl : 1; /**< Write 1 to clear AGL interrupt enable */ 1740 uint64_t reserved_37_45 : 9; 1741 uint64_t agx0 : 1; /**< Write 1 to clear GMX0 interrupt enable */ 1742 uint64_t dpi : 1; /**< Write 1 to clear DPI interrupt enable */ 1743 uint64_t sli : 1; /**< Write 1 to clear SLI interrupt enable */ 1744 uint64_t usb : 1; /**< Write 1 to clear USB UCTL0 interrupt enable */ 1745 uint64_t dfa : 1; /**< Write 1 to clear DFA interrupt enable */ 1746 uint64_t key : 1; /**< Write 1 to clear KEY interrupt enable */ 1747 uint64_t rad : 1; /**< Write 1 to clear RAD interrupt enable */ 1748 uint64_t tim : 1; /**< Write 1 to clear TIM interrupt enable */ 1749 uint64_t zip : 1; /**< Write 1 to clear ZIP interrupt enable */ 1750 uint64_t pko : 1; /**< Write 1 to clear PKO interrupt enable */ 1751 uint64_t pip : 1; /**< Write 1 to clear PIP interrupt enable */ 1752 uint64_t ipd : 1; /**< Write 1 to clear IPD interrupt enable */ 1753 uint64_t l2c : 1; /**< Write 1 to clear L2C interrupt enable */ 1754 uint64_t pow : 1; /**< Write 1 to clear POW err interrupt enable */ 1755 uint64_t fpa : 1; /**< Write 1 to clear FPA interrupt enable */ 1756 uint64_t iob : 1; /**< Write 1 to clear IOB interrupt enable */ 1757 uint64_t mio : 1; /**< Write 1 to clear MIO boot interrupt enable */ 1758 uint64_t nand : 1; /**< Write 1 to clear NAND Flash Controller interrupt 1759 enable */ 1760 uint64_t mii1 : 1; /**< Write 1 to clear RGMII/MII/MIX Interface 1 1761 Interrupt enable */ 1762 uint64_t usb1 : 1; /**< Second USB Interrupt */ 1763 uint64_t uart2 : 1; /**< Third UART interrupt */ 1764 uint64_t wdog : 16; /**< Write 1s to clear Watchdog summary interrupt enable */ 1765#else 1766 uint64_t wdog : 16; 1767 uint64_t uart2 : 1; 1768 uint64_t usb1 : 1; 1769 uint64_t mii1 : 1; 1770 uint64_t nand : 1; 1771 uint64_t mio : 1; 1772 uint64_t iob : 1; 1773 uint64_t fpa : 1; 1774 uint64_t pow : 1; 1775 uint64_t l2c : 1; 1776 uint64_t ipd : 1; 1777 uint64_t pip : 1; 1778 uint64_t pko : 1; 1779 uint64_t zip : 1; 1780 uint64_t tim : 1; 1781 uint64_t rad : 1; 1782 uint64_t key : 1; 1783 uint64_t dfa : 1; 1784 uint64_t usb : 1; 1785 uint64_t sli : 1; 1786 uint64_t dpi : 1; 1787 uint64_t agx0 : 1; 1788 uint64_t reserved_37_45 : 9; 1789 uint64_t agl : 1; 1790 uint64_t ptp : 1; 1791 uint64_t pem0 : 1; 1792 uint64_t pem1 : 1; 1793 uint64_t srio0 : 1; 1794 uint64_t srio1 : 1; 1795 uint64_t lmc0 : 1; 1796 uint64_t reserved_53_55 : 3; 1797 uint64_t dfm : 1; 1798 uint64_t reserved_57_62 : 6; 1799 uint64_t rst : 1; 1800#endif 1801 } s; 1802 struct cvmx_ciu_intx_en1_w1c_cn52xx 1803 { 1804#if __BYTE_ORDER == __BIG_ENDIAN 1805 uint64_t reserved_20_63 : 44; 1806 uint64_t nand : 1; /**< NAND Flash Controller */ 1807 uint64_t mii1 : 1; /**< Second MII Interrupt */ 1808 uint64_t usb1 : 1; /**< Second USB Interrupt */ 1809 uint64_t uart2 : 1; /**< Third UART interrupt */ 1810 uint64_t reserved_4_15 : 12; 1811 uint64_t wdog : 4; /**< Watchdog summary interrupt enable vector */ 1812#else 1813 uint64_t wdog : 4; 1814 uint64_t reserved_4_15 : 12; 1815 uint64_t uart2 : 1; 1816 uint64_t usb1 : 1; 1817 uint64_t mii1 : 1; 1818 uint64_t nand : 1; 1819 uint64_t reserved_20_63 : 44; 1820#endif 1821 } cn52xx; 1822 struct cvmx_ciu_intx_en1_w1c_cn56xx 1823 { 1824#if __BYTE_ORDER == __BIG_ENDIAN 1825 uint64_t reserved_12_63 : 52; 1826 uint64_t wdog : 12; /**< Watchdog summary interrupt enable vectory */ 1827#else 1828 uint64_t wdog : 12; 1829 uint64_t reserved_12_63 : 52; 1830#endif 1831 } cn56xx; 1832 struct cvmx_ciu_intx_en1_w1c_cn58xx 1833 { 1834#if __BYTE_ORDER == __BIG_ENDIAN 1835 uint64_t reserved_16_63 : 48; 1836 uint64_t wdog : 16; /**< Watchdog summary interrupt enable vectory */ 1837#else 1838 uint64_t wdog : 16; 1839 uint64_t reserved_16_63 : 48; 1840#endif 1841 } cn58xx; 1842 struct cvmx_ciu_intx_en1_w1c_cn63xx 1843 { 1844#if __BYTE_ORDER == __BIG_ENDIAN 1845 uint64_t rst : 1; /**< Write 1 to clear MIO RST interrupt enable */ 1846 uint64_t reserved_57_62 : 6; 1847 uint64_t dfm : 1; /**< Write 1 to clear DFM interrupt enable */ 1848 uint64_t reserved_53_55 : 3; 1849 uint64_t lmc0 : 1; /**< Write 1 to clear LMC0 interrupt enable */ 1850 uint64_t srio1 : 1; /**< Write 1 to clear SRIO1 interrupt enable */ 1851 uint64_t srio0 : 1; /**< Write 1 to clear SRIO0 interrupt enable */ 1852 uint64_t pem1 : 1; /**< Write 1 to clear PEM1 interrupt enable */ 1853 uint64_t pem0 : 1; /**< Write 1 to clear PEM0 interrupt enable */ 1854 uint64_t ptp : 1; /**< Write 1 to clear PTP interrupt enable */ 1855 uint64_t agl : 1; /**< Write 1 to clear AGL interrupt enable */ 1856 uint64_t reserved_37_45 : 9; 1857 uint64_t agx0 : 1; /**< Write 1 to clear GMX0 interrupt enable */ 1858 uint64_t dpi : 1; /**< Write 1 to clear DPI interrupt enable */ 1859 uint64_t sli : 1; /**< Write 1 to clear SLI interrupt enable */ 1860 uint64_t usb : 1; /**< Write 1 to clear USB UCTL0 interrupt enable */ 1861 uint64_t dfa : 1; /**< Write 1 to clear DFA interrupt enable */ 1862 uint64_t key : 1; /**< Write 1 to clear KEY interrupt enable */ 1863 uint64_t rad : 1; /**< Write 1 to clear RAD interrupt enable */ 1864 uint64_t tim : 1; /**< Write 1 to clear TIM interrupt enable */ 1865 uint64_t zip : 1; /**< Write 1 to clear ZIP interrupt enable */ 1866 uint64_t pko : 1; /**< Write 1 to clear PKO interrupt enable */ 1867 uint64_t pip : 1; /**< Write 1 to clear PIP interrupt enable */ 1868 uint64_t ipd : 1; /**< Write 1 to clear IPD interrupt enable */ 1869 uint64_t l2c : 1; /**< Write 1 to clear L2C interrupt enable */ 1870 uint64_t pow : 1; /**< Write 1 to clear POW err interrupt enable */ 1871 uint64_t fpa : 1; /**< Write 1 to clear FPA interrupt enable */ 1872 uint64_t iob : 1; /**< Write 1 to clear IOB interrupt enable */ 1873 uint64_t mio : 1; /**< Write 1 to clear MIO boot interrupt enable */ 1874 uint64_t nand : 1; /**< Write 1 to clear NAND Flash Controller interrupt 1875 enable */ 1876 uint64_t mii1 : 1; /**< Write 1 to clear RGMII/MII/MIX Interface 1 1877 Interrupt enable */ 1878 uint64_t reserved_6_17 : 12; 1879 uint64_t wdog : 6; /**< Write 1s to clear Watchdog summary interrupt enable */ 1880#else 1881 uint64_t wdog : 6; 1882 uint64_t reserved_6_17 : 12; 1883 uint64_t mii1 : 1; 1884 uint64_t nand : 1; 1885 uint64_t mio : 1; 1886 uint64_t iob : 1; 1887 uint64_t fpa : 1; 1888 uint64_t pow : 1; 1889 uint64_t l2c : 1; 1890 uint64_t ipd : 1; 1891 uint64_t pip : 1; 1892 uint64_t pko : 1; 1893 uint64_t zip : 1; 1894 uint64_t tim : 1; 1895 uint64_t rad : 1; 1896 uint64_t key : 1; 1897 uint64_t dfa : 1; 1898 uint64_t usb : 1; 1899 uint64_t sli : 1; 1900 uint64_t dpi : 1; 1901 uint64_t agx0 : 1; 1902 uint64_t reserved_37_45 : 9; 1903 uint64_t agl : 1; 1904 uint64_t ptp : 1; 1905 uint64_t pem0 : 1; 1906 uint64_t pem1 : 1; 1907 uint64_t srio0 : 1; 1908 uint64_t srio1 : 1; 1909 uint64_t lmc0 : 1; 1910 uint64_t reserved_53_55 : 3; 1911 uint64_t dfm : 1; 1912 uint64_t reserved_57_62 : 6; 1913 uint64_t rst : 1; 1914#endif 1915 } cn63xx; 1916 struct cvmx_ciu_intx_en1_w1c_cn63xx cn63xxp1; 1917}; 1918typedef union cvmx_ciu_intx_en1_w1c cvmx_ciu_intx_en1_w1c_t; 1919 1920/** 1921 * cvmx_ciu_int#_en1_w1s 1922 * 1923 * Notes: 1924 * Write-1-to-set version of the CIU_INTx_EN1 register 1925 * 1926 */ 1927union cvmx_ciu_intx_en1_w1s 1928{ 1929 uint64_t u64; 1930 struct cvmx_ciu_intx_en1_w1s_s 1931 { 1932#if __BYTE_ORDER == __BIG_ENDIAN 1933 uint64_t rst : 1; /**< Write 1 to set MIO RST interrupt enable */ 1934 uint64_t reserved_57_62 : 6; 1935 uint64_t dfm : 1; /**< Write 1 to set DFM interrupt enable */ 1936 uint64_t reserved_53_55 : 3; 1937 uint64_t lmc0 : 1; /**< Write 1 to set LMC0 interrupt enable */ 1938 uint64_t srio1 : 1; /**< Write 1 to set SRIO1 interrupt enable */ 1939 uint64_t srio0 : 1; /**< Write 1 to set SRIO0 interrupt enable */ 1940 uint64_t pem1 : 1; /**< Write 1 to set PEM1 interrupt enable */ 1941 uint64_t pem0 : 1; /**< Write 1 to set PEM0 interrupt enable */ 1942 uint64_t ptp : 1; /**< Write 1 to set PTP interrupt enable */ 1943 uint64_t agl : 1; /**< Write 1 to set AGL interrupt enable */ 1944 uint64_t reserved_37_45 : 9; 1945 uint64_t agx0 : 1; /**< Write 1 to set GMX0 interrupt enable */ 1946 uint64_t dpi : 1; /**< Write 1 to set DPI interrupt enable */ 1947 uint64_t sli : 1; /**< Write 1 to set SLI interrupt enable */ 1948 uint64_t usb : 1; /**< Write 1 to set USB UCTL0 interrupt enable */ 1949 uint64_t dfa : 1; /**< Write 1 to set DFA interrupt enable */ 1950 uint64_t key : 1; /**< Write 1 to set KEY interrupt enable */ 1951 uint64_t rad : 1; /**< Write 1 to set RAD interrupt enable */ 1952 uint64_t tim : 1; /**< Write 1 to set TIM interrupt enable */ 1953 uint64_t zip : 1; /**< Write 1 to set ZIP interrupt enable */ 1954 uint64_t pko : 1; /**< Write 1 to set PKO interrupt enable */ 1955 uint64_t pip : 1; /**< Write 1 to set PIP interrupt enable */ 1956 uint64_t ipd : 1; /**< Write 1 to set IPD interrupt enable */ 1957 uint64_t l2c : 1; /**< Write 1 to set L2C interrupt enable */ 1958 uint64_t pow : 1; /**< Write 1 to set POW err interrupt enable */ 1959 uint64_t fpa : 1; /**< Write 1 to set FPA interrupt enable */ 1960 uint64_t iob : 1; /**< Write 1 to set IOB interrupt enable */ 1961 uint64_t mio : 1; /**< Write 1 to set MIO boot interrupt enable */ 1962 uint64_t nand : 1; /**< Write 1 to set NAND Flash Controller interrupt 1963 enable */ 1964 uint64_t mii1 : 1; /**< Write 1 to set RGMII/MII/MIX Interface 1 Interrupt 1965 enable */ 1966 uint64_t usb1 : 1; /**< Second USB Interrupt */ 1967 uint64_t uart2 : 1; /**< Third UART interrupt */ 1968 uint64_t wdog : 16; /**< Write 1s to set Watchdog summary interrupt enable */ 1969#else 1970 uint64_t wdog : 16; 1971 uint64_t uart2 : 1; 1972 uint64_t usb1 : 1; 1973 uint64_t mii1 : 1; 1974 uint64_t nand : 1; 1975 uint64_t mio : 1; 1976 uint64_t iob : 1; 1977 uint64_t fpa : 1; 1978 uint64_t pow : 1; 1979 uint64_t l2c : 1; 1980 uint64_t ipd : 1; 1981 uint64_t pip : 1; 1982 uint64_t pko : 1; 1983 uint64_t zip : 1; 1984 uint64_t tim : 1; 1985 uint64_t rad : 1; 1986 uint64_t key : 1; 1987 uint64_t dfa : 1; 1988 uint64_t usb : 1; 1989 uint64_t sli : 1; 1990 uint64_t dpi : 1; 1991 uint64_t agx0 : 1; 1992 uint64_t reserved_37_45 : 9; 1993 uint64_t agl : 1; 1994 uint64_t ptp : 1; 1995 uint64_t pem0 : 1; 1996 uint64_t pem1 : 1; 1997 uint64_t srio0 : 1; 1998 uint64_t srio1 : 1; 1999 uint64_t lmc0 : 1; 2000 uint64_t reserved_53_55 : 3; 2001 uint64_t dfm : 1; 2002 uint64_t reserved_57_62 : 6; 2003 uint64_t rst : 1; 2004#endif 2005 } s; 2006 struct cvmx_ciu_intx_en1_w1s_cn52xx 2007 { 2008#if __BYTE_ORDER == __BIG_ENDIAN 2009 uint64_t reserved_20_63 : 44; 2010 uint64_t nand : 1; /**< NAND Flash Controller */ 2011 uint64_t mii1 : 1; /**< Second MII Interrupt */ 2012 uint64_t usb1 : 1; /**< Second USB Interrupt */ 2013 uint64_t uart2 : 1; /**< Third UART interrupt */ 2014 uint64_t reserved_4_15 : 12; 2015 uint64_t wdog : 4; /**< Watchdog summary interrupt enable vector */ 2016#else 2017 uint64_t wdog : 4; 2018 uint64_t reserved_4_15 : 12; 2019 uint64_t uart2 : 1; 2020 uint64_t usb1 : 1; 2021 uint64_t mii1 : 1; 2022 uint64_t nand : 1; 2023 uint64_t reserved_20_63 : 44; 2024#endif 2025 } cn52xx; 2026 struct cvmx_ciu_intx_en1_w1s_cn56xx 2027 { 2028#if __BYTE_ORDER == __BIG_ENDIAN 2029 uint64_t reserved_12_63 : 52; 2030 uint64_t wdog : 12; /**< Watchdog summary interrupt enable vectory */ 2031#else 2032 uint64_t wdog : 12; 2033 uint64_t reserved_12_63 : 52; 2034#endif 2035 } cn56xx; 2036 struct cvmx_ciu_intx_en1_w1s_cn58xx 2037 { 2038#if __BYTE_ORDER == __BIG_ENDIAN 2039 uint64_t reserved_16_63 : 48; 2040 uint64_t wdog : 16; /**< Watchdog summary interrupt enable vectory */ 2041#else 2042 uint64_t wdog : 16; 2043 uint64_t reserved_16_63 : 48; 2044#endif 2045 } cn58xx; 2046 struct cvmx_ciu_intx_en1_w1s_cn63xx 2047 { 2048#if __BYTE_ORDER == __BIG_ENDIAN 2049 uint64_t rst : 1; /**< Write 1 to set MIO RST interrupt enable */ 2050 uint64_t reserved_57_62 : 6; 2051 uint64_t dfm : 1; /**< Write 1 to set DFM interrupt enable */ 2052 uint64_t reserved_53_55 : 3; 2053 uint64_t lmc0 : 1; /**< Write 1 to set LMC0 interrupt enable */ 2054 uint64_t srio1 : 1; /**< Write 1 to set SRIO1 interrupt enable */ 2055 uint64_t srio0 : 1; /**< Write 1 to set SRIO0 interrupt enable */ 2056 uint64_t pem1 : 1; /**< Write 1 to set PEM1 interrupt enable */ 2057 uint64_t pem0 : 1; /**< Write 1 to set PEM0 interrupt enable */ 2058 uint64_t ptp : 1; /**< Write 1 to set PTP interrupt enable */ 2059 uint64_t agl : 1; /**< Write 1 to set AGL interrupt enable */ 2060 uint64_t reserved_37_45 : 9; 2061 uint64_t agx0 : 1; /**< Write 1 to set GMX0 interrupt enable */ 2062 uint64_t dpi : 1; /**< Write 1 to set DPI interrupt enable */ 2063 uint64_t sli : 1; /**< Write 1 to set SLI interrupt enable */ 2064 uint64_t usb : 1; /**< Write 1 to set USB UCTL0 interrupt enable */ 2065 uint64_t dfa : 1; /**< Write 1 to set DFA interrupt enable */ 2066 uint64_t key : 1; /**< Write 1 to set KEY interrupt enable */ 2067 uint64_t rad : 1; /**< Write 1 to set RAD interrupt enable */ 2068 uint64_t tim : 1; /**< Write 1 to set TIM interrupt enable */ 2069 uint64_t zip : 1; /**< Write 1 to set ZIP interrupt enable */ 2070 uint64_t pko : 1; /**< Write 1 to set PKO interrupt enable */ 2071 uint64_t pip : 1; /**< Write 1 to set PIP interrupt enable */ 2072 uint64_t ipd : 1; /**< Write 1 to set IPD interrupt enable */ 2073 uint64_t l2c : 1; /**< Write 1 to set L2C interrupt enable */ 2074 uint64_t pow : 1; /**< Write 1 to set POW err interrupt enable */ 2075 uint64_t fpa : 1; /**< Write 1 to set FPA interrupt enable */ 2076 uint64_t iob : 1; /**< Write 1 to set IOB interrupt enable */ 2077 uint64_t mio : 1; /**< Write 1 to set MIO boot interrupt enable */ 2078 uint64_t nand : 1; /**< Write 1 to set NAND Flash Controller interrupt 2079 enable */ 2080 uint64_t mii1 : 1; /**< Write 1 to set RGMII/MII/MIX Interface 1 Interrupt 2081 enable */ 2082 uint64_t reserved_6_17 : 12; 2083 uint64_t wdog : 6; /**< Write 1s to set Watchdog summary interrupt enable */ 2084#else 2085 uint64_t wdog : 6; 2086 uint64_t reserved_6_17 : 12; 2087 uint64_t mii1 : 1; 2088 uint64_t nand : 1; 2089 uint64_t mio : 1; 2090 uint64_t iob : 1; 2091 uint64_t fpa : 1; 2092 uint64_t pow : 1; 2093 uint64_t l2c : 1; 2094 uint64_t ipd : 1; 2095 uint64_t pip : 1; 2096 uint64_t pko : 1; 2097 uint64_t zip : 1; 2098 uint64_t tim : 1; 2099 uint64_t rad : 1; 2100 uint64_t key : 1; 2101 uint64_t dfa : 1; 2102 uint64_t usb : 1; 2103 uint64_t sli : 1; 2104 uint64_t dpi : 1; 2105 uint64_t agx0 : 1; 2106 uint64_t reserved_37_45 : 9; 2107 uint64_t agl : 1; 2108 uint64_t ptp : 1; 2109 uint64_t pem0 : 1; 2110 uint64_t pem1 : 1; 2111 uint64_t srio0 : 1; 2112 uint64_t srio1 : 1; 2113 uint64_t lmc0 : 1; 2114 uint64_t reserved_53_55 : 3; 2115 uint64_t dfm : 1; 2116 uint64_t reserved_57_62 : 6; 2117 uint64_t rst : 1; 2118#endif 2119 } cn63xx; 2120 struct cvmx_ciu_intx_en1_w1s_cn63xx cn63xxp1; 2121}; 2122typedef union cvmx_ciu_intx_en1_w1s cvmx_ciu_intx_en1_w1s_t; 2123 2124/** 2125 * cvmx_ciu_int#_en4_0 2126 * 2127 * Notes: 2128 * CIU_INT0_EN4_0: PP0 /IP4 2129 * CIU_INT1_EN4_0: PP1 /IP4 2130 * ... 2131 * CIU_INT11_EN4_0: PP11 /IP4 2132 */ 2133union cvmx_ciu_intx_en4_0 2134{ 2135 uint64_t u64; 2136 struct cvmx_ciu_intx_en4_0_s 2137 { 2138#if __BYTE_ORDER == __BIG_ENDIAN 2139 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt enable */ 2140 uint64_t mii : 1; /**< RGMII/MII/MIX Interface 0 Interrupt enable */ 2141 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt enable */ 2142 uint64_t powiq : 1; /**< POW IQ interrupt enable */ 2143 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt enable */ 2144 uint64_t mpi : 1; /**< MPI/SPI interrupt */ 2145 uint64_t pcm : 1; /**< PCM/TDM interrupt */ 2146 uint64_t usb : 1; /**< USB EHCI or OHCI Interrupt enable */ 2147 uint64_t timer : 4; /**< General timer interrupt enables */ 2148 uint64_t key_zero : 1; /**< Key Zeroization interrupt */ 2149 uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt enable */ 2150 uint64_t gmx_drp : 2; /**< GMX packet drop interrupt enable */ 2151 uint64_t trace : 1; /**< Trace buffer interrupt enable */ 2152 uint64_t rml : 1; /**< RML Interrupt enable */ 2153 uint64_t twsi : 1; /**< TWSI Interrupt enable */ 2154 uint64_t reserved_44_44 : 1; 2155 uint64_t pci_msi : 4; /**< PCIe/sRIO MSI enables */ 2156 uint64_t pci_int : 4; /**< PCIe INTA/B/C/D enables */ 2157 uint64_t uart : 2; /**< Two UART interrupt enables */ 2158 uint64_t mbox : 2; /**< Two mailbox interrupt enables */ 2159 uint64_t gpio : 16; /**< 16 GPIO interrupt enables */ 2160 uint64_t workq : 16; /**< 16 work queue interrupt enables */ 2161#else 2162 uint64_t workq : 16; 2163 uint64_t gpio : 16; 2164 uint64_t mbox : 2; 2165 uint64_t uart : 2; 2166 uint64_t pci_int : 4; 2167 uint64_t pci_msi : 4; 2168 uint64_t reserved_44_44 : 1; 2169 uint64_t twsi : 1; 2170 uint64_t rml : 1; 2171 uint64_t trace : 1; 2172 uint64_t gmx_drp : 2; 2173 uint64_t ipd_drp : 1; 2174 uint64_t key_zero : 1; 2175 uint64_t timer : 4; 2176 uint64_t usb : 1; 2177 uint64_t pcm : 1; 2178 uint64_t mpi : 1; 2179 uint64_t twsi2 : 1; 2180 uint64_t powiq : 1; 2181 uint64_t ipdppthr : 1; 2182 uint64_t mii : 1; 2183 uint64_t bootdma : 1; 2184#endif 2185 } s; 2186 struct cvmx_ciu_intx_en4_0_cn50xx 2187 { 2188#if __BYTE_ORDER == __BIG_ENDIAN 2189 uint64_t reserved_59_63 : 5; 2190 uint64_t mpi : 1; /**< MPI/SPI interrupt */ 2191 uint64_t pcm : 1; /**< PCM/TDM interrupt */ 2192 uint64_t usb : 1; /**< USB interrupt */ 2193 uint64_t timer : 4; /**< General timer interrupts */ 2194 uint64_t reserved_51_51 : 1; 2195 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */ 2196 uint64_t reserved_49_49 : 1; 2197 uint64_t gmx_drp : 1; /**< GMX packet drop */ 2198 uint64_t reserved_47_47 : 1; 2199 uint64_t rml : 1; /**< RML Interrupt */ 2200 uint64_t twsi : 1; /**< TWSI Interrupt */ 2201 uint64_t reserved_44_44 : 1; 2202 uint64_t pci_msi : 4; /**< PCI MSI */ 2203 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */ 2204 uint64_t uart : 2; /**< Two UART interrupts */ 2205 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */ 2206 uint64_t gpio : 16; /**< 16 GPIO interrupts */ 2207 uint64_t workq : 16; /**< 16 work queue interrupts */ 2208#else 2209 uint64_t workq : 16; 2210 uint64_t gpio : 16; 2211 uint64_t mbox : 2; 2212 uint64_t uart : 2; 2213 uint64_t pci_int : 4; 2214 uint64_t pci_msi : 4; 2215 uint64_t reserved_44_44 : 1; 2216 uint64_t twsi : 1; 2217 uint64_t rml : 1; 2218 uint64_t reserved_47_47 : 1; 2219 uint64_t gmx_drp : 1; 2220 uint64_t reserved_49_49 : 1; 2221 uint64_t ipd_drp : 1; 2222 uint64_t reserved_51_51 : 1; 2223 uint64_t timer : 4; 2224 uint64_t usb : 1; 2225 uint64_t pcm : 1; 2226 uint64_t mpi : 1; 2227 uint64_t reserved_59_63 : 5; 2228#endif 2229 } cn50xx; 2230 struct cvmx_ciu_intx_en4_0_cn52xx 2231 { 2232#if __BYTE_ORDER == __BIG_ENDIAN 2233 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt */ 2234 uint64_t mii : 1; /**< MII Interface Interrupt */ 2235 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt */ 2236 uint64_t powiq : 1; /**< POW IQ interrupt */ 2237 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt */ 2238 uint64_t reserved_57_58 : 2; 2239 uint64_t usb : 1; /**< USB Interrupt */ 2240 uint64_t timer : 4; /**< General timer interrupts */ 2241 uint64_t reserved_51_51 : 1; 2242 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */ 2243 uint64_t reserved_49_49 : 1; 2244 uint64_t gmx_drp : 1; /**< GMX packet drop */ 2245 uint64_t trace : 1; /**< L2C has the CMB trace buffer */ 2246 uint64_t rml : 1; /**< RML Interrupt */ 2247 uint64_t twsi : 1; /**< TWSI Interrupt */ 2248 uint64_t reserved_44_44 : 1; 2249 uint64_t pci_msi : 4; /**< PCI MSI */ 2250 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */ 2251 uint64_t uart : 2; /**< Two UART interrupts */ 2252 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */ 2253 uint64_t gpio : 16; /**< 16 GPIO interrupts */ 2254 uint64_t workq : 16; /**< 16 work queue interrupts */ 2255#else 2256 uint64_t workq : 16; 2257 uint64_t gpio : 16; 2258 uint64_t mbox : 2; 2259 uint64_t uart : 2; 2260 uint64_t pci_int : 4; 2261 uint64_t pci_msi : 4; 2262 uint64_t reserved_44_44 : 1; 2263 uint64_t twsi : 1; 2264 uint64_t rml : 1; 2265 uint64_t trace : 1; 2266 uint64_t gmx_drp : 1; 2267 uint64_t reserved_49_49 : 1; 2268 uint64_t ipd_drp : 1; 2269 uint64_t reserved_51_51 : 1; 2270 uint64_t timer : 4; 2271 uint64_t usb : 1; 2272 uint64_t reserved_57_58 : 2; 2273 uint64_t twsi2 : 1; 2274 uint64_t powiq : 1; 2275 uint64_t ipdppthr : 1; 2276 uint64_t mii : 1; 2277 uint64_t bootdma : 1; 2278#endif 2279 } cn52xx; 2280 struct cvmx_ciu_intx_en4_0_cn52xx cn52xxp1; 2281 struct cvmx_ciu_intx_en4_0_cn56xx 2282 { 2283#if __BYTE_ORDER == __BIG_ENDIAN 2284 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt */ 2285 uint64_t mii : 1; /**< MII Interface Interrupt */ 2286 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt */ 2287 uint64_t powiq : 1; /**< POW IQ interrupt */ 2288 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt */ 2289 uint64_t reserved_57_58 : 2; 2290 uint64_t usb : 1; /**< USB Interrupt */ 2291 uint64_t timer : 4; /**< General timer interrupts */ 2292 uint64_t key_zero : 1; /**< Key Zeroization interrupt */ 2293 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */ 2294 uint64_t gmx_drp : 2; /**< GMX packet drop */ 2295 uint64_t trace : 1; /**< L2C has the CMB trace buffer */ 2296 uint64_t rml : 1; /**< RML Interrupt */ 2297 uint64_t twsi : 1; /**< TWSI Interrupt */ 2298 uint64_t reserved_44_44 : 1; 2299 uint64_t pci_msi : 4; /**< PCI MSI */ 2300 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */ 2301 uint64_t uart : 2; /**< Two UART interrupts */ 2302 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */ 2303 uint64_t gpio : 16; /**< 16 GPIO interrupts */ 2304 uint64_t workq : 16; /**< 16 work queue interrupts */ 2305#else 2306 uint64_t workq : 16; 2307 uint64_t gpio : 16; 2308 uint64_t mbox : 2; 2309 uint64_t uart : 2; 2310 uint64_t pci_int : 4; 2311 uint64_t pci_msi : 4; 2312 uint64_t reserved_44_44 : 1; 2313 uint64_t twsi : 1; 2314 uint64_t rml : 1; 2315 uint64_t trace : 1; 2316 uint64_t gmx_drp : 2; 2317 uint64_t ipd_drp : 1; 2318 uint64_t key_zero : 1; 2319 uint64_t timer : 4; 2320 uint64_t usb : 1; 2321 uint64_t reserved_57_58 : 2; 2322 uint64_t twsi2 : 1; 2323 uint64_t powiq : 1; 2324 uint64_t ipdppthr : 1; 2325 uint64_t mii : 1; 2326 uint64_t bootdma : 1; 2327#endif 2328 } cn56xx; 2329 struct cvmx_ciu_intx_en4_0_cn56xx cn56xxp1; 2330 struct cvmx_ciu_intx_en4_0_cn58xx 2331 { 2332#if __BYTE_ORDER == __BIG_ENDIAN 2333 uint64_t reserved_56_63 : 8; 2334 uint64_t timer : 4; /**< General timer interrupts */ 2335 uint64_t key_zero : 1; /**< Key Zeroization interrupt */ 2336 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */ 2337 uint64_t gmx_drp : 2; /**< GMX packet drop */ 2338 uint64_t trace : 1; /**< L2C has the CMB trace buffer */ 2339 uint64_t rml : 1; /**< RML Interrupt */ 2340 uint64_t twsi : 1; /**< TWSI Interrupt */ 2341 uint64_t reserved_44_44 : 1; 2342 uint64_t pci_msi : 4; /**< PCI MSI */ 2343 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */ 2344 uint64_t uart : 2; /**< Two UART interrupts */ 2345 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */ 2346 uint64_t gpio : 16; /**< 16 GPIO interrupts */ 2347 uint64_t workq : 16; /**< 16 work queue interrupts */ 2348#else 2349 uint64_t workq : 16; 2350 uint64_t gpio : 16; 2351 uint64_t mbox : 2; 2352 uint64_t uart : 2; 2353 uint64_t pci_int : 4; 2354 uint64_t pci_msi : 4; 2355 uint64_t reserved_44_44 : 1; 2356 uint64_t twsi : 1; 2357 uint64_t rml : 1; 2358 uint64_t trace : 1; 2359 uint64_t gmx_drp : 2; 2360 uint64_t ipd_drp : 1; 2361 uint64_t key_zero : 1; 2362 uint64_t timer : 4; 2363 uint64_t reserved_56_63 : 8; 2364#endif 2365 } cn58xx; 2366 struct cvmx_ciu_intx_en4_0_cn58xx cn58xxp1; 2367 struct cvmx_ciu_intx_en4_0_cn52xx cn63xx; 2368 struct cvmx_ciu_intx_en4_0_cn52xx cn63xxp1; 2369}; 2370typedef union cvmx_ciu_intx_en4_0 cvmx_ciu_intx_en4_0_t; 2371 2372/** 2373 * cvmx_ciu_int#_en4_0_w1c 2374 * 2375 * Notes: 2376 * Write-1-to-clear version of the CIU_INTx_EN4_0 register 2377 * 2378 */ 2379union cvmx_ciu_intx_en4_0_w1c 2380{ 2381 uint64_t u64; 2382 struct cvmx_ciu_intx_en4_0_w1c_s 2383 { 2384#if __BYTE_ORDER == __BIG_ENDIAN 2385 uint64_t bootdma : 1; /**< Write 1 to clear Boot bus DMA engines Interrupt 2386 enable */ 2387 uint64_t mii : 1; /**< Write 1 to clr RGMII/MII/MIX Interface 0 Interrupt 2388 enable */ 2389 uint64_t ipdppthr : 1; /**< Write 1 to clear IPD per-port counter threshold 2390 interrupt enable */ 2391 uint64_t powiq : 1; /**< Write 1 to clear POW IQ interrupt */ 2392 uint64_t twsi2 : 1; /**< Write 1 to clear 2nd TWSI Interrupt */ 2393 uint64_t reserved_57_58 : 2; 2394 uint64_t usb : 1; /**< Write 1 to clear USB EHCI or OHCI Interrupt */ 2395 uint64_t timer : 4; /**< Write 1 to clear General timer interrupts */ 2396 uint64_t key_zero : 1; /**< Key Zeroization interrupt */ 2397 uint64_t ipd_drp : 1; /**< Write 1 to clear IPD QOS packet drop interrupt 2398 enable */ 2399 uint64_t gmx_drp : 2; /**< Write 1 to clear GMX packet drop interrupt enable */ 2400 uint64_t trace : 1; /**< Write 1 to clear Trace buffer interrupt enable */ 2401 uint64_t rml : 1; /**< Write 1 to clear RML Interrupt enable */ 2402 uint64_t twsi : 1; /**< Write 1 to clear TWSI Interrupt enable */ 2403 uint64_t reserved_44_44 : 1; 2404 uint64_t pci_msi : 4; /**< Write 1s to clear PCIe/sRIO MSI enables */ 2405 uint64_t pci_int : 4; /**< Write 1s to clear PCIe INTA/B/C/D enables */ 2406 uint64_t uart : 2; /**< Write 1s to clear UART interrupt enables */ 2407 uint64_t mbox : 2; /**< Write 1s to clear mailbox interrupt enables */ 2408 uint64_t gpio : 16; /**< Write 1s to clear GPIO interrupt enables */ 2409 uint64_t workq : 16; /**< Write 1s to clear work queue interrupt enables */ 2410#else 2411 uint64_t workq : 16; 2412 uint64_t gpio : 16; 2413 uint64_t mbox : 2; 2414 uint64_t uart : 2; 2415 uint64_t pci_int : 4; 2416 uint64_t pci_msi : 4; 2417 uint64_t reserved_44_44 : 1; 2418 uint64_t twsi : 1; 2419 uint64_t rml : 1; 2420 uint64_t trace : 1; 2421 uint64_t gmx_drp : 2; 2422 uint64_t ipd_drp : 1; 2423 uint64_t key_zero : 1; 2424 uint64_t timer : 4; 2425 uint64_t usb : 1; 2426 uint64_t reserved_57_58 : 2; 2427 uint64_t twsi2 : 1; 2428 uint64_t powiq : 1; 2429 uint64_t ipdppthr : 1; 2430 uint64_t mii : 1; 2431 uint64_t bootdma : 1; 2432#endif 2433 } s; 2434 struct cvmx_ciu_intx_en4_0_w1c_cn52xx 2435 { 2436#if __BYTE_ORDER == __BIG_ENDIAN 2437 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt */ 2438 uint64_t mii : 1; /**< MII Interface Interrupt */ 2439 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt */ 2440 uint64_t powiq : 1; /**< POW IQ interrupt */ 2441 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt */ 2442 uint64_t reserved_57_58 : 2; 2443 uint64_t usb : 1; /**< USB Interrupt */ 2444 uint64_t timer : 4; /**< General timer interrupts */ 2445 uint64_t reserved_51_51 : 1; 2446 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */ 2447 uint64_t reserved_49_49 : 1; 2448 uint64_t gmx_drp : 1; /**< GMX packet drop */ 2449 uint64_t trace : 1; /**< L2C has the CMB trace buffer */ 2450 uint64_t rml : 1; /**< RML Interrupt */ 2451 uint64_t twsi : 1; /**< TWSI Interrupt */ 2452 uint64_t reserved_44_44 : 1; 2453 uint64_t pci_msi : 4; /**< PCI MSI */ 2454 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */ 2455 uint64_t uart : 2; /**< Two UART interrupts */ 2456 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */ 2457 uint64_t gpio : 16; /**< 16 GPIO interrupts */ 2458 uint64_t workq : 16; /**< 16 work queue interrupts */ 2459#else 2460 uint64_t workq : 16; 2461 uint64_t gpio : 16; 2462 uint64_t mbox : 2; 2463 uint64_t uart : 2; 2464 uint64_t pci_int : 4; 2465 uint64_t pci_msi : 4; 2466 uint64_t reserved_44_44 : 1; 2467 uint64_t twsi : 1; 2468 uint64_t rml : 1; 2469 uint64_t trace : 1; 2470 uint64_t gmx_drp : 1; 2471 uint64_t reserved_49_49 : 1; 2472 uint64_t ipd_drp : 1; 2473 uint64_t reserved_51_51 : 1; 2474 uint64_t timer : 4; 2475 uint64_t usb : 1; 2476 uint64_t reserved_57_58 : 2; 2477 uint64_t twsi2 : 1; 2478 uint64_t powiq : 1; 2479 uint64_t ipdppthr : 1; 2480 uint64_t mii : 1; 2481 uint64_t bootdma : 1; 2482#endif 2483 } cn52xx; 2484 struct cvmx_ciu_intx_en4_0_w1c_s cn56xx; 2485 struct cvmx_ciu_intx_en4_0_w1c_cn58xx 2486 { 2487#if __BYTE_ORDER == __BIG_ENDIAN 2488 uint64_t reserved_56_63 : 8; 2489 uint64_t timer : 4; /**< General timer interrupts */ 2490 uint64_t key_zero : 1; /**< Key Zeroization interrupt */ 2491 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */ 2492 uint64_t gmx_drp : 2; /**< GMX packet drop */ 2493 uint64_t trace : 1; /**< L2C has the CMB trace buffer */ 2494 uint64_t rml : 1; /**< RML Interrupt */ 2495 uint64_t twsi : 1; /**< TWSI Interrupt */ 2496 uint64_t reserved_44_44 : 1; 2497 uint64_t pci_msi : 4; /**< PCI MSI */ 2498 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */ 2499 uint64_t uart : 2; /**< Two UART interrupts */ 2500 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */ 2501 uint64_t gpio : 16; /**< 16 GPIO interrupts */ 2502 uint64_t workq : 16; /**< 16 work queue interrupts */ 2503#else 2504 uint64_t workq : 16; 2505 uint64_t gpio : 16; 2506 uint64_t mbox : 2; 2507 uint64_t uart : 2; 2508 uint64_t pci_int : 4; 2509 uint64_t pci_msi : 4; 2510 uint64_t reserved_44_44 : 1; 2511 uint64_t twsi : 1; 2512 uint64_t rml : 1; 2513 uint64_t trace : 1; 2514 uint64_t gmx_drp : 2; 2515 uint64_t ipd_drp : 1; 2516 uint64_t key_zero : 1; 2517 uint64_t timer : 4; 2518 uint64_t reserved_56_63 : 8; 2519#endif 2520 } cn58xx; 2521 struct cvmx_ciu_intx_en4_0_w1c_cn52xx cn63xx; 2522 struct cvmx_ciu_intx_en4_0_w1c_cn52xx cn63xxp1; 2523}; 2524typedef union cvmx_ciu_intx_en4_0_w1c cvmx_ciu_intx_en4_0_w1c_t; 2525 2526/** 2527 * cvmx_ciu_int#_en4_0_w1s 2528 * 2529 * Notes: 2530 * Write-1-to-set version of the CIU_INTx_EN4_0 register 2531 * 2532 */ 2533union cvmx_ciu_intx_en4_0_w1s 2534{ 2535 uint64_t u64; 2536 struct cvmx_ciu_intx_en4_0_w1s_s 2537 { 2538#if __BYTE_ORDER == __BIG_ENDIAN 2539 uint64_t bootdma : 1; /**< Write 1 to set Boot bus DMA engines Interrupt 2540 enable */ 2541 uint64_t mii : 1; /**< Write 1 to set RGMII/MII/MIX Interface 0 Interrupt 2542 enable */ 2543 uint64_t ipdppthr : 1; /**< Write 1 to set IPD per-port counter threshold 2544 interrupt enable */ 2545 uint64_t powiq : 1; /**< Write 1 to set POW IQ interrupt */ 2546 uint64_t twsi2 : 1; /**< Write 1 to set 2nd TWSI Interrupt */ 2547 uint64_t reserved_57_58 : 2; 2548 uint64_t usb : 1; /**< Write 1 to set USB EHCI or OHCI Interrupt */ 2549 uint64_t timer : 4; /**< Write 1 to set General timer interrupts */ 2550 uint64_t key_zero : 1; /**< Key Zeroization interrupt */ 2551 uint64_t ipd_drp : 1; /**< Write 1 to set IPD QOS packet drop interrupt 2552 enable */ 2553 uint64_t gmx_drp : 2; /**< Write 1 to set GMX packet drop interrupt enable */ 2554 uint64_t trace : 1; /**< Write 1 to set Trace buffer interrupt enable */ 2555 uint64_t rml : 1; /**< Write 1 to set RML Interrupt enable */ 2556 uint64_t twsi : 1; /**< Write 1 to set TWSI Interrupt enable */ 2557 uint64_t reserved_44_44 : 1; 2558 uint64_t pci_msi : 4; /**< Write 1s to set PCIe/sRIO MSI enables */ 2559 uint64_t pci_int : 4; /**< Write 1s to set PCIe INTA/B/C/D enables */ 2560 uint64_t uart : 2; /**< Write 1s to set UART interrupt enables */ 2561 uint64_t mbox : 2; /**< Write 1s to set mailbox interrupt enables */ 2562 uint64_t gpio : 16; /**< Write 1s to set GPIO interrupt enables */ 2563 uint64_t workq : 16; /**< Write 1s to set work queue interrupt enables */ 2564#else 2565 uint64_t workq : 16; 2566 uint64_t gpio : 16; 2567 uint64_t mbox : 2; 2568 uint64_t uart : 2; 2569 uint64_t pci_int : 4; 2570 uint64_t pci_msi : 4; 2571 uint64_t reserved_44_44 : 1; 2572 uint64_t twsi : 1; 2573 uint64_t rml : 1; 2574 uint64_t trace : 1; 2575 uint64_t gmx_drp : 2; 2576 uint64_t ipd_drp : 1; 2577 uint64_t key_zero : 1; 2578 uint64_t timer : 4; 2579 uint64_t usb : 1; 2580 uint64_t reserved_57_58 : 2; 2581 uint64_t twsi2 : 1; 2582 uint64_t powiq : 1; 2583 uint64_t ipdppthr : 1; 2584 uint64_t mii : 1; 2585 uint64_t bootdma : 1; 2586#endif 2587 } s; 2588 struct cvmx_ciu_intx_en4_0_w1s_cn52xx 2589 { 2590#if __BYTE_ORDER == __BIG_ENDIAN 2591 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt */ 2592 uint64_t mii : 1; /**< MII Interface Interrupt */ 2593 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt */ 2594 uint64_t powiq : 1; /**< POW IQ interrupt */ 2595 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt */ 2596 uint64_t reserved_57_58 : 2; 2597 uint64_t usb : 1; /**< USB Interrupt */ 2598 uint64_t timer : 4; /**< General timer interrupts */ 2599 uint64_t reserved_51_51 : 1; 2600 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */ 2601 uint64_t reserved_49_49 : 1; 2602 uint64_t gmx_drp : 1; /**< GMX packet drop */ 2603 uint64_t trace : 1; /**< L2C has the CMB trace buffer */ 2604 uint64_t rml : 1; /**< RML Interrupt */ 2605 uint64_t twsi : 1; /**< TWSI Interrupt */ 2606 uint64_t reserved_44_44 : 1; 2607 uint64_t pci_msi : 4; /**< PCI MSI */ 2608 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */ 2609 uint64_t uart : 2; /**< Two UART interrupts */ 2610 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */ 2611 uint64_t gpio : 16; /**< 16 GPIO interrupts */ 2612 uint64_t workq : 16; /**< 16 work queue interrupts */ 2613#else 2614 uint64_t workq : 16; 2615 uint64_t gpio : 16; 2616 uint64_t mbox : 2; 2617 uint64_t uart : 2; 2618 uint64_t pci_int : 4; 2619 uint64_t pci_msi : 4; 2620 uint64_t reserved_44_44 : 1; 2621 uint64_t twsi : 1; 2622 uint64_t rml : 1; 2623 uint64_t trace : 1; 2624 uint64_t gmx_drp : 1; 2625 uint64_t reserved_49_49 : 1; 2626 uint64_t ipd_drp : 1; 2627 uint64_t reserved_51_51 : 1; 2628 uint64_t timer : 4; 2629 uint64_t usb : 1; 2630 uint64_t reserved_57_58 : 2; 2631 uint64_t twsi2 : 1; 2632 uint64_t powiq : 1; 2633 uint64_t ipdppthr : 1; 2634 uint64_t mii : 1; 2635 uint64_t bootdma : 1; 2636#endif 2637 } cn52xx; 2638 struct cvmx_ciu_intx_en4_0_w1s_s cn56xx; 2639 struct cvmx_ciu_intx_en4_0_w1s_cn58xx 2640 { 2641#if __BYTE_ORDER == __BIG_ENDIAN 2642 uint64_t reserved_56_63 : 8; 2643 uint64_t timer : 4; /**< General timer interrupts */ 2644 uint64_t key_zero : 1; /**< Key Zeroization interrupt */ 2645 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */ 2646 uint64_t gmx_drp : 2; /**< GMX packet drop */ 2647 uint64_t trace : 1; /**< L2C has the CMB trace buffer */ 2648 uint64_t rml : 1; /**< RML Interrupt */ 2649 uint64_t twsi : 1; /**< TWSI Interrupt */ 2650 uint64_t reserved_44_44 : 1; 2651 uint64_t pci_msi : 4; /**< PCI MSI */ 2652 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */ 2653 uint64_t uart : 2; /**< Two UART interrupts */ 2654 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */ 2655 uint64_t gpio : 16; /**< 16 GPIO interrupts */ 2656 uint64_t workq : 16; /**< 16 work queue interrupts */ 2657#else 2658 uint64_t workq : 16; 2659 uint64_t gpio : 16; 2660 uint64_t mbox : 2; 2661 uint64_t uart : 2; 2662 uint64_t pci_int : 4; 2663 uint64_t pci_msi : 4; 2664 uint64_t reserved_44_44 : 1; 2665 uint64_t twsi : 1; 2666 uint64_t rml : 1; 2667 uint64_t trace : 1; 2668 uint64_t gmx_drp : 2; 2669 uint64_t ipd_drp : 1; 2670 uint64_t key_zero : 1; 2671 uint64_t timer : 4; 2672 uint64_t reserved_56_63 : 8; 2673#endif 2674 } cn58xx; 2675 struct cvmx_ciu_intx_en4_0_w1s_cn52xx cn63xx; 2676 struct cvmx_ciu_intx_en4_0_w1s_cn52xx cn63xxp1; 2677}; 2678typedef union cvmx_ciu_intx_en4_0_w1s cvmx_ciu_intx_en4_0_w1s_t; 2679 2680/** 2681 * cvmx_ciu_int#_en4_1 2682 * 2683 * Notes: 2684 * PPx/IP4 will be raised when... 2685 * PPx/IP4 = |([CIU_INT_SUM1, CIU_INTx_SUM4] & [CIU_INTx_EN4_1, CIU_INTx_EN4_0]) 2686 */ 2687union cvmx_ciu_intx_en4_1 2688{ 2689 uint64_t u64; 2690 struct cvmx_ciu_intx_en4_1_s 2691 { 2692#if __BYTE_ORDER == __BIG_ENDIAN 2693 uint64_t rst : 1; /**< MIO RST interrupt enable */ 2694 uint64_t reserved_57_62 : 6; 2695 uint64_t dfm : 1; /**< DFM interrupt enable */ 2696 uint64_t reserved_53_55 : 3; 2697 uint64_t lmc0 : 1; /**< LMC0 interrupt enable */ 2698 uint64_t srio1 : 1; /**< SRIO1 interrupt enable */ 2699 uint64_t srio0 : 1; /**< SRIO0 interrupt enable */ 2700 uint64_t pem1 : 1; /**< PEM1 interrupt enable */ 2701 uint64_t pem0 : 1; /**< PEM0 interrupt enable */ 2702 uint64_t ptp : 1; /**< PTP interrupt enable */ 2703 uint64_t agl : 1; /**< AGL interrupt enable */ 2704 uint64_t reserved_37_45 : 9; 2705 uint64_t agx0 : 1; /**< GMX0 interrupt enable */ 2706 uint64_t dpi : 1; /**< DPI interrupt enable */ 2707 uint64_t sli : 1; /**< SLI interrupt enable */ 2708 uint64_t usb : 1; /**< USB UCTL0 interrupt enable */ 2709 uint64_t dfa : 1; /**< DFA interrupt enable */ 2710 uint64_t key : 1; /**< KEY interrupt enable */ 2711 uint64_t rad : 1; /**< RAD interrupt enable */ 2712 uint64_t tim : 1; /**< TIM interrupt enable */ 2713 uint64_t zip : 1; /**< ZIP interrupt enable */ 2714 uint64_t pko : 1; /**< PKO interrupt enable */ 2715 uint64_t pip : 1; /**< PIP interrupt enable */ 2716 uint64_t ipd : 1; /**< IPD interrupt enable */ 2717 uint64_t l2c : 1; /**< L2C interrupt enable */ 2718 uint64_t pow : 1; /**< POW err interrupt enable */ 2719 uint64_t fpa : 1; /**< FPA interrupt enable */ 2720 uint64_t iob : 1; /**< IOB interrupt enable */ 2721 uint64_t mio : 1; /**< MIO boot interrupt enable */ 2722 uint64_t nand : 1; /**< NAND Flash Controller interrupt enable */ 2723 uint64_t mii1 : 1; /**< RGMII/MII/MIX Interface 1 Interrupt enable */ 2724 uint64_t usb1 : 1; /**< Second USB Interrupt */ 2725 uint64_t uart2 : 1; /**< Third UART interrupt */ 2726 uint64_t wdog : 16; /**< Watchdog summary interrupt enable vector */ 2727#else 2728 uint64_t wdog : 16; 2729 uint64_t uart2 : 1; 2730 uint64_t usb1 : 1; 2731 uint64_t mii1 : 1; 2732 uint64_t nand : 1; 2733 uint64_t mio : 1; 2734 uint64_t iob : 1; 2735 uint64_t fpa : 1; 2736 uint64_t pow : 1; 2737 uint64_t l2c : 1; 2738 uint64_t ipd : 1; 2739 uint64_t pip : 1; 2740 uint64_t pko : 1; 2741 uint64_t zip : 1; 2742 uint64_t tim : 1; 2743 uint64_t rad : 1; 2744 uint64_t key : 1; 2745 uint64_t dfa : 1; 2746 uint64_t usb : 1; 2747 uint64_t sli : 1; 2748 uint64_t dpi : 1; 2749 uint64_t agx0 : 1; 2750 uint64_t reserved_37_45 : 9; 2751 uint64_t agl : 1; 2752 uint64_t ptp : 1; 2753 uint64_t pem0 : 1; 2754 uint64_t pem1 : 1; 2755 uint64_t srio0 : 1; 2756 uint64_t srio1 : 1; 2757 uint64_t lmc0 : 1; 2758 uint64_t reserved_53_55 : 3; 2759 uint64_t dfm : 1; 2760 uint64_t reserved_57_62 : 6; 2761 uint64_t rst : 1; 2762#endif 2763 } s; 2764 struct cvmx_ciu_intx_en4_1_cn50xx 2765 { 2766#if __BYTE_ORDER == __BIG_ENDIAN 2767 uint64_t reserved_2_63 : 62; 2768 uint64_t wdog : 2; /**< Watchdog summary interrupt enable vectory */ 2769#else 2770 uint64_t wdog : 2; 2771 uint64_t reserved_2_63 : 62; 2772#endif 2773 } cn50xx; 2774 struct cvmx_ciu_intx_en4_1_cn52xx 2775 { 2776#if __BYTE_ORDER == __BIG_ENDIAN 2777 uint64_t reserved_20_63 : 44; 2778 uint64_t nand : 1; /**< NAND Flash Controller */ 2779 uint64_t mii1 : 1; /**< Second MII Interrupt */ 2780 uint64_t usb1 : 1; /**< Second USB Interrupt */ 2781 uint64_t uart2 : 1; /**< Third UART interrupt */ 2782 uint64_t reserved_4_15 : 12; 2783 uint64_t wdog : 4; /**< Watchdog summary interrupt enable vector */ 2784#else 2785 uint64_t wdog : 4; 2786 uint64_t reserved_4_15 : 12; 2787 uint64_t uart2 : 1; 2788 uint64_t usb1 : 1; 2789 uint64_t mii1 : 1; 2790 uint64_t nand : 1; 2791 uint64_t reserved_20_63 : 44; 2792#endif 2793 } cn52xx; 2794 struct cvmx_ciu_intx_en4_1_cn52xxp1 2795 { 2796#if __BYTE_ORDER == __BIG_ENDIAN 2797 uint64_t reserved_19_63 : 45; 2798 uint64_t mii1 : 1; /**< Second MII Interrupt */ 2799 uint64_t usb1 : 1; /**< Second USB Interrupt */ 2800 uint64_t uart2 : 1; /**< Third UART interrupt */ 2801 uint64_t reserved_4_15 : 12; 2802 uint64_t wdog : 4; /**< Watchdog summary interrupt enable vector */ 2803#else 2804 uint64_t wdog : 4; 2805 uint64_t reserved_4_15 : 12; 2806 uint64_t uart2 : 1; 2807 uint64_t usb1 : 1; 2808 uint64_t mii1 : 1; 2809 uint64_t reserved_19_63 : 45; 2810#endif 2811 } cn52xxp1; 2812 struct cvmx_ciu_intx_en4_1_cn56xx 2813 { 2814#if __BYTE_ORDER == __BIG_ENDIAN 2815 uint64_t reserved_12_63 : 52; 2816 uint64_t wdog : 12; /**< Watchdog summary interrupt enable vectory */ 2817#else 2818 uint64_t wdog : 12; 2819 uint64_t reserved_12_63 : 52; 2820#endif 2821 } cn56xx; 2822 struct cvmx_ciu_intx_en4_1_cn56xx cn56xxp1; 2823 struct cvmx_ciu_intx_en4_1_cn58xx 2824 { 2825#if __BYTE_ORDER == __BIG_ENDIAN 2826 uint64_t reserved_16_63 : 48; 2827 uint64_t wdog : 16; /**< Watchdog summary interrupt enable vectory */ 2828#else 2829 uint64_t wdog : 16; 2830 uint64_t reserved_16_63 : 48; 2831#endif 2832 } cn58xx; 2833 struct cvmx_ciu_intx_en4_1_cn58xx cn58xxp1; 2834 struct cvmx_ciu_intx_en4_1_cn63xx 2835 { 2836#if __BYTE_ORDER == __BIG_ENDIAN 2837 uint64_t rst : 1; /**< MIO RST interrupt enable */ 2838 uint64_t reserved_57_62 : 6; 2839 uint64_t dfm : 1; /**< DFM interrupt enable */ 2840 uint64_t reserved_53_55 : 3; 2841 uint64_t lmc0 : 1; /**< LMC0 interrupt enable */ 2842 uint64_t srio1 : 1; /**< SRIO1 interrupt enable */ 2843 uint64_t srio0 : 1; /**< SRIO0 interrupt enable */ 2844 uint64_t pem1 : 1; /**< PEM1 interrupt enable */ 2845 uint64_t pem0 : 1; /**< PEM0 interrupt enable */ 2846 uint64_t ptp : 1; /**< PTP interrupt enable */ 2847 uint64_t agl : 1; /**< AGL interrupt enable */ 2848 uint64_t reserved_37_45 : 9; 2849 uint64_t agx0 : 1; /**< GMX0 interrupt enable */ 2850 uint64_t dpi : 1; /**< DPI interrupt enable */ 2851 uint64_t sli : 1; /**< SLI interrupt enable */ 2852 uint64_t usb : 1; /**< USB UCTL0 interrupt enable */ 2853 uint64_t dfa : 1; /**< DFA interrupt enable */ 2854 uint64_t key : 1; /**< KEY interrupt enable */ 2855 uint64_t rad : 1; /**< RAD interrupt enable */ 2856 uint64_t tim : 1; /**< TIM interrupt enable */ 2857 uint64_t zip : 1; /**< ZIP interrupt enable */ 2858 uint64_t pko : 1; /**< PKO interrupt enable */ 2859 uint64_t pip : 1; /**< PIP interrupt enable */ 2860 uint64_t ipd : 1; /**< IPD interrupt enable */ 2861 uint64_t l2c : 1; /**< L2C interrupt enable */ 2862 uint64_t pow : 1; /**< POW err interrupt enable */ 2863 uint64_t fpa : 1; /**< FPA interrupt enable */ 2864 uint64_t iob : 1; /**< IOB interrupt enable */ 2865 uint64_t mio : 1; /**< MIO boot interrupt enable */ 2866 uint64_t nand : 1; /**< NAND Flash Controller interrupt enable */ 2867 uint64_t mii1 : 1; /**< RGMII/MII/MIX Interface 1 Interrupt enable */ 2868 uint64_t reserved_6_17 : 12; 2869 uint64_t wdog : 6; /**< Watchdog summary interrupt enable vector */ 2870#else 2871 uint64_t wdog : 6; 2872 uint64_t reserved_6_17 : 12; 2873 uint64_t mii1 : 1; 2874 uint64_t nand : 1; 2875 uint64_t mio : 1; 2876 uint64_t iob : 1; 2877 uint64_t fpa : 1; 2878 uint64_t pow : 1; 2879 uint64_t l2c : 1; 2880 uint64_t ipd : 1; 2881 uint64_t pip : 1; 2882 uint64_t pko : 1; 2883 uint64_t zip : 1; 2884 uint64_t tim : 1; 2885 uint64_t rad : 1; 2886 uint64_t key : 1; 2887 uint64_t dfa : 1; 2888 uint64_t usb : 1; 2889 uint64_t sli : 1; 2890 uint64_t dpi : 1; 2891 uint64_t agx0 : 1; 2892 uint64_t reserved_37_45 : 9; 2893 uint64_t agl : 1; 2894 uint64_t ptp : 1; 2895 uint64_t pem0 : 1; 2896 uint64_t pem1 : 1; 2897 uint64_t srio0 : 1; 2898 uint64_t srio1 : 1; 2899 uint64_t lmc0 : 1; 2900 uint64_t reserved_53_55 : 3; 2901 uint64_t dfm : 1; 2902 uint64_t reserved_57_62 : 6; 2903 uint64_t rst : 1; 2904#endif 2905 } cn63xx; 2906 struct cvmx_ciu_intx_en4_1_cn63xx cn63xxp1; 2907}; 2908typedef union cvmx_ciu_intx_en4_1 cvmx_ciu_intx_en4_1_t; 2909 2910/** 2911 * cvmx_ciu_int#_en4_1_w1c 2912 * 2913 * Notes: 2914 * Write-1-to-clear version of the CIU_INTx_EN4_1 register 2915 * 2916 */ 2917union cvmx_ciu_intx_en4_1_w1c 2918{ 2919 uint64_t u64; 2920 struct cvmx_ciu_intx_en4_1_w1c_s 2921 { 2922#if __BYTE_ORDER == __BIG_ENDIAN 2923 uint64_t rst : 1; /**< Write 1 to clear MIO RST interrupt enable */ 2924 uint64_t reserved_57_62 : 6; 2925 uint64_t dfm : 1; /**< Write 1 to clear DFM interrupt enable */ 2926 uint64_t reserved_53_55 : 3; 2927 uint64_t lmc0 : 1; /**< Write 1 to clear LMC0 interrupt enable */ 2928 uint64_t srio1 : 1; /**< Write 1 to clear SRIO1 interrupt enable */ 2929 uint64_t srio0 : 1; /**< Write 1 to clear SRIO0 interrupt enable */ 2930 uint64_t pem1 : 1; /**< Write 1 to clear PEM1 interrupt enable */ 2931 uint64_t pem0 : 1; /**< Write 1 to clear PEM0 interrupt enable */ 2932 uint64_t ptp : 1; /**< Write 1 to clear PTP interrupt enable */ 2933 uint64_t agl : 1; /**< Write 1 to clear AGL interrupt enable */ 2934 uint64_t reserved_37_45 : 9; 2935 uint64_t agx0 : 1; /**< Write 1 to clear GMX0 interrupt enable */ 2936 uint64_t dpi : 1; /**< Write 1 to clear DPI interrupt enable */ 2937 uint64_t sli : 1; /**< Write 1 to clear SLI interrupt enable */ 2938 uint64_t usb : 1; /**< Write 1 to clear USB UCTL0 interrupt enable */ 2939 uint64_t dfa : 1; /**< Write 1 to clear DFA interrupt enable */ 2940 uint64_t key : 1; /**< Write 1 to clear KEY interrupt enable */ 2941 uint64_t rad : 1; /**< Write 1 to clear RAD interrupt enable */ 2942 uint64_t tim : 1; /**< Write 1 to clear TIM interrupt enable */ 2943 uint64_t zip : 1; /**< Write 1 to clear ZIP interrupt enable */ 2944 uint64_t pko : 1; /**< Write 1 to clear PKO interrupt enable */ 2945 uint64_t pip : 1; /**< Write 1 to clear PIP interrupt enable */ 2946 uint64_t ipd : 1; /**< Write 1 to clear IPD interrupt enable */ 2947 uint64_t l2c : 1; /**< Write 1 to clear L2C interrupt enable */ 2948 uint64_t pow : 1; /**< Write 1 to clear POW err interrupt enable */ 2949 uint64_t fpa : 1; /**< Write 1 to clear FPA interrupt enable */ 2950 uint64_t iob : 1; /**< Write 1 to clear IOB interrupt enable */ 2951 uint64_t mio : 1; /**< Write 1 to clear MIO boot interrupt enable */ 2952 uint64_t nand : 1; /**< Write 1 to clear NAND Flash Controller interrupt 2953 enable */ 2954 uint64_t mii1 : 1; /**< Write 1 to clear RGMII/MII/MIX Interface 1 2955 Interrupt enable */ 2956 uint64_t usb1 : 1; /**< Second USB Interrupt */ 2957 uint64_t uart2 : 1; /**< Third UART interrupt */ 2958 uint64_t wdog : 16; /**< Write 1s to clear Watchdog summary interrupt enable */ 2959#else 2960 uint64_t wdog : 16; 2961 uint64_t uart2 : 1; 2962 uint64_t usb1 : 1; 2963 uint64_t mii1 : 1; 2964 uint64_t nand : 1; 2965 uint64_t mio : 1; 2966 uint64_t iob : 1; 2967 uint64_t fpa : 1; 2968 uint64_t pow : 1; 2969 uint64_t l2c : 1; 2970 uint64_t ipd : 1; 2971 uint64_t pip : 1; 2972 uint64_t pko : 1; 2973 uint64_t zip : 1; 2974 uint64_t tim : 1; 2975 uint64_t rad : 1; 2976 uint64_t key : 1; 2977 uint64_t dfa : 1; 2978 uint64_t usb : 1; 2979 uint64_t sli : 1; 2980 uint64_t dpi : 1; 2981 uint64_t agx0 : 1; 2982 uint64_t reserved_37_45 : 9; 2983 uint64_t agl : 1; 2984 uint64_t ptp : 1; 2985 uint64_t pem0 : 1; 2986 uint64_t pem1 : 1; 2987 uint64_t srio0 : 1; 2988 uint64_t srio1 : 1; 2989 uint64_t lmc0 : 1; 2990 uint64_t reserved_53_55 : 3; 2991 uint64_t dfm : 1; 2992 uint64_t reserved_57_62 : 6; 2993 uint64_t rst : 1; 2994#endif 2995 } s; 2996 struct cvmx_ciu_intx_en4_1_w1c_cn52xx 2997 { 2998#if __BYTE_ORDER == __BIG_ENDIAN 2999 uint64_t reserved_20_63 : 44; 3000 uint64_t nand : 1; /**< NAND Flash Controller */ 3001 uint64_t mii1 : 1; /**< Second MII Interrupt */ 3002 uint64_t usb1 : 1; /**< Second USB Interrupt */ 3003 uint64_t uart2 : 1; /**< Third UART interrupt */ 3004 uint64_t reserved_4_15 : 12; 3005 uint64_t wdog : 4; /**< Watchdog summary interrupt enable vector */ 3006#else 3007 uint64_t wdog : 4; 3008 uint64_t reserved_4_15 : 12; 3009 uint64_t uart2 : 1; 3010 uint64_t usb1 : 1; 3011 uint64_t mii1 : 1; 3012 uint64_t nand : 1; 3013 uint64_t reserved_20_63 : 44; 3014#endif 3015 } cn52xx; 3016 struct cvmx_ciu_intx_en4_1_w1c_cn56xx 3017 { 3018#if __BYTE_ORDER == __BIG_ENDIAN 3019 uint64_t reserved_12_63 : 52; 3020 uint64_t wdog : 12; /**< Watchdog summary interrupt enable vectory */ 3021#else 3022 uint64_t wdog : 12; 3023 uint64_t reserved_12_63 : 52; 3024#endif 3025 } cn56xx; 3026 struct cvmx_ciu_intx_en4_1_w1c_cn58xx 3027 { 3028#if __BYTE_ORDER == __BIG_ENDIAN 3029 uint64_t reserved_16_63 : 48; 3030 uint64_t wdog : 16; /**< Watchdog summary interrupt enable vectory */ 3031#else 3032 uint64_t wdog : 16; 3033 uint64_t reserved_16_63 : 48; 3034#endif 3035 } cn58xx; 3036 struct cvmx_ciu_intx_en4_1_w1c_cn63xx 3037 { 3038#if __BYTE_ORDER == __BIG_ENDIAN 3039 uint64_t rst : 1; /**< Write 1 to clear MIO RST interrupt enable */ 3040 uint64_t reserved_57_62 : 6; 3041 uint64_t dfm : 1; /**< Write 1 to clear DFM interrupt enable */ 3042 uint64_t reserved_53_55 : 3; 3043 uint64_t lmc0 : 1; /**< Write 1 to clear LMC0 interrupt enable */ 3044 uint64_t srio1 : 1; /**< Write 1 to clear SRIO1 interrupt enable */ 3045 uint64_t srio0 : 1; /**< Write 1 to clear SRIO0 interrupt enable */ 3046 uint64_t pem1 : 1; /**< Write 1 to clear PEM1 interrupt enable */ 3047 uint64_t pem0 : 1; /**< Write 1 to clear PEM0 interrupt enable */ 3048 uint64_t ptp : 1; /**< Write 1 to clear PTP interrupt enable */ 3049 uint64_t agl : 1; /**< Write 1 to clear AGL interrupt enable */ 3050 uint64_t reserved_37_45 : 9; 3051 uint64_t agx0 : 1; /**< Write 1 to clear GMX0 interrupt enable */ 3052 uint64_t dpi : 1; /**< Write 1 to clear DPI interrupt enable */ 3053 uint64_t sli : 1; /**< Write 1 to clear SLI interrupt enable */ 3054 uint64_t usb : 1; /**< Write 1 to clear USB UCTL0 interrupt enable */ 3055 uint64_t dfa : 1; /**< Write 1 to clear DFA interrupt enable */ 3056 uint64_t key : 1; /**< Write 1 to clear KEY interrupt enable */ 3057 uint64_t rad : 1; /**< Write 1 to clear RAD interrupt enable */ 3058 uint64_t tim : 1; /**< Write 1 to clear TIM interrupt enable */ 3059 uint64_t zip : 1; /**< Write 1 to clear ZIP interrupt enable */ 3060 uint64_t pko : 1; /**< Write 1 to clear PKO interrupt enable */ 3061 uint64_t pip : 1; /**< Write 1 to clear PIP interrupt enable */ 3062 uint64_t ipd : 1; /**< Write 1 to clear IPD interrupt enable */ 3063 uint64_t l2c : 1; /**< Write 1 to clear L2C interrupt enable */ 3064 uint64_t pow : 1; /**< Write 1 to clear POW err interrupt enable */ 3065 uint64_t fpa : 1; /**< Write 1 to clear FPA interrupt enable */ 3066 uint64_t iob : 1; /**< Write 1 to clear IOB interrupt enable */ 3067 uint64_t mio : 1; /**< Write 1 to clear MIO boot interrupt enable */ 3068 uint64_t nand : 1; /**< Write 1 to clear NAND Flash Controller interrupt 3069 enable */ 3070 uint64_t mii1 : 1; /**< Write 1 to clear RGMII/MII/MIX Interface 1 3071 Interrupt enable */ 3072 uint64_t reserved_6_17 : 12; 3073 uint64_t wdog : 6; /**< Write 1s to clear Watchdog summary interrupt enable */ 3074#else 3075 uint64_t wdog : 6; 3076 uint64_t reserved_6_17 : 12; 3077 uint64_t mii1 : 1; 3078 uint64_t nand : 1; 3079 uint64_t mio : 1; 3080 uint64_t iob : 1; 3081 uint64_t fpa : 1; 3082 uint64_t pow : 1; 3083 uint64_t l2c : 1; 3084 uint64_t ipd : 1; 3085 uint64_t pip : 1; 3086 uint64_t pko : 1; 3087 uint64_t zip : 1; 3088 uint64_t tim : 1; 3089 uint64_t rad : 1; 3090 uint64_t key : 1; 3091 uint64_t dfa : 1; 3092 uint64_t usb : 1; 3093 uint64_t sli : 1; 3094 uint64_t dpi : 1; 3095 uint64_t agx0 : 1; 3096 uint64_t reserved_37_45 : 9; 3097 uint64_t agl : 1; 3098 uint64_t ptp : 1; 3099 uint64_t pem0 : 1; 3100 uint64_t pem1 : 1; 3101 uint64_t srio0 : 1; 3102 uint64_t srio1 : 1; 3103 uint64_t lmc0 : 1; 3104 uint64_t reserved_53_55 : 3; 3105 uint64_t dfm : 1; 3106 uint64_t reserved_57_62 : 6; 3107 uint64_t rst : 1; 3108#endif 3109 } cn63xx; 3110 struct cvmx_ciu_intx_en4_1_w1c_cn63xx cn63xxp1; 3111}; 3112typedef union cvmx_ciu_intx_en4_1_w1c cvmx_ciu_intx_en4_1_w1c_t; 3113 3114/** 3115 * cvmx_ciu_int#_en4_1_w1s 3116 * 3117 * Notes: 3118 * Write-1-to-set version of the CIU_INTx_EN4_1 register 3119 * 3120 */ 3121union cvmx_ciu_intx_en4_1_w1s 3122{ 3123 uint64_t u64; 3124 struct cvmx_ciu_intx_en4_1_w1s_s 3125 { 3126#if __BYTE_ORDER == __BIG_ENDIAN 3127 uint64_t rst : 1; /**< Write 1 to set MIO RST interrupt enable */ 3128 uint64_t reserved_57_62 : 6; 3129 uint64_t dfm : 1; /**< Write 1 to set DFM interrupt enable */ 3130 uint64_t reserved_53_55 : 3; 3131 uint64_t lmc0 : 1; /**< Write 1 to set LMC0 interrupt enable */ 3132 uint64_t srio1 : 1; /**< Write 1 to set SRIO1 interrupt enable */ 3133 uint64_t srio0 : 1; /**< Write 1 to set SRIO0 interrupt enable */ 3134 uint64_t pem1 : 1; /**< Write 1 to set PEM1 interrupt enable */ 3135 uint64_t pem0 : 1; /**< Write 1 to set PEM0 interrupt enable */ 3136 uint64_t ptp : 1; /**< Write 1 to set PTP interrupt enable */ 3137 uint64_t agl : 1; /**< Write 1 to set AGL interrupt enable */ 3138 uint64_t reserved_37_45 : 9; 3139 uint64_t agx0 : 1; /**< Write 1 to set GMX0 interrupt enable */ 3140 uint64_t dpi : 1; /**< Write 1 to set DPI interrupt enable */ 3141 uint64_t sli : 1; /**< Write 1 to set SLI interrupt enable */ 3142 uint64_t usb : 1; /**< Write 1 to set USB UCTL0 interrupt enable */ 3143 uint64_t dfa : 1; /**< Write 1 to set DFA interrupt enable */ 3144 uint64_t key : 1; /**< Write 1 to set KEY interrupt enable */ 3145 uint64_t rad : 1; /**< Write 1 to set RAD interrupt enable */ 3146 uint64_t tim : 1; /**< Write 1 to set TIM interrupt enable */ 3147 uint64_t zip : 1; /**< Write 1 to set ZIP interrupt enable */ 3148 uint64_t pko : 1; /**< Write 1 to set PKO interrupt enable */ 3149 uint64_t pip : 1; /**< Write 1 to set PIP interrupt enable */ 3150 uint64_t ipd : 1; /**< Write 1 to set IPD interrupt enable */ 3151 uint64_t l2c : 1; /**< Write 1 to set L2C interrupt enable */ 3152 uint64_t pow : 1; /**< Write 1 to set POW err interrupt enable */ 3153 uint64_t fpa : 1; /**< Write 1 to set FPA interrupt enable */ 3154 uint64_t iob : 1; /**< Write 1 to set IOB interrupt enable */ 3155 uint64_t mio : 1; /**< Write 1 to set MIO boot interrupt enable */ 3156 uint64_t nand : 1; /**< Write 1 to set NAND Flash Controller interrupt 3157 enable */ 3158 uint64_t mii1 : 1; /**< Write 1 to set RGMII/MII/MIX Interface 1 Interrupt 3159 enable */ 3160 uint64_t usb1 : 1; /**< Second USB Interrupt */ 3161 uint64_t uart2 : 1; /**< Third UART interrupt */ 3162 uint64_t wdog : 16; /**< Write 1s to set Watchdog summary interrupt enable */ 3163#else 3164 uint64_t wdog : 16; 3165 uint64_t uart2 : 1; 3166 uint64_t usb1 : 1; 3167 uint64_t mii1 : 1; 3168 uint64_t nand : 1; 3169 uint64_t mio : 1; 3170 uint64_t iob : 1; 3171 uint64_t fpa : 1; 3172 uint64_t pow : 1; 3173 uint64_t l2c : 1; 3174 uint64_t ipd : 1; 3175 uint64_t pip : 1; 3176 uint64_t pko : 1; 3177 uint64_t zip : 1; 3178 uint64_t tim : 1; 3179 uint64_t rad : 1; 3180 uint64_t key : 1; 3181 uint64_t dfa : 1; 3182 uint64_t usb : 1; 3183 uint64_t sli : 1; 3184 uint64_t dpi : 1; 3185 uint64_t agx0 : 1; 3186 uint64_t reserved_37_45 : 9; 3187 uint64_t agl : 1; 3188 uint64_t ptp : 1; 3189 uint64_t pem0 : 1; 3190 uint64_t pem1 : 1; 3191 uint64_t srio0 : 1; 3192 uint64_t srio1 : 1; 3193 uint64_t lmc0 : 1; 3194 uint64_t reserved_53_55 : 3; 3195 uint64_t dfm : 1; 3196 uint64_t reserved_57_62 : 6; 3197 uint64_t rst : 1; 3198#endif 3199 } s; 3200 struct cvmx_ciu_intx_en4_1_w1s_cn52xx 3201 { 3202#if __BYTE_ORDER == __BIG_ENDIAN 3203 uint64_t reserved_20_63 : 44; 3204 uint64_t nand : 1; /**< NAND Flash Controller */ 3205 uint64_t mii1 : 1; /**< Second MII Interrupt */ 3206 uint64_t usb1 : 1; /**< Second USB Interrupt */ 3207 uint64_t uart2 : 1; /**< Third UART interrupt */ 3208 uint64_t reserved_4_15 : 12; 3209 uint64_t wdog : 4; /**< Watchdog summary interrupt enable vector */ 3210#else 3211 uint64_t wdog : 4; 3212 uint64_t reserved_4_15 : 12; 3213 uint64_t uart2 : 1; 3214 uint64_t usb1 : 1; 3215 uint64_t mii1 : 1; 3216 uint64_t nand : 1; 3217 uint64_t reserved_20_63 : 44; 3218#endif 3219 } cn52xx; 3220 struct cvmx_ciu_intx_en4_1_w1s_cn56xx 3221 { 3222#if __BYTE_ORDER == __BIG_ENDIAN 3223 uint64_t reserved_12_63 : 52; 3224 uint64_t wdog : 12; /**< Watchdog summary interrupt enable vectory */ 3225#else 3226 uint64_t wdog : 12; 3227 uint64_t reserved_12_63 : 52; 3228#endif 3229 } cn56xx; 3230 struct cvmx_ciu_intx_en4_1_w1s_cn58xx 3231 { 3232#if __BYTE_ORDER == __BIG_ENDIAN 3233 uint64_t reserved_16_63 : 48; 3234 uint64_t wdog : 16; /**< Watchdog summary interrupt enable vectory */ 3235#else 3236 uint64_t wdog : 16; 3237 uint64_t reserved_16_63 : 48; 3238#endif 3239 } cn58xx; 3240 struct cvmx_ciu_intx_en4_1_w1s_cn63xx 3241 { 3242#if __BYTE_ORDER == __BIG_ENDIAN 3243 uint64_t rst : 1; /**< Write 1 to set MIO RST interrupt enable */ 3244 uint64_t reserved_57_62 : 6; 3245 uint64_t dfm : 1; /**< Write 1 to set DFM interrupt enable */ 3246 uint64_t reserved_53_55 : 3; 3247 uint64_t lmc0 : 1; /**< Write 1 to set LMC0 interrupt enable */ 3248 uint64_t srio1 : 1; /**< Write 1 to set SRIO1 interrupt enable */ 3249 uint64_t srio0 : 1; /**< Write 1 to set SRIO0 interrupt enable */ 3250 uint64_t pem1 : 1; /**< Write 1 to set PEM1 interrupt enable */ 3251 uint64_t pem0 : 1; /**< Write 1 to set PEM0 interrupt enable */ 3252 uint64_t ptp : 1; /**< Write 1 to set PTP interrupt enable */ 3253 uint64_t agl : 1; /**< Write 1 to set AGL interrupt enable */ 3254 uint64_t reserved_37_45 : 9; 3255 uint64_t agx0 : 1; /**< Write 1 to set GMX0 interrupt enable */ 3256 uint64_t dpi : 1; /**< Write 1 to set DPI interrupt enable */ 3257 uint64_t sli : 1; /**< Write 1 to set SLI interrupt enable */ 3258 uint64_t usb : 1; /**< Write 1 to set USB UCTL0 interrupt enable */ 3259 uint64_t dfa : 1; /**< Write 1 to set DFA interrupt enable */ 3260 uint64_t key : 1; /**< Write 1 to set KEY interrupt enable */ 3261 uint64_t rad : 1; /**< Write 1 to set RAD interrupt enable */ 3262 uint64_t tim : 1; /**< Write 1 to set TIM interrupt enable */ 3263 uint64_t zip : 1; /**< Write 1 to set ZIP interrupt enable */ 3264 uint64_t pko : 1; /**< Write 1 to set PKO interrupt enable */ 3265 uint64_t pip : 1; /**< Write 1 to set PIP interrupt enable */ 3266 uint64_t ipd : 1; /**< Write 1 to set IPD interrupt enable */ 3267 uint64_t l2c : 1; /**< Write 1 to set L2C interrupt enable */ 3268 uint64_t pow : 1; /**< Write 1 to set POW err interrupt enable */ 3269 uint64_t fpa : 1; /**< Write 1 to set FPA interrupt enable */ 3270 uint64_t iob : 1; /**< Write 1 to set IOB interrupt enable */ 3271 uint64_t mio : 1; /**< Write 1 to set MIO boot interrupt enable */ 3272 uint64_t nand : 1; /**< Write 1 to set NAND Flash Controller interrupt 3273 enable */ 3274 uint64_t mii1 : 1; /**< Write 1 to set RGMII/MII/MIX Interface 1 Interrupt 3275 enable */ 3276 uint64_t reserved_6_17 : 12; 3277 uint64_t wdog : 6; /**< Write 1s to set Watchdog summary interrupt enable */ 3278#else 3279 uint64_t wdog : 6; 3280 uint64_t reserved_6_17 : 12; 3281 uint64_t mii1 : 1; 3282 uint64_t nand : 1; 3283 uint64_t mio : 1; 3284 uint64_t iob : 1; 3285 uint64_t fpa : 1; 3286 uint64_t pow : 1; 3287 uint64_t l2c : 1; 3288 uint64_t ipd : 1; 3289 uint64_t pip : 1; 3290 uint64_t pko : 1; 3291 uint64_t zip : 1; 3292 uint64_t tim : 1; 3293 uint64_t rad : 1; 3294 uint64_t key : 1; 3295 uint64_t dfa : 1; 3296 uint64_t usb : 1; 3297 uint64_t sli : 1; 3298 uint64_t dpi : 1; 3299 uint64_t agx0 : 1; 3300 uint64_t reserved_37_45 : 9; 3301 uint64_t agl : 1; 3302 uint64_t ptp : 1; 3303 uint64_t pem0 : 1; 3304 uint64_t pem1 : 1; 3305 uint64_t srio0 : 1; 3306 uint64_t srio1 : 1; 3307 uint64_t lmc0 : 1; 3308 uint64_t reserved_53_55 : 3; 3309 uint64_t dfm : 1; 3310 uint64_t reserved_57_62 : 6; 3311 uint64_t rst : 1; 3312#endif 3313 } cn63xx; 3314 struct cvmx_ciu_intx_en4_1_w1s_cn63xx cn63xxp1; 3315}; 3316typedef union cvmx_ciu_intx_en4_1_w1s cvmx_ciu_intx_en4_1_w1s_t; 3317 3318/** 3319 * cvmx_ciu_int#_sum0 3320 */ 3321union cvmx_ciu_intx_sum0 3322{ 3323 uint64_t u64; 3324 struct cvmx_ciu_intx_sum0_s 3325 { 3326#if __BYTE_ORDER == __BIG_ENDIAN 3327 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt 3328 See MIO_BOOT_DMA_INT*, MIO_NDF_DMA_INT */ 3329 uint64_t mii : 1; /**< RGMII/MII/MIX Interface 0 Interrupt 3330 See MIX0_ISR */ 3331 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt 3332 See IPD_PORT_QOS_INT* */ 3333 uint64_t powiq : 1; /**< POW IQ interrupt 3334 See POW_IQ_INT */ 3335 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt 3336 See MIO_TWS1_INT */ 3337 uint64_t mpi : 1; /**< MPI/SPI interrupt */ 3338 uint64_t pcm : 1; /**< PCM/TDM interrupt */ 3339 uint64_t usb : 1; /**< USB EHCI or OHCI Interrupt 3340 See UAHC0_EHCI_USBSTS UAHC0_OHCI0_HCINTERRUPTSTATUS */ 3341 uint64_t timer : 4; /**< General timer interrupts 3342 Set any time the corresponding CIU timer expires */ 3343 uint64_t key_zero : 1; /**< Key Zeroization interrupt 3344 KEY_ZERO will be set when the external ZERO_KEYS 3345 pin is sampled high. KEY_ZERO is cleared by SW */ 3346 uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt 3347 Set any time PIP/IPD drops a packet */ 3348 uint64_t gmx_drp : 2; /**< GMX packet drop interrupt 3349 Set any time corresponding GMX drops a packet */ 3350 uint64_t trace : 1; /**< Trace buffer interrupt 3351 See TRA_INT_STATUS */ 3352 uint64_t rml : 1; /**< RML Interrupt 3353 This interrupt will assert if any bit within 3354 CIU_BLOCK_INT is asserted. */ 3355 uint64_t twsi : 1; /**< TWSI Interrupt 3356 See MIO_TWS0_INT */ 3357 uint64_t wdog_sum : 1; /**< SUM1&EN1 summary bit 3358 This read-only bit reads as a one whenever any 3359 CIU_INT_SUM1 bit is set and corresponding 3360 enable bit in CIU_INTx_EN is set, where x 3361 is the same as x in this CIU_INTx_SUM0. 3362 PPs use CIU_INTx_SUM0 where x=0-11 3363 PCIe/sRIO uses the CIU_INTx_SUM0 where x=32-33. 3364 Even INTx registers report WDOG to IP2 3365 Odd INTx registers report WDOG to IP3 3366 Note that WDOG_SUM only summarizes the SUM/EN1 3367 result and does not have a corresponding enable 3368 bit, so does not directly contribute to 3369 interrupts. */ 3370 uint64_t pci_msi : 4; /**< PCIe/sRIO MSI 3371 See SLI_MSI_RCVn for bit <40+n> */ 3372 uint64_t pci_int : 4; /**< PCIe INTA/B/C/D 3373 Refer to "Receiving Emulated INTA/INTB/ 3374 INTC/INTD" in the SLI chapter of the spec */ 3375 uint64_t uart : 2; /**< Two UART interrupts 3376 See MIO_UARTn_IIR[IID] for bit <34+n> */ 3377 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-11 3378 [33] is the or of <31:16> 3379 [32] is the or of <15:0> 3380 Two PCIe/sRIO internal interrupts for entries 32-33 3381 which equal CIU_PCI_INTA[INT] */ 3382 uint64_t gpio : 16; /**< 16 GPIO interrupts */ 3383 uint64_t workq : 16; /**< 16 work queue interrupts 3384 See POW_WQ_INT[WQ_INT] 3385 1 bit/group. A copy of the R/W1C bit in the POW. */ 3386#else 3387 uint64_t workq : 16; 3388 uint64_t gpio : 16; 3389 uint64_t mbox : 2; 3390 uint64_t uart : 2; 3391 uint64_t pci_int : 4; 3392 uint64_t pci_msi : 4; 3393 uint64_t wdog_sum : 1; 3394 uint64_t twsi : 1; 3395 uint64_t rml : 1; 3396 uint64_t trace : 1; 3397 uint64_t gmx_drp : 2; 3398 uint64_t ipd_drp : 1; 3399 uint64_t key_zero : 1; 3400 uint64_t timer : 4; 3401 uint64_t usb : 1; 3402 uint64_t pcm : 1; 3403 uint64_t mpi : 1; 3404 uint64_t twsi2 : 1; 3405 uint64_t powiq : 1; 3406 uint64_t ipdppthr : 1; 3407 uint64_t mii : 1; 3408 uint64_t bootdma : 1; 3409#endif 3410 } s; 3411 struct cvmx_ciu_intx_sum0_cn30xx 3412 { 3413#if __BYTE_ORDER == __BIG_ENDIAN 3414 uint64_t reserved_59_63 : 5; 3415 uint64_t mpi : 1; /**< MPI/SPI interrupt */ 3416 uint64_t pcm : 1; /**< PCM/TDM interrupt */ 3417 uint64_t usb : 1; /**< USB interrupt */ 3418 uint64_t timer : 4; /**< General timer interrupts */ 3419 uint64_t reserved_51_51 : 1; 3420 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */ 3421 uint64_t reserved_49_49 : 1; 3422 uint64_t gmx_drp : 1; /**< GMX packet drop */ 3423 uint64_t reserved_47_47 : 1; 3424 uint64_t rml : 1; /**< RML Interrupt */ 3425 uint64_t twsi : 1; /**< TWSI Interrupt */ 3426 uint64_t wdog_sum : 1; /**< Watchdog summary 3427 PPs use CIU_INTx_SUM0 where x=0-1. 3428 PCI uses the CIU_INTx_SUM0 where x=32. 3429 Even INTx registers report WDOG to IP2 3430 Odd INTx registers report WDOG to IP3 */ 3431 uint64_t pci_msi : 4; /**< PCI MSI 3432 [43] is the or of <63:48> 3433 [42] is the or of <47:32> 3434 [41] is the or of <31:16> 3435 [40] is the or of <15:0> */ 3436 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */ 3437 uint64_t uart : 2; /**< Two UART interrupts */ 3438 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-31 3439 [33] is the or of <31:16> 3440 [32] is the or of <15:0> 3441 Two PCI internal interrupts for entry 32 3442 CIU_PCI_INTA */ 3443 uint64_t gpio : 16; /**< 16 GPIO interrupts */ 3444 uint64_t workq : 16; /**< 16 work queue interrupts 3445 1 bit/group. A copy of the R/W1C bit in the POW. */ 3446#else 3447 uint64_t workq : 16; 3448 uint64_t gpio : 16; 3449 uint64_t mbox : 2; 3450 uint64_t uart : 2; 3451 uint64_t pci_int : 4; 3452 uint64_t pci_msi : 4; 3453 uint64_t wdog_sum : 1; 3454 uint64_t twsi : 1; 3455 uint64_t rml : 1; 3456 uint64_t reserved_47_47 : 1; 3457 uint64_t gmx_drp : 1; 3458 uint64_t reserved_49_49 : 1; 3459 uint64_t ipd_drp : 1; 3460 uint64_t reserved_51_51 : 1; 3461 uint64_t timer : 4; 3462 uint64_t usb : 1; 3463 uint64_t pcm : 1; 3464 uint64_t mpi : 1; 3465 uint64_t reserved_59_63 : 5; 3466#endif 3467 } cn30xx; 3468 struct cvmx_ciu_intx_sum0_cn31xx 3469 { 3470#if __BYTE_ORDER == __BIG_ENDIAN 3471 uint64_t reserved_59_63 : 5; 3472 uint64_t mpi : 1; /**< MPI/SPI interrupt */ 3473 uint64_t pcm : 1; /**< PCM/TDM interrupt */ 3474 uint64_t usb : 1; /**< USB interrupt */ 3475 uint64_t timer : 4; /**< General timer interrupts */ 3476 uint64_t reserved_51_51 : 1; 3477 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */ 3478 uint64_t reserved_49_49 : 1; 3479 uint64_t gmx_drp : 1; /**< GMX packet drop */ 3480 uint64_t trace : 1; /**< L2C has the CMB trace buffer */ 3481 uint64_t rml : 1; /**< RML Interrupt */ 3482 uint64_t twsi : 1; /**< TWSI Interrupt */ 3483 uint64_t wdog_sum : 1; /**< Watchdog summary 3484 PPs use CIU_INTx_SUM0 where x=0-3. 3485 PCI uses the CIU_INTx_SUM0 where x=32. 3486 Even INTx registers report WDOG to IP2 3487 Odd INTx registers report WDOG to IP3 */ 3488 uint64_t pci_msi : 4; /**< PCI MSI 3489 [43] is the or of <63:48> 3490 [42] is the or of <47:32> 3491 [41] is the or of <31:16> 3492 [40] is the or of <15:0> */ 3493 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */ 3494 uint64_t uart : 2; /**< Two UART interrupts */ 3495 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-31 3496 [33] is the or of <31:16> 3497 [32] is the or of <15:0> 3498 Two PCI internal interrupts for entry 32 3499 CIU_PCI_INTA */ 3500 uint64_t gpio : 16; /**< 16 GPIO interrupts */ 3501 uint64_t workq : 16; /**< 16 work queue interrupts 3502 1 bit/group. A copy of the R/W1C bit in the POW. */ 3503#else 3504 uint64_t workq : 16; 3505 uint64_t gpio : 16; 3506 uint64_t mbox : 2; 3507 uint64_t uart : 2; 3508 uint64_t pci_int : 4; 3509 uint64_t pci_msi : 4; 3510 uint64_t wdog_sum : 1; 3511 uint64_t twsi : 1; 3512 uint64_t rml : 1; 3513 uint64_t trace : 1; 3514 uint64_t gmx_drp : 1; 3515 uint64_t reserved_49_49 : 1; 3516 uint64_t ipd_drp : 1; 3517 uint64_t reserved_51_51 : 1; 3518 uint64_t timer : 4; 3519 uint64_t usb : 1; 3520 uint64_t pcm : 1; 3521 uint64_t mpi : 1; 3522 uint64_t reserved_59_63 : 5; 3523#endif 3524 } cn31xx; 3525 struct cvmx_ciu_intx_sum0_cn38xx 3526 { 3527#if __BYTE_ORDER == __BIG_ENDIAN 3528 uint64_t reserved_56_63 : 8; 3529 uint64_t timer : 4; /**< General timer interrupts */ 3530 uint64_t key_zero : 1; /**< Key Zeroization interrupt 3531 KEY_ZERO will be set when the external ZERO_KEYS 3532 pin is sampled high. KEY_ZERO is cleared by SW */ 3533 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */ 3534 uint64_t gmx_drp : 2; /**< GMX packet drop */ 3535 uint64_t trace : 1; /**< L2C has the CMB trace buffer */ 3536 uint64_t rml : 1; /**< RML Interrupt */ 3537 uint64_t twsi : 1; /**< TWSI Interrupt */ 3538 uint64_t wdog_sum : 1; /**< Watchdog summary 3539 PPs use CIU_INTx_SUM0 where x=0-31. 3540 PCI uses the CIU_INTx_SUM0 where x=32. 3541 Even INTx registers report WDOG to IP2 3542 Odd INTx registers report WDOG to IP3 */ 3543 uint64_t pci_msi : 4; /**< PCI MSI 3544 [43] is the or of <63:48> 3545 [42] is the or of <47:32> 3546 [41] is the or of <31:16> 3547 [40] is the or of <15:0> */ 3548 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */ 3549 uint64_t uart : 2; /**< Two UART interrupts */ 3550 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-31 3551 [33] is the or of <31:16> 3552 [32] is the or of <15:0> 3553 Two PCI internal interrupts for entry 32 3554 CIU_PCI_INTA */ 3555 uint64_t gpio : 16; /**< 16 GPIO interrupts */ 3556 uint64_t workq : 16; /**< 16 work queue interrupts 3557 1 bit/group. A copy of the R/W1C bit in the POW. */ 3558#else 3559 uint64_t workq : 16; 3560 uint64_t gpio : 16; 3561 uint64_t mbox : 2; 3562 uint64_t uart : 2; 3563 uint64_t pci_int : 4; 3564 uint64_t pci_msi : 4; 3565 uint64_t wdog_sum : 1; 3566 uint64_t twsi : 1; 3567 uint64_t rml : 1; 3568 uint64_t trace : 1; 3569 uint64_t gmx_drp : 2; 3570 uint64_t ipd_drp : 1; 3571 uint64_t key_zero : 1; 3572 uint64_t timer : 4; 3573 uint64_t reserved_56_63 : 8; 3574#endif 3575 } cn38xx; 3576 struct cvmx_ciu_intx_sum0_cn38xx cn38xxp2; 3577 struct cvmx_ciu_intx_sum0_cn30xx cn50xx; 3578 struct cvmx_ciu_intx_sum0_cn52xx 3579 { 3580#if __BYTE_ORDER == __BIG_ENDIAN 3581 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt */ 3582 uint64_t mii : 1; /**< MII Interface Interrupt */ 3583 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt */ 3584 uint64_t powiq : 1; /**< POW IQ interrupt */ 3585 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt */ 3586 uint64_t reserved_57_58 : 2; 3587 uint64_t usb : 1; /**< USB Interrupt */ 3588 uint64_t timer : 4; /**< General timer interrupts */ 3589 uint64_t reserved_51_51 : 1; 3590 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */ 3591 uint64_t reserved_49_49 : 1; 3592 uint64_t gmx_drp : 1; /**< GMX packet drop */ 3593 uint64_t trace : 1; /**< L2C has the CMB trace buffer */ 3594 uint64_t rml : 1; /**< RML Interrupt */ 3595 uint64_t twsi : 1; /**< TWSI Interrupt */ 3596 uint64_t wdog_sum : 1; /**< SUM1&EN1 summary bit 3597 This read-only bit reads as a one whenever any 3598 CIU_INT_SUM1 bit is set and corresponding 3599 enable bit in CIU_INTx_EN is set, where x 3600 is the same as x in this CIU_INTx_SUM0. 3601 PPs use CIU_INTx_SUM0 where x=0-7. 3602 PCI uses the CIU_INTx_SUM0 where x=32. 3603 Even INTx registers report WDOG to IP2 3604 Odd INTx registers report WDOG to IP3 3605 Note that WDOG_SUM only summarizes the SUM/EN1 3606 result and does not have a corresponding enable 3607 bit, so does not directly contribute to 3608 interrupts. */ 3609 uint64_t pci_msi : 4; /**< PCI MSI 3610 Refer to "Receiving Message-Signalled 3611 Interrupts" in the PCIe chapter of the spec */ 3612 uint64_t pci_int : 4; /**< PCI INTA/B/C/D 3613 Refer to "Receiving Emulated INTA/INTB/ 3614 INTC/INTD" in the PCIe chapter of the spec */ 3615 uint64_t uart : 2; /**< Two UART interrupts */ 3616 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-7 3617 [33] is the or of <31:16> 3618 [32] is the or of <15:0> 3619 Two PCI internal interrupts for entry 32 3620 CIU_PCI_INTA */ 3621 uint64_t gpio : 16; /**< 16 GPIO interrupts */ 3622 uint64_t workq : 16; /**< 16 work queue interrupts 3623 1 bit/group. A copy of the R/W1C bit in the POW. */ 3624#else 3625 uint64_t workq : 16; 3626 uint64_t gpio : 16; 3627 uint64_t mbox : 2; 3628 uint64_t uart : 2; 3629 uint64_t pci_int : 4; 3630 uint64_t pci_msi : 4; 3631 uint64_t wdog_sum : 1; 3632 uint64_t twsi : 1; 3633 uint64_t rml : 1; 3634 uint64_t trace : 1; 3635 uint64_t gmx_drp : 1; 3636 uint64_t reserved_49_49 : 1; 3637 uint64_t ipd_drp : 1; 3638 uint64_t reserved_51_51 : 1; 3639 uint64_t timer : 4; 3640 uint64_t usb : 1; 3641 uint64_t reserved_57_58 : 2; 3642 uint64_t twsi2 : 1; 3643 uint64_t powiq : 1; 3644 uint64_t ipdppthr : 1; 3645 uint64_t mii : 1; 3646 uint64_t bootdma : 1; 3647#endif 3648 } cn52xx; 3649 struct cvmx_ciu_intx_sum0_cn52xx cn52xxp1; 3650 struct cvmx_ciu_intx_sum0_cn56xx 3651 { 3652#if __BYTE_ORDER == __BIG_ENDIAN 3653 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt */ 3654 uint64_t mii : 1; /**< MII Interface Interrupt */ 3655 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt */ 3656 uint64_t powiq : 1; /**< POW IQ interrupt */ 3657 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt */ 3658 uint64_t reserved_57_58 : 2; 3659 uint64_t usb : 1; /**< USB Interrupt */ 3660 uint64_t timer : 4; /**< General timer interrupts */ 3661 uint64_t key_zero : 1; /**< Key Zeroization interrupt 3662 KEY_ZERO will be set when the external ZERO_KEYS 3663 pin is sampled high. KEY_ZERO is cleared by SW */ 3664 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */ 3665 uint64_t gmx_drp : 2; /**< GMX packet drop */ 3666 uint64_t trace : 1; /**< L2C has the CMB trace buffer */ 3667 uint64_t rml : 1; /**< RML Interrupt */ 3668 uint64_t twsi : 1; /**< TWSI Interrupt */ 3669 uint64_t wdog_sum : 1; /**< Watchdog summary 3670 PPs use CIU_INTx_SUM0 where x=0-23. 3671 PCI uses the CIU_INTx_SUM0 where x=32. 3672 Even INTx registers report WDOG to IP2 3673 Odd INTx registers report WDOG to IP3 */ 3674 uint64_t pci_msi : 4; /**< PCI MSI 3675 Refer to "Receiving Message-Signalled 3676 Interrupts" in the PCIe chapter of the spec */ 3677 uint64_t pci_int : 4; /**< PCI INTA/B/C/D 3678 Refer to "Receiving Emulated INTA/INTB/ 3679 INTC/INTD" in the PCIe chapter of the spec */ 3680 uint64_t uart : 2; /**< Two UART interrupts */ 3681 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-23 3682 [33] is the or of <31:16> 3683 [32] is the or of <15:0> 3684 Two PCI internal interrupts for entry 32 3685 CIU_PCI_INTA */ 3686 uint64_t gpio : 16; /**< 16 GPIO interrupts */ 3687 uint64_t workq : 16; /**< 16 work queue interrupts 3688 1 bit/group. A copy of the R/W1C bit in the POW. */ 3689#else 3690 uint64_t workq : 16; 3691 uint64_t gpio : 16; 3692 uint64_t mbox : 2; 3693 uint64_t uart : 2; 3694 uint64_t pci_int : 4; 3695 uint64_t pci_msi : 4; 3696 uint64_t wdog_sum : 1; 3697 uint64_t twsi : 1; 3698 uint64_t rml : 1; 3699 uint64_t trace : 1; 3700 uint64_t gmx_drp : 2; 3701 uint64_t ipd_drp : 1; 3702 uint64_t key_zero : 1; 3703 uint64_t timer : 4; 3704 uint64_t usb : 1; 3705 uint64_t reserved_57_58 : 2; 3706 uint64_t twsi2 : 1; 3707 uint64_t powiq : 1; 3708 uint64_t ipdppthr : 1; 3709 uint64_t mii : 1; 3710 uint64_t bootdma : 1; 3711#endif 3712 } cn56xx; 3713 struct cvmx_ciu_intx_sum0_cn56xx cn56xxp1; 3714 struct cvmx_ciu_intx_sum0_cn38xx cn58xx; 3715 struct cvmx_ciu_intx_sum0_cn38xx cn58xxp1; 3716 struct cvmx_ciu_intx_sum0_cn52xx cn63xx; 3717 struct cvmx_ciu_intx_sum0_cn52xx cn63xxp1; 3718}; 3719typedef union cvmx_ciu_intx_sum0 cvmx_ciu_intx_sum0_t; 3720 3721/** 3722 * cvmx_ciu_int#_sum4 3723 */ 3724union cvmx_ciu_intx_sum4 3725{ 3726 uint64_t u64; 3727 struct cvmx_ciu_intx_sum4_s 3728 { 3729#if __BYTE_ORDER == __BIG_ENDIAN 3730 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt 3731 See MIO_BOOT_DMA_INT*, MIO_NDF_DMA_INT */ 3732 uint64_t mii : 1; /**< RGMII/MII/MIX Interface 0 Interrupt 3733 See MIX0_ISR */ 3734 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt 3735 See IPD_PORT_QOS_INT* */ 3736 uint64_t powiq : 1; /**< POW IQ interrupt 3737 See POW_IQ_INT */ 3738 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt 3739 See MIO_TWS1_INT */ 3740 uint64_t mpi : 1; /**< MPI/SPI interrupt */ 3741 uint64_t pcm : 1; /**< PCM/TDM interrupt */ 3742 uint64_t usb : 1; /**< USB EHCI or OHCI Interrupt 3743 See UAHC0_EHCI_USBSTS UAHC0_OHCI0_HCINTERRUPTSTATUS */ 3744 uint64_t timer : 4; /**< General timer interrupts 3745 Set any time the corresponding CIU timer expires */ 3746 uint64_t key_zero : 1; /**< Key Zeroization interrupt 3747 KEY_ZERO will be set when the external ZERO_KEYS 3748 pin is sampled high. KEY_ZERO is cleared by SW */ 3749 uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt 3750 Set any time PIP/IPD drops a packet */ 3751 uint64_t gmx_drp : 2; /**< GMX packet drop interrupt 3752 Set any time corresponding GMX drops a packet */ 3753 uint64_t trace : 1; /**< Trace buffer interrupt 3754 See TRA_INT_STATUS */ 3755 uint64_t rml : 1; /**< RML Interrupt 3756 This bit is set when any bit is set in 3757 CIU_BLOCK_INT. */ 3758 uint64_t twsi : 1; /**< TWSI Interrupt 3759 See MIO_TWS0_INT */ 3760 uint64_t wdog_sum : 1; /**< SUM1&EN4_1 summary bit 3761 This read-only bit reads as a one whenever any 3762 CIU_INT_SUM1 bit is set and corresponding 3763 enable bit in CIU_INTx_EN4_1 is set, where x 3764 is the same as x in this CIU_INTx_SUM4. 3765 PPs use CIU_INTx_SUM4 for IP4, where x=PPid. 3766 Note that WDOG_SUM only summarizes the SUM/EN4_1 3767 result and does not have a corresponding enable 3768 bit, so does not directly contribute to 3769 interrupts. */ 3770 uint64_t pci_msi : 4; /**< PCIe/sRIO MSI 3771 See SLI_MSI_RCVn for bit <40+n> */ 3772 uint64_t pci_int : 4; /**< PCIe INTA/B/C/D 3773 Refer to "Receiving Emulated INTA/INTB/ 3774 INTC/INTD" in the SLI chapter of the spec */ 3775 uint64_t uart : 2; /**< Two UART interrupts 3776 See MIO_UARTn_IIR[IID] for bit <34+n> */ 3777 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-5 3778 [33] is the or of <31:16> 3779 [32] is the or of <15:0> */ 3780 uint64_t gpio : 16; /**< 16 GPIO interrupts */ 3781 uint64_t workq : 16; /**< 16 work queue interrupts 3782 See POW_WQ_INT[WQ_INT] 3783 1 bit/group. A copy of the R/W1C bit in the POW. */ 3784#else 3785 uint64_t workq : 16; 3786 uint64_t gpio : 16; 3787 uint64_t mbox : 2; 3788 uint64_t uart : 2; 3789 uint64_t pci_int : 4; 3790 uint64_t pci_msi : 4; 3791 uint64_t wdog_sum : 1; 3792 uint64_t twsi : 1; 3793 uint64_t rml : 1; 3794 uint64_t trace : 1; 3795 uint64_t gmx_drp : 2; 3796 uint64_t ipd_drp : 1; 3797 uint64_t key_zero : 1; 3798 uint64_t timer : 4; 3799 uint64_t usb : 1; 3800 uint64_t pcm : 1; 3801 uint64_t mpi : 1; 3802 uint64_t twsi2 : 1; 3803 uint64_t powiq : 1; 3804 uint64_t ipdppthr : 1; 3805 uint64_t mii : 1; 3806 uint64_t bootdma : 1; 3807#endif 3808 } s; 3809 struct cvmx_ciu_intx_sum4_cn50xx 3810 { 3811#if __BYTE_ORDER == __BIG_ENDIAN 3812 uint64_t reserved_59_63 : 5; 3813 uint64_t mpi : 1; /**< MPI/SPI interrupt */ 3814 uint64_t pcm : 1; /**< PCM/TDM interrupt */ 3815 uint64_t usb : 1; /**< USB interrupt */ 3816 uint64_t timer : 4; /**< General timer interrupts */ 3817 uint64_t reserved_51_51 : 1; 3818 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */ 3819 uint64_t reserved_49_49 : 1; 3820 uint64_t gmx_drp : 1; /**< GMX packet drop */ 3821 uint64_t reserved_47_47 : 1; 3822 uint64_t rml : 1; /**< RML Interrupt */ 3823 uint64_t twsi : 1; /**< TWSI Interrupt */ 3824 uint64_t wdog_sum : 1; /**< Watchdog summary 3825 PPs use CIU_INTx_SUM4 where x=0-1. */ 3826 uint64_t pci_msi : 4; /**< PCI MSI 3827 [43] is the or of <63:48> 3828 [42] is the or of <47:32> 3829 [41] is the or of <31:16> 3830 [40] is the or of <15:0> */ 3831 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */ 3832 uint64_t uart : 2; /**< Two UART interrupts */ 3833 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-31 3834 [33] is the or of <31:16> 3835 [32] is the or of <15:0> 3836 Two PCI internal interrupts for entry 32 3837 CIU_PCI_INTA */ 3838 uint64_t gpio : 16; /**< 16 GPIO interrupts */ 3839 uint64_t workq : 16; /**< 16 work queue interrupts 3840 1 bit/group. A copy of the R/W1C bit in the POW. */ 3841#else 3842 uint64_t workq : 16; 3843 uint64_t gpio : 16; 3844 uint64_t mbox : 2; 3845 uint64_t uart : 2; 3846 uint64_t pci_int : 4; 3847 uint64_t pci_msi : 4; 3848 uint64_t wdog_sum : 1; 3849 uint64_t twsi : 1; 3850 uint64_t rml : 1; 3851 uint64_t reserved_47_47 : 1; 3852 uint64_t gmx_drp : 1; 3853 uint64_t reserved_49_49 : 1; 3854 uint64_t ipd_drp : 1; 3855 uint64_t reserved_51_51 : 1; 3856 uint64_t timer : 4; 3857 uint64_t usb : 1; 3858 uint64_t pcm : 1; 3859 uint64_t mpi : 1; 3860 uint64_t reserved_59_63 : 5; 3861#endif 3862 } cn50xx; 3863 struct cvmx_ciu_intx_sum4_cn52xx 3864 { 3865#if __BYTE_ORDER == __BIG_ENDIAN 3866 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt */ 3867 uint64_t mii : 1; /**< MII Interface Interrupt */ 3868 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt */ 3869 uint64_t powiq : 1; /**< POW IQ interrupt */ 3870 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt */ 3871 uint64_t reserved_57_58 : 2; 3872 uint64_t usb : 1; /**< USB Interrupt */ 3873 uint64_t timer : 4; /**< General timer interrupts */ 3874 uint64_t reserved_51_51 : 1; 3875 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */ 3876 uint64_t reserved_49_49 : 1; 3877 uint64_t gmx_drp : 1; /**< GMX packet drop */ 3878 uint64_t trace : 1; /**< L2C has the CMB trace buffer */ 3879 uint64_t rml : 1; /**< RML Interrupt */ 3880 uint64_t twsi : 1; /**< TWSI Interrupt */ 3881 uint64_t wdog_sum : 1; /**< SUM1&EN4_1 summary bit 3882 This read-only bit reads as a one whenever any 3883 CIU_INT_SUM1 bit is set and corresponding 3884 enable bit in CIU_INTx_EN4_1 is set, where x 3885 is the same as x in this CIU_INTx_SUM4. 3886 PPs use CIU_INTx_SUM4 for IP4, where x=PPid. 3887 Note that WDOG_SUM only summarizes the SUM/EN4_1 3888 result and does not have a corresponding enable 3889 bit, so does not directly contribute to 3890 interrupts. */ 3891 uint64_t pci_msi : 4; /**< PCI MSI 3892 Refer to "Receiving Message-Signalled 3893 Interrupts" in the PCIe chapter of the spec */ 3894 uint64_t pci_int : 4; /**< PCI INTA/B/C/D 3895 Refer to "Receiving Emulated INTA/INTB/ 3896 INTC/INTD" in the PCIe chapter of the spec */ 3897 uint64_t uart : 2; /**< Two UART interrupts */ 3898 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-3 3899 [33] is the or of <31:16> 3900 [32] is the or of <15:0> */ 3901 uint64_t gpio : 16; /**< 16 GPIO interrupts */ 3902 uint64_t workq : 16; /**< 16 work queue interrupts 3903 1 bit/group. A copy of the R/W1C bit in the POW. */ 3904#else 3905 uint64_t workq : 16; 3906 uint64_t gpio : 16; 3907 uint64_t mbox : 2; 3908 uint64_t uart : 2; 3909 uint64_t pci_int : 4; 3910 uint64_t pci_msi : 4; 3911 uint64_t wdog_sum : 1; 3912 uint64_t twsi : 1; 3913 uint64_t rml : 1; 3914 uint64_t trace : 1; 3915 uint64_t gmx_drp : 1; 3916 uint64_t reserved_49_49 : 1; 3917 uint64_t ipd_drp : 1; 3918 uint64_t reserved_51_51 : 1; 3919 uint64_t timer : 4; 3920 uint64_t usb : 1; 3921 uint64_t reserved_57_58 : 2; 3922 uint64_t twsi2 : 1; 3923 uint64_t powiq : 1; 3924 uint64_t ipdppthr : 1; 3925 uint64_t mii : 1; 3926 uint64_t bootdma : 1; 3927#endif 3928 } cn52xx; 3929 struct cvmx_ciu_intx_sum4_cn52xx cn52xxp1; 3930 struct cvmx_ciu_intx_sum4_cn56xx 3931 { 3932#if __BYTE_ORDER == __BIG_ENDIAN 3933 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt */ 3934 uint64_t mii : 1; /**< MII Interface Interrupt */ 3935 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt */ 3936 uint64_t powiq : 1; /**< POW IQ interrupt */ 3937 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt */ 3938 uint64_t reserved_57_58 : 2; 3939 uint64_t usb : 1; /**< USB Interrupt */ 3940 uint64_t timer : 4; /**< General timer interrupts */ 3941 uint64_t key_zero : 1; /**< Key Zeroization interrupt 3942 KEY_ZERO will be set when the external ZERO_KEYS 3943 pin is sampled high. KEY_ZERO is cleared by SW */ 3944 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */ 3945 uint64_t gmx_drp : 2; /**< GMX packet drop */ 3946 uint64_t trace : 1; /**< L2C has the CMB trace buffer */ 3947 uint64_t rml : 1; /**< RML Interrupt */ 3948 uint64_t twsi : 1; /**< TWSI Interrupt */ 3949 uint64_t wdog_sum : 1; /**< Watchdog summary 3950 These registers report WDOG to IP4 */ 3951 uint64_t pci_msi : 4; /**< PCI MSI 3952 Refer to "Receiving Message-Signalled 3953 Interrupts" in the PCIe chapter of the spec */ 3954 uint64_t pci_int : 4; /**< PCI INTA/B/C/D 3955 Refer to "Receiving Emulated INTA/INTB/ 3956 INTC/INTD" in the PCIe chapter of the spec */ 3957 uint64_t uart : 2; /**< Two UART interrupts */ 3958 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-11 3959 [33] is the or of <31:16> 3960 [32] is the or of <15:0> */ 3961 uint64_t gpio : 16; /**< 16 GPIO interrupts */ 3962 uint64_t workq : 16; /**< 16 work queue interrupts 3963 1 bit/group. A copy of the R/W1C bit in the POW. */ 3964#else 3965 uint64_t workq : 16; 3966 uint64_t gpio : 16; 3967 uint64_t mbox : 2; 3968 uint64_t uart : 2; 3969 uint64_t pci_int : 4; 3970 uint64_t pci_msi : 4; 3971 uint64_t wdog_sum : 1; 3972 uint64_t twsi : 1; 3973 uint64_t rml : 1; 3974 uint64_t trace : 1; 3975 uint64_t gmx_drp : 2; 3976 uint64_t ipd_drp : 1; 3977 uint64_t key_zero : 1; 3978 uint64_t timer : 4; 3979 uint64_t usb : 1; 3980 uint64_t reserved_57_58 : 2; 3981 uint64_t twsi2 : 1; 3982 uint64_t powiq : 1; 3983 uint64_t ipdppthr : 1; 3984 uint64_t mii : 1; 3985 uint64_t bootdma : 1; 3986#endif 3987 } cn56xx; 3988 struct cvmx_ciu_intx_sum4_cn56xx cn56xxp1; 3989 struct cvmx_ciu_intx_sum4_cn58xx 3990 { 3991#if __BYTE_ORDER == __BIG_ENDIAN 3992 uint64_t reserved_56_63 : 8; 3993 uint64_t timer : 4; /**< General timer interrupts */ 3994 uint64_t key_zero : 1; /**< Key Zeroization interrupt 3995 KEY_ZERO will be set when the external ZERO_KEYS 3996 pin is sampled high. KEY_ZERO is cleared by SW */ 3997 uint64_t ipd_drp : 1; /**< IPD QOS packet drop */ 3998 uint64_t gmx_drp : 2; /**< GMX packet drop */ 3999 uint64_t trace : 1; /**< L2C has the CMB trace buffer */ 4000 uint64_t rml : 1; /**< RML Interrupt */ 4001 uint64_t twsi : 1; /**< TWSI Interrupt */ 4002 uint64_t wdog_sum : 1; /**< Watchdog summary 4003 These registers report WDOG to IP4 */ 4004 uint64_t pci_msi : 4; /**< PCI MSI 4005 [43] is the or of <63:48> 4006 [42] is the or of <47:32> 4007 [41] is the or of <31:16> 4008 [40] is the or of <15:0> */ 4009 uint64_t pci_int : 4; /**< PCI INTA/B/C/D */ 4010 uint64_t uart : 2; /**< Two UART interrupts */ 4011 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-31 4012 [33] is the or of <31:16> 4013 [32] is the or of <15:0> 4014 Two PCI internal interrupts for entry 32 4015 CIU_PCI_INTA */ 4016 uint64_t gpio : 16; /**< 16 GPIO interrupts */ 4017 uint64_t workq : 16; /**< 16 work queue interrupts 4018 1 bit/group. A copy of the R/W1C bit in the POW. */ 4019#else 4020 uint64_t workq : 16; 4021 uint64_t gpio : 16; 4022 uint64_t mbox : 2; 4023 uint64_t uart : 2; 4024 uint64_t pci_int : 4; 4025 uint64_t pci_msi : 4; 4026 uint64_t wdog_sum : 1; 4027 uint64_t twsi : 1; 4028 uint64_t rml : 1; 4029 uint64_t trace : 1; 4030 uint64_t gmx_drp : 2; 4031 uint64_t ipd_drp : 1; 4032 uint64_t key_zero : 1; 4033 uint64_t timer : 4; 4034 uint64_t reserved_56_63 : 8; 4035#endif 4036 } cn58xx; 4037 struct cvmx_ciu_intx_sum4_cn58xx cn58xxp1; 4038 struct cvmx_ciu_intx_sum4_cn52xx cn63xx; 4039 struct cvmx_ciu_intx_sum4_cn52xx cn63xxp1; 4040}; 4041typedef union cvmx_ciu_intx_sum4 cvmx_ciu_intx_sum4_t; 4042 4043/** 4044 * cvmx_ciu_int33_sum0 4045 */ 4046union cvmx_ciu_int33_sum0 4047{ 4048 uint64_t u64; 4049 struct cvmx_ciu_int33_sum0_s 4050 { 4051#if __BYTE_ORDER == __BIG_ENDIAN 4052 uint64_t bootdma : 1; /**< Boot bus DMA engines Interrupt 4053 See MIO_BOOT_DMA_INT*, MIO_NDF_DMA_INT */ 4054 uint64_t mii : 1; /**< RGMII/MII/MIX Interface 0 Interrupt 4055 See MIX0_ISR */ 4056 uint64_t ipdppthr : 1; /**< IPD per-port counter threshold interrupt 4057 See IPD_PORT_QOS_INT* */ 4058 uint64_t powiq : 1; /**< POW IQ interrupt 4059 See POW_IQ_INT */ 4060 uint64_t twsi2 : 1; /**< 2nd TWSI Interrupt 4061 See MIO_TWS1_INT */ 4062 uint64_t reserved_57_58 : 2; 4063 uint64_t usb : 1; /**< USB EHCI or OHCI Interrupt 4064 See UAHC0_EHCI_USBSTS UAHC0_OHCI0_HCINTERRUPTSTATUS */ 4065 uint64_t timer : 4; /**< General timer interrupts 4066 Set any time the corresponding CIU timer expires */ 4067 uint64_t reserved_51_51 : 1; 4068 uint64_t ipd_drp : 1; /**< IPD QOS packet drop interrupt 4069 Set any time PIP/IPD drops a packet */ 4070 uint64_t reserved_49_49 : 1; 4071 uint64_t gmx_drp : 1; /**< GMX packet drop interrupt 4072 Set any time corresponding GMX drops a packet */ 4073 uint64_t trace : 1; /**< Trace buffer interrupt 4074 See TRA_INT_STATUS */ 4075 uint64_t rml : 1; /**< RML Interrupt 4076 This interrupt will assert if any bit within 4077 CIU_BLOCK_INT is asserted. */ 4078 uint64_t twsi : 1; /**< TWSI Interrupt 4079 See MIO_TWS0_INT */ 4080 uint64_t wdog_sum : 1; /**< SUM1&EN1 summary bit 4081 This read-only bit reads as a one whenever any 4082 CIU_INT_SUM1 bit is set and corresponding 4083 enable bit in CIU_INTx_EN is set, where x 4084 is the same as x in this CIU_INTx_SUM0. 4085 PPs use CIU_INTx_SUM0 where x=0-11. 4086 PCIe/sRIO uses the CIU_INTx_SUM0 where x=32-33. 4087 Even INTx registers report WDOG to IP2 4088 Odd INTx registers report WDOG to IP3 4089 Note that WDOG_SUM only summarizes the SUM/EN1 4090 result and does not have a corresponding enable 4091 bit, so does not directly contribute to 4092 interrupts. */ 4093 uint64_t pci_msi : 4; /**< PCIe/sRIO MSI 4094 See SLI_MSI_RCVn for bit <40+n> */ 4095 uint64_t pci_int : 4; /**< PCIe INTA/B/C/D 4096 Refer to "Receiving Emulated INTA/INTB/ 4097 INTC/INTD" in the SLI chapter of the spec */ 4098 uint64_t uart : 2; /**< Two UART interrupts 4099 See MIO_UARTn_IIR[IID] for bit <34+n> */ 4100 uint64_t mbox : 2; /**< A read-only copy of CIU_PCI_INTA[INT] */ 4101 uint64_t gpio : 16; /**< 16 GPIO interrupts */ 4102 uint64_t workq : 16; /**< 16 work queue interrupts 4103 See POW_WQ_INT[WQ_INT] 4104 1 bit/group. A copy of the R/W1C bit in the POW. */ 4105#else 4106 uint64_t workq : 16; 4107 uint64_t gpio : 16; 4108 uint64_t mbox : 2; 4109 uint64_t uart : 2; 4110 uint64_t pci_int : 4; 4111 uint64_t pci_msi : 4; 4112 uint64_t wdog_sum : 1; 4113 uint64_t twsi : 1; 4114 uint64_t rml : 1; 4115 uint64_t trace : 1; 4116 uint64_t gmx_drp : 1; 4117 uint64_t reserved_49_49 : 1; 4118 uint64_t ipd_drp : 1; 4119 uint64_t reserved_51_51 : 1; 4120 uint64_t timer : 4; 4121 uint64_t usb : 1; 4122 uint64_t reserved_57_58 : 2; 4123 uint64_t twsi2 : 1; 4124 uint64_t powiq : 1; 4125 uint64_t ipdppthr : 1; 4126 uint64_t mii : 1; 4127 uint64_t bootdma : 1; 4128#endif 4129 } s; 4130 struct cvmx_ciu_int33_sum0_s cn63xx; 4131 struct cvmx_ciu_int33_sum0_s cn63xxp1; 4132}; 4133typedef union cvmx_ciu_int33_sum0 cvmx_ciu_int33_sum0_t; 4134 4135/** 4136 * cvmx_ciu_int_dbg_sel 4137 */ 4138union cvmx_ciu_int_dbg_sel 4139{ 4140 uint64_t u64; 4141 struct cvmx_ciu_int_dbg_sel_s 4142 { 4143#if __BYTE_ORDER == __BIG_ENDIAN 4144 uint64_t reserved_19_63 : 45; 4145 uint64_t sel : 3; /**< Selects if all or the specific interrupt is 4146 presented on the debug port. 4147 0=erst_n 4148 1=start_bist 4149 2=toggle at sclk/2 freq 4150 3=All PP interrupt bits are ORed together 4151 4=Only the selected PP/IRQ is selected */ 4152 uint64_t reserved_10_15 : 6; 4153 uint64_t irq : 2; /**< Which IRQ to select 4154 0=IRQ2 4155 1=IRQ3 4156 2=IRQ4 */ 4157 uint64_t reserved_3_7 : 5; 4158 uint64_t pp : 3; /**< Which PP to select */ 4159#else 4160 uint64_t pp : 3; 4161 uint64_t reserved_3_7 : 5; 4162 uint64_t irq : 2; 4163 uint64_t reserved_10_15 : 6; 4164 uint64_t sel : 3; 4165 uint64_t reserved_19_63 : 45; 4166#endif 4167 } s; 4168 struct cvmx_ciu_int_dbg_sel_s cn63xx; 4169}; 4170typedef union cvmx_ciu_int_dbg_sel cvmx_ciu_int_dbg_sel_t; 4171 4172/** 4173 * cvmx_ciu_int_sum1 4174 */ 4175union cvmx_ciu_int_sum1 4176{ 4177 uint64_t u64; 4178 struct cvmx_ciu_int_sum1_s 4179 { 4180#if __BYTE_ORDER == __BIG_ENDIAN 4181 uint64_t rst : 1; /**< MIO RST interrupt 4182 See MIO_RST_INT */ 4183 uint64_t reserved_57_62 : 6; 4184 uint64_t dfm : 1; /**< DFM Interrupt 4185 See DFM_FNT_STAT */ 4186 uint64_t reserved_53_55 : 3; 4187 uint64_t lmc0 : 1; /**< LMC0 interrupt 4188 See LMC0_INT */ 4189 uint64_t srio1 : 1; /**< SRIO1 interrupt 4190 See SRIO1_INT_REG */ 4191 uint64_t srio0 : 1; /**< SRIO0 interrupt 4192 See SRIO0_INT_REG */ 4193 uint64_t pem1 : 1; /**< PEM1 interrupt 4194 See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */ 4195 uint64_t pem0 : 1; /**< PEM0 interrupt 4196 See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */ 4197 uint64_t ptp : 1; /**< PTP interrupt 4198 Set when HW decrements MIO_PTP_EVT_CNT to zero */ 4199 uint64_t agl : 1; /**< AGL interrupt 4200 See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */ 4201 uint64_t reserved_37_45 : 9; 4202 uint64_t agx0 : 1; /**< GMX0 interrupt 4203 See GMX0_RX*_INT_REG, GMX0_TX_INT_REG, 4204 PCS0_INT*_REG, PCSX0_INT_REG */ 4205 uint64_t dpi : 1; /**< DPI interrupt 4206 See DPI_INT_REG */ 4207 uint64_t sli : 1; /**< SLI interrupt 4208 See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */ 4209 uint64_t usb : 1; /**< USB UCTL0 interrupt 4210 See UCTL0_INT_REG */ 4211 uint64_t dfa : 1; /**< DFA interrupt 4212 See DFA_ERROR */ 4213 uint64_t key : 1; /**< KEY interrupt 4214 See KEY_INT_SUM */ 4215 uint64_t rad : 1; /**< RAD interrupt 4216 See RAD_REG_ERROR */ 4217 uint64_t tim : 1; /**< TIM interrupt 4218 See TIM_REG_ERROR */ 4219 uint64_t zip : 1; /**< ZIP interrupt 4220 See ZIP_ERROR */ 4221 uint64_t pko : 1; /**< PKO interrupt 4222 See PKO_REG_ERROR */ 4223 uint64_t pip : 1; /**< PIP interrupt 4224 See PIP_INT_REG */ 4225 uint64_t ipd : 1; /**< IPD interrupt 4226 See IPD_INT_SUM */ 4227 uint64_t l2c : 1; /**< L2C interrupt 4228 See L2C_INT_REG */ 4229 uint64_t pow : 1; /**< POW err interrupt 4230 See POW_ECC_ERR */ 4231 uint64_t fpa : 1; /**< FPA interrupt 4232 See FPA_INT_SUM */ 4233 uint64_t iob : 1; /**< IOB interrupt 4234 See IOB_INT_SUM */ 4235 uint64_t mio : 1; /**< MIO boot interrupt 4236 See MIO_BOOT_ERR */ 4237 uint64_t nand : 1; /**< NAND Flash Controller interrupt 4238 See NDF_INT */ 4239 uint64_t mii1 : 1; /**< RGMII/MII/MIX Interface 1 Interrupt 4240 See MIX1_ISR */ 4241 uint64_t usb1 : 1; /**< Second USB Interrupt */ 4242 uint64_t uart2 : 1; /**< Third UART interrupt */ 4243 uint64_t wdog : 16; /**< 6 watchdog interrupts */ 4244#else 4245 uint64_t wdog : 16; 4246 uint64_t uart2 : 1; 4247 uint64_t usb1 : 1; 4248 uint64_t mii1 : 1; 4249 uint64_t nand : 1; 4250 uint64_t mio : 1; 4251 uint64_t iob : 1; 4252 uint64_t fpa : 1; 4253 uint64_t pow : 1; 4254 uint64_t l2c : 1; 4255 uint64_t ipd : 1; 4256 uint64_t pip : 1; 4257 uint64_t pko : 1; 4258 uint64_t zip : 1; 4259 uint64_t tim : 1; 4260 uint64_t rad : 1; 4261 uint64_t key : 1; 4262 uint64_t dfa : 1; 4263 uint64_t usb : 1; 4264 uint64_t sli : 1; 4265 uint64_t dpi : 1; 4266 uint64_t agx0 : 1; 4267 uint64_t reserved_37_45 : 9; 4268 uint64_t agl : 1; 4269 uint64_t ptp : 1; 4270 uint64_t pem0 : 1; 4271 uint64_t pem1 : 1; 4272 uint64_t srio0 : 1; 4273 uint64_t srio1 : 1; 4274 uint64_t lmc0 : 1; 4275 uint64_t reserved_53_55 : 3; 4276 uint64_t dfm : 1; 4277 uint64_t reserved_57_62 : 6; 4278 uint64_t rst : 1; 4279#endif 4280 } s; 4281 struct cvmx_ciu_int_sum1_cn30xx 4282 { 4283#if __BYTE_ORDER == __BIG_ENDIAN 4284 uint64_t reserved_1_63 : 63; 4285 uint64_t wdog : 1; /**< 1 watchdog interrupt */ 4286#else 4287 uint64_t wdog : 1; 4288 uint64_t reserved_1_63 : 63; 4289#endif 4290 } cn30xx; 4291 struct cvmx_ciu_int_sum1_cn31xx 4292 { 4293#if __BYTE_ORDER == __BIG_ENDIAN 4294 uint64_t reserved_2_63 : 62; 4295 uint64_t wdog : 2; /**< 2 watchdog interrupts */ 4296#else 4297 uint64_t wdog : 2; 4298 uint64_t reserved_2_63 : 62; 4299#endif 4300 } cn31xx; 4301 struct cvmx_ciu_int_sum1_cn38xx 4302 { 4303#if __BYTE_ORDER == __BIG_ENDIAN 4304 uint64_t reserved_16_63 : 48; 4305 uint64_t wdog : 16; /**< 16 watchdog interrupts */ 4306#else 4307 uint64_t wdog : 16; 4308 uint64_t reserved_16_63 : 48; 4309#endif 4310 } cn38xx; 4311 struct cvmx_ciu_int_sum1_cn38xx cn38xxp2; 4312 struct cvmx_ciu_int_sum1_cn31xx cn50xx; 4313 struct cvmx_ciu_int_sum1_cn52xx 4314 { 4315#if __BYTE_ORDER == __BIG_ENDIAN 4316 uint64_t reserved_20_63 : 44; 4317 uint64_t nand : 1; /**< NAND Flash Controller */ 4318 uint64_t mii1 : 1; /**< Second MII Interrupt */ 4319 uint64_t usb1 : 1; /**< Second USB Interrupt */ 4320 uint64_t uart2 : 1; /**< Third UART interrupt */ 4321 uint64_t reserved_4_15 : 12; 4322 uint64_t wdog : 4; /**< 4 watchdog interrupts */ 4323#else 4324 uint64_t wdog : 4; 4325 uint64_t reserved_4_15 : 12; 4326 uint64_t uart2 : 1; 4327 uint64_t usb1 : 1; 4328 uint64_t mii1 : 1; 4329 uint64_t nand : 1; 4330 uint64_t reserved_20_63 : 44; 4331#endif 4332 } cn52xx; 4333 struct cvmx_ciu_int_sum1_cn52xxp1 4334 { 4335#if __BYTE_ORDER == __BIG_ENDIAN 4336 uint64_t reserved_19_63 : 45; 4337 uint64_t mii1 : 1; /**< Second MII Interrupt */ 4338 uint64_t usb1 : 1; /**< Second USB Interrupt */ 4339 uint64_t uart2 : 1; /**< Third UART interrupt */ 4340 uint64_t reserved_4_15 : 12; 4341 uint64_t wdog : 4; /**< 4 watchdog interrupts */ 4342#else 4343 uint64_t wdog : 4; 4344 uint64_t reserved_4_15 : 12; 4345 uint64_t uart2 : 1; 4346 uint64_t usb1 : 1; 4347 uint64_t mii1 : 1; 4348 uint64_t reserved_19_63 : 45; 4349#endif 4350 } cn52xxp1; 4351 struct cvmx_ciu_int_sum1_cn56xx 4352 { 4353#if __BYTE_ORDER == __BIG_ENDIAN 4354 uint64_t reserved_12_63 : 52; 4355 uint64_t wdog : 12; /**< 12 watchdog interrupts */ 4356#else 4357 uint64_t wdog : 12; 4358 uint64_t reserved_12_63 : 52; 4359#endif 4360 } cn56xx; 4361 struct cvmx_ciu_int_sum1_cn56xx cn56xxp1; 4362 struct cvmx_ciu_int_sum1_cn38xx cn58xx; 4363 struct cvmx_ciu_int_sum1_cn38xx cn58xxp1; 4364 struct cvmx_ciu_int_sum1_cn63xx 4365 { 4366#if __BYTE_ORDER == __BIG_ENDIAN 4367 uint64_t rst : 1; /**< MIO RST interrupt 4368 See MIO_RST_INT */ 4369 uint64_t reserved_57_62 : 6; 4370 uint64_t dfm : 1; /**< DFM Interrupt 4371 See DFM_FNT_STAT */ 4372 uint64_t reserved_53_55 : 3; 4373 uint64_t lmc0 : 1; /**< LMC0 interrupt 4374 See LMC0_INT */ 4375 uint64_t srio1 : 1; /**< SRIO1 interrupt 4376 See SRIO1_INT_REG, SRIO1_INT2_REG */ 4377 uint64_t srio0 : 1; /**< SRIO0 interrupt 4378 See SRIO0_INT_REG, SRIO0_INT2_REG */ 4379 uint64_t pem1 : 1; /**< PEM1 interrupt 4380 See PEM1_INT_SUM (enabled by PEM1_INT_ENB) */ 4381 uint64_t pem0 : 1; /**< PEM0 interrupt 4382 See PEM0_INT_SUM (enabled by PEM0_INT_ENB) */ 4383 uint64_t ptp : 1; /**< PTP interrupt 4384 Set when HW decrements MIO_PTP_EVT_CNT to zero */ 4385 uint64_t agl : 1; /**< AGL interrupt 4386 See AGL_GMX_RX*_INT_REG, AGL_GMX_TX_INT_REG */ 4387 uint64_t reserved_37_45 : 9; 4388 uint64_t agx0 : 1; /**< GMX0 interrupt 4389 See GMX0_RX*_INT_REG, GMX0_TX_INT_REG, 4390 PCS0_INT*_REG, PCSX0_INT_REG */ 4391 uint64_t dpi : 1; /**< DPI interrupt 4392 See DPI_INT_REG */ 4393 uint64_t sli : 1; /**< SLI interrupt 4394 See SLI_INT_SUM (enabled by SLI_INT_ENB_CIU) */ 4395 uint64_t usb : 1; /**< USB UCTL0 interrupt 4396 See UCTL0_INT_REG */ 4397 uint64_t dfa : 1; /**< DFA interrupt 4398 See DFA_ERROR */ 4399 uint64_t key : 1; /**< KEY interrupt 4400 See KEY_INT_SUM */ 4401 uint64_t rad : 1; /**< RAD interrupt 4402 See RAD_REG_ERROR */ 4403 uint64_t tim : 1; /**< TIM interrupt 4404 See TIM_REG_ERROR */ 4405 uint64_t zip : 1; /**< ZIP interrupt 4406 See ZIP_ERROR */ 4407 uint64_t pko : 1; /**< PKO interrupt 4408 See PKO_REG_ERROR */ 4409 uint64_t pip : 1; /**< PIP interrupt 4410 See PIP_INT_REG */ 4411 uint64_t ipd : 1; /**< IPD interrupt 4412 See IPD_INT_SUM */ 4413 uint64_t l2c : 1; /**< L2C interrupt 4414 See L2C_INT_REG */ 4415 uint64_t pow : 1; /**< POW err interrupt 4416 See POW_ECC_ERR */ 4417 uint64_t fpa : 1; /**< FPA interrupt 4418 See FPA_INT_SUM */ 4419 uint64_t iob : 1; /**< IOB interrupt 4420 See IOB_INT_SUM */ 4421 uint64_t mio : 1; /**< MIO boot interrupt 4422 See MIO_BOOT_ERR */ 4423 uint64_t nand : 1; /**< NAND Flash Controller interrupt 4424 See NDF_INT */ 4425 uint64_t mii1 : 1; /**< RGMII/MII/MIX Interface 1 Interrupt 4426 See MIX1_ISR */ 4427 uint64_t reserved_6_17 : 12; 4428 uint64_t wdog : 6; /**< 6 watchdog interrupts */ 4429#else 4430 uint64_t wdog : 6; 4431 uint64_t reserved_6_17 : 12; 4432 uint64_t mii1 : 1; 4433 uint64_t nand : 1; 4434 uint64_t mio : 1; 4435 uint64_t iob : 1; 4436 uint64_t fpa : 1; 4437 uint64_t pow : 1; 4438 uint64_t l2c : 1; 4439 uint64_t ipd : 1; 4440 uint64_t pip : 1; 4441 uint64_t pko : 1; 4442 uint64_t zip : 1; 4443 uint64_t tim : 1; 4444 uint64_t rad : 1; 4445 uint64_t key : 1; 4446 uint64_t dfa : 1; 4447 uint64_t usb : 1; 4448 uint64_t sli : 1; 4449 uint64_t dpi : 1; 4450 uint64_t agx0 : 1; 4451 uint64_t reserved_37_45 : 9; 4452 uint64_t agl : 1; 4453 uint64_t ptp : 1; 4454 uint64_t pem0 : 1; 4455 uint64_t pem1 : 1; 4456 uint64_t srio0 : 1; 4457 uint64_t srio1 : 1; 4458 uint64_t lmc0 : 1; 4459 uint64_t reserved_53_55 : 3; 4460 uint64_t dfm : 1; 4461 uint64_t reserved_57_62 : 6; 4462 uint64_t rst : 1; 4463#endif 4464 } cn63xx; 4465 struct cvmx_ciu_int_sum1_cn63xx cn63xxp1; 4466}; 4467typedef union cvmx_ciu_int_sum1 cvmx_ciu_int_sum1_t; 4468 4469/** 4470 * cvmx_ciu_mbox_clr# 4471 */ 4472union cvmx_ciu_mbox_clrx 4473{ 4474 uint64_t u64; 4475 struct cvmx_ciu_mbox_clrx_s 4476 { 4477#if __BYTE_ORDER == __BIG_ENDIAN 4478 uint64_t reserved_32_63 : 32; 4479 uint64_t bits : 32; /**< On writes, clr corresponding bit in MBOX register 4480 on reads, return the MBOX register */ 4481#else 4482 uint64_t bits : 32; 4483 uint64_t reserved_32_63 : 32; 4484#endif 4485 } s; 4486 struct cvmx_ciu_mbox_clrx_s cn30xx; 4487 struct cvmx_ciu_mbox_clrx_s cn31xx; 4488 struct cvmx_ciu_mbox_clrx_s cn38xx; 4489 struct cvmx_ciu_mbox_clrx_s cn38xxp2; 4490 struct cvmx_ciu_mbox_clrx_s cn50xx; 4491 struct cvmx_ciu_mbox_clrx_s cn52xx; 4492 struct cvmx_ciu_mbox_clrx_s cn52xxp1; 4493 struct cvmx_ciu_mbox_clrx_s cn56xx; 4494 struct cvmx_ciu_mbox_clrx_s cn56xxp1; 4495 struct cvmx_ciu_mbox_clrx_s cn58xx; 4496 struct cvmx_ciu_mbox_clrx_s cn58xxp1; 4497 struct cvmx_ciu_mbox_clrx_s cn63xx; 4498 struct cvmx_ciu_mbox_clrx_s cn63xxp1; 4499}; 4500typedef union cvmx_ciu_mbox_clrx cvmx_ciu_mbox_clrx_t; 4501 4502/** 4503 * cvmx_ciu_mbox_set# 4504 */ 4505union cvmx_ciu_mbox_setx 4506{ 4507 uint64_t u64; 4508 struct cvmx_ciu_mbox_setx_s 4509 { 4510#if __BYTE_ORDER == __BIG_ENDIAN 4511 uint64_t reserved_32_63 : 32; 4512 uint64_t bits : 32; /**< On writes, set corresponding bit in MBOX register 4513 on reads, return the MBOX register */ 4514#else 4515 uint64_t bits : 32; 4516 uint64_t reserved_32_63 : 32; 4517#endif 4518 } s; 4519 struct cvmx_ciu_mbox_setx_s cn30xx; 4520 struct cvmx_ciu_mbox_setx_s cn31xx; 4521 struct cvmx_ciu_mbox_setx_s cn38xx; 4522 struct cvmx_ciu_mbox_setx_s cn38xxp2; 4523 struct cvmx_ciu_mbox_setx_s cn50xx; 4524 struct cvmx_ciu_mbox_setx_s cn52xx; 4525 struct cvmx_ciu_mbox_setx_s cn52xxp1; 4526 struct cvmx_ciu_mbox_setx_s cn56xx; 4527 struct cvmx_ciu_mbox_setx_s cn56xxp1; 4528 struct cvmx_ciu_mbox_setx_s cn58xx; 4529 struct cvmx_ciu_mbox_setx_s cn58xxp1; 4530 struct cvmx_ciu_mbox_setx_s cn63xx; 4531 struct cvmx_ciu_mbox_setx_s cn63xxp1; 4532}; 4533typedef union cvmx_ciu_mbox_setx cvmx_ciu_mbox_setx_t; 4534 4535/** 4536 * cvmx_ciu_nmi 4537 */ 4538union cvmx_ciu_nmi 4539{ 4540 uint64_t u64; 4541 struct cvmx_ciu_nmi_s 4542 { 4543#if __BYTE_ORDER == __BIG_ENDIAN 4544 uint64_t reserved_16_63 : 48; 4545 uint64_t nmi : 16; /**< Send NMI pulse to PP vector */ 4546#else 4547 uint64_t nmi : 16; 4548 uint64_t reserved_16_63 : 48; 4549#endif 4550 } s; 4551 struct cvmx_ciu_nmi_cn30xx 4552 { 4553#if __BYTE_ORDER == __BIG_ENDIAN 4554 uint64_t reserved_1_63 : 63; 4555 uint64_t nmi : 1; /**< Send NMI pulse to PP vector */ 4556#else 4557 uint64_t nmi : 1; 4558 uint64_t reserved_1_63 : 63; 4559#endif 4560 } cn30xx; 4561 struct cvmx_ciu_nmi_cn31xx 4562 { 4563#if __BYTE_ORDER == __BIG_ENDIAN 4564 uint64_t reserved_2_63 : 62; 4565 uint64_t nmi : 2; /**< Send NMI pulse to PP vector */ 4566#else 4567 uint64_t nmi : 2; 4568 uint64_t reserved_2_63 : 62; 4569#endif 4570 } cn31xx; 4571 struct cvmx_ciu_nmi_s cn38xx; 4572 struct cvmx_ciu_nmi_s cn38xxp2; 4573 struct cvmx_ciu_nmi_cn31xx cn50xx; 4574 struct cvmx_ciu_nmi_cn52xx 4575 { 4576#if __BYTE_ORDER == __BIG_ENDIAN 4577 uint64_t reserved_4_63 : 60; 4578 uint64_t nmi : 4; /**< Send NMI pulse to PP vector */ 4579#else 4580 uint64_t nmi : 4; 4581 uint64_t reserved_4_63 : 60; 4582#endif 4583 } cn52xx; 4584 struct cvmx_ciu_nmi_cn52xx cn52xxp1; 4585 struct cvmx_ciu_nmi_cn56xx 4586 { 4587#if __BYTE_ORDER == __BIG_ENDIAN 4588 uint64_t reserved_12_63 : 52; 4589 uint64_t nmi : 12; /**< Send NMI pulse to PP vector */ 4590#else 4591 uint64_t nmi : 12; 4592 uint64_t reserved_12_63 : 52; 4593#endif 4594 } cn56xx; 4595 struct cvmx_ciu_nmi_cn56xx cn56xxp1; 4596 struct cvmx_ciu_nmi_s cn58xx; 4597 struct cvmx_ciu_nmi_s cn58xxp1; 4598 struct cvmx_ciu_nmi_cn63xx 4599 { 4600#if __BYTE_ORDER == __BIG_ENDIAN 4601 uint64_t reserved_6_63 : 58; 4602 uint64_t nmi : 6; /**< Send NMI pulse to PP vector */ 4603#else 4604 uint64_t nmi : 6; 4605 uint64_t reserved_6_63 : 58; 4606#endif 4607 } cn63xx; 4608 struct cvmx_ciu_nmi_cn63xx cn63xxp1; 4609}; 4610typedef union cvmx_ciu_nmi cvmx_ciu_nmi_t; 4611 4612/** 4613 * cvmx_ciu_pci_inta 4614 */ 4615union cvmx_ciu_pci_inta 4616{ 4617 uint64_t u64; 4618 struct cvmx_ciu_pci_inta_s 4619 { 4620#if __BYTE_ORDER == __BIG_ENDIAN 4621 uint64_t reserved_2_63 : 62; 4622 uint64_t intr : 2; /**< PCIe/sRIO interrupt 4623 These bits are observed in CIU_INTX_SUM0<33:32> 4624 where X=32-33 */ 4625#else 4626 uint64_t intr : 2; 4627 uint64_t reserved_2_63 : 62; 4628#endif 4629 } s; 4630 struct cvmx_ciu_pci_inta_s cn30xx; 4631 struct cvmx_ciu_pci_inta_s cn31xx; 4632 struct cvmx_ciu_pci_inta_s cn38xx; 4633 struct cvmx_ciu_pci_inta_s cn38xxp2; 4634 struct cvmx_ciu_pci_inta_s cn50xx; 4635 struct cvmx_ciu_pci_inta_s cn52xx; 4636 struct cvmx_ciu_pci_inta_s cn52xxp1; 4637 struct cvmx_ciu_pci_inta_s cn56xx; 4638 struct cvmx_ciu_pci_inta_s cn56xxp1; 4639 struct cvmx_ciu_pci_inta_s cn58xx; 4640 struct cvmx_ciu_pci_inta_s cn58xxp1; 4641 struct cvmx_ciu_pci_inta_s cn63xx; 4642 struct cvmx_ciu_pci_inta_s cn63xxp1; 4643}; 4644typedef union cvmx_ciu_pci_inta cvmx_ciu_pci_inta_t; 4645 4646/** 4647 * cvmx_ciu_pp_dbg 4648 */ 4649union cvmx_ciu_pp_dbg 4650{ 4651 uint64_t u64; 4652 struct cvmx_ciu_pp_dbg_s 4653 { 4654#if __BYTE_ORDER == __BIG_ENDIAN 4655 uint64_t reserved_16_63 : 48; 4656 uint64_t ppdbg : 16; /**< Debug[DM] value for each PP 4657 whether the PP's are in debug mode or not */ 4658#else 4659 uint64_t ppdbg : 16; 4660 uint64_t reserved_16_63 : 48; 4661#endif 4662 } s; 4663 struct cvmx_ciu_pp_dbg_cn30xx 4664 { 4665#if __BYTE_ORDER == __BIG_ENDIAN 4666 uint64_t reserved_1_63 : 63; 4667 uint64_t ppdbg : 1; /**< Debug[DM] value for each PP 4668 whether the PP's are in debug mode or not */ 4669#else 4670 uint64_t ppdbg : 1; 4671 uint64_t reserved_1_63 : 63; 4672#endif 4673 } cn30xx; 4674 struct cvmx_ciu_pp_dbg_cn31xx 4675 { 4676#if __BYTE_ORDER == __BIG_ENDIAN 4677 uint64_t reserved_2_63 : 62; 4678 uint64_t ppdbg : 2; /**< Debug[DM] value for each PP 4679 whether the PP's are in debug mode or not */ 4680#else 4681 uint64_t ppdbg : 2; 4682 uint64_t reserved_2_63 : 62; 4683#endif 4684 } cn31xx; 4685 struct cvmx_ciu_pp_dbg_s cn38xx; 4686 struct cvmx_ciu_pp_dbg_s cn38xxp2; 4687 struct cvmx_ciu_pp_dbg_cn31xx cn50xx; 4688 struct cvmx_ciu_pp_dbg_cn52xx 4689 { 4690#if __BYTE_ORDER == __BIG_ENDIAN 4691 uint64_t reserved_4_63 : 60; 4692 uint64_t ppdbg : 4; /**< Debug[DM] value for each PP 4693 whether the PP's are in debug mode or not */ 4694#else 4695 uint64_t ppdbg : 4; 4696 uint64_t reserved_4_63 : 60; 4697#endif 4698 } cn52xx; 4699 struct cvmx_ciu_pp_dbg_cn52xx cn52xxp1; 4700 struct cvmx_ciu_pp_dbg_cn56xx 4701 { 4702#if __BYTE_ORDER == __BIG_ENDIAN 4703 uint64_t reserved_12_63 : 52; 4704 uint64_t ppdbg : 12; /**< Debug[DM] value for each PP 4705 whether the PP's are in debug mode or not */ 4706#else 4707 uint64_t ppdbg : 12; 4708 uint64_t reserved_12_63 : 52; 4709#endif 4710 } cn56xx; 4711 struct cvmx_ciu_pp_dbg_cn56xx cn56xxp1; 4712 struct cvmx_ciu_pp_dbg_s cn58xx; 4713 struct cvmx_ciu_pp_dbg_s cn58xxp1; 4714 struct cvmx_ciu_pp_dbg_cn63xx 4715 { 4716#if __BYTE_ORDER == __BIG_ENDIAN 4717 uint64_t reserved_6_63 : 58; 4718 uint64_t ppdbg : 6; /**< Debug[DM] value for each PP 4719 whether the PP's are in debug mode or not */ 4720#else 4721 uint64_t ppdbg : 6; 4722 uint64_t reserved_6_63 : 58; 4723#endif 4724 } cn63xx; 4725 struct cvmx_ciu_pp_dbg_cn63xx cn63xxp1; 4726}; 4727typedef union cvmx_ciu_pp_dbg cvmx_ciu_pp_dbg_t; 4728 4729/** 4730 * cvmx_ciu_pp_poke# 4731 * 4732 * Notes: 4733 * Any write to a CIU_PP_POKE register clears any pending interrupt generated 4734 * by the associated watchdog, resets the CIU_WDOG[STATE] field, and set 4735 * CIU_WDOG[CNT] to be (CIU_WDOG[LEN] << 8). 4736 * 4737 * Reads to this register will return the associated CIU_WDOG register. 4738 */ 4739union cvmx_ciu_pp_pokex 4740{ 4741 uint64_t u64; 4742 struct cvmx_ciu_pp_pokex_s 4743 { 4744#if __BYTE_ORDER == __BIG_ENDIAN 4745 uint64_t poke : 64; /**< Reserved */ 4746#else 4747 uint64_t poke : 64; 4748#endif 4749 } s; 4750 struct cvmx_ciu_pp_pokex_s cn30xx; 4751 struct cvmx_ciu_pp_pokex_s cn31xx; 4752 struct cvmx_ciu_pp_pokex_s cn38xx; 4753 struct cvmx_ciu_pp_pokex_s cn38xxp2; 4754 struct cvmx_ciu_pp_pokex_s cn50xx; 4755 struct cvmx_ciu_pp_pokex_s cn52xx; 4756 struct cvmx_ciu_pp_pokex_s cn52xxp1; 4757 struct cvmx_ciu_pp_pokex_s cn56xx; 4758 struct cvmx_ciu_pp_pokex_s cn56xxp1; 4759 struct cvmx_ciu_pp_pokex_s cn58xx; 4760 struct cvmx_ciu_pp_pokex_s cn58xxp1; 4761 struct cvmx_ciu_pp_pokex_s cn63xx; 4762 struct cvmx_ciu_pp_pokex_s cn63xxp1; 4763}; 4764typedef union cvmx_ciu_pp_pokex cvmx_ciu_pp_pokex_t; 4765 4766/** 4767 * cvmx_ciu_pp_rst 4768 * 4769 * Contains the reset control for each PP. Value of '1' will hold a PP in reset, '0' will release. 4770 * Resets to 0xffff when PCI boot is enabled, 0xfffe otherwise. 4771 */ 4772union cvmx_ciu_pp_rst 4773{ 4774 uint64_t u64; 4775 struct cvmx_ciu_pp_rst_s 4776 { 4777#if __BYTE_ORDER == __BIG_ENDIAN 4778 uint64_t reserved_16_63 : 48; 4779 uint64_t rst : 15; /**< PP Rst for PP's 5-1 */ 4780 uint64_t rst0 : 1; /**< PP Rst for PP0 4781 depends on standalone mode */ 4782#else 4783 uint64_t rst0 : 1; 4784 uint64_t rst : 15; 4785 uint64_t reserved_16_63 : 48; 4786#endif 4787 } s; 4788 struct cvmx_ciu_pp_rst_cn30xx 4789 { 4790#if __BYTE_ORDER == __BIG_ENDIAN 4791 uint64_t reserved_1_63 : 63; 4792 uint64_t rst0 : 1; /**< PP Rst for PP0 4793 depends on standalone mode */ 4794#else 4795 uint64_t rst0 : 1; 4796 uint64_t reserved_1_63 : 63; 4797#endif 4798 } cn30xx; 4799 struct cvmx_ciu_pp_rst_cn31xx 4800 { 4801#if __BYTE_ORDER == __BIG_ENDIAN 4802 uint64_t reserved_2_63 : 62; 4803 uint64_t rst : 1; /**< PP Rst for PP1 */ 4804 uint64_t rst0 : 1; /**< PP Rst for PP0 4805 depends on standalone mode */ 4806#else 4807 uint64_t rst0 : 1; 4808 uint64_t rst : 1; 4809 uint64_t reserved_2_63 : 62; 4810#endif 4811 } cn31xx; 4812 struct cvmx_ciu_pp_rst_s cn38xx; 4813 struct cvmx_ciu_pp_rst_s cn38xxp2; 4814 struct cvmx_ciu_pp_rst_cn31xx cn50xx; 4815 struct cvmx_ciu_pp_rst_cn52xx 4816 { 4817#if __BYTE_ORDER == __BIG_ENDIAN 4818 uint64_t reserved_4_63 : 60; 4819 uint64_t rst : 3; /**< PP Rst for PP's 11-1 */ 4820 uint64_t rst0 : 1; /**< PP Rst for PP0 4821 depends on standalone mode */ 4822#else 4823 uint64_t rst0 : 1; 4824 uint64_t rst : 3; 4825 uint64_t reserved_4_63 : 60; 4826#endif 4827 } cn52xx; 4828 struct cvmx_ciu_pp_rst_cn52xx cn52xxp1; 4829 struct cvmx_ciu_pp_rst_cn56xx 4830 { 4831#if __BYTE_ORDER == __BIG_ENDIAN 4832 uint64_t reserved_12_63 : 52; 4833 uint64_t rst : 11; /**< PP Rst for PP's 11-1 */ 4834 uint64_t rst0 : 1; /**< PP Rst for PP0 4835 depends on standalone mode */ 4836#else 4837 uint64_t rst0 : 1; 4838 uint64_t rst : 11; 4839 uint64_t reserved_12_63 : 52; 4840#endif 4841 } cn56xx; 4842 struct cvmx_ciu_pp_rst_cn56xx cn56xxp1; 4843 struct cvmx_ciu_pp_rst_s cn58xx; 4844 struct cvmx_ciu_pp_rst_s cn58xxp1; 4845 struct cvmx_ciu_pp_rst_cn63xx 4846 { 4847#if __BYTE_ORDER == __BIG_ENDIAN 4848 uint64_t reserved_6_63 : 58; 4849 uint64_t rst : 5; /**< PP Rst for PP's 5-1 */ 4850 uint64_t rst0 : 1; /**< PP Rst for PP0 4851 depends on standalone mode */ 4852#else 4853 uint64_t rst0 : 1; 4854 uint64_t rst : 5; 4855 uint64_t reserved_6_63 : 58; 4856#endif 4857 } cn63xx; 4858 struct cvmx_ciu_pp_rst_cn63xx cn63xxp1; 4859}; 4860typedef union cvmx_ciu_pp_rst cvmx_ciu_pp_rst_t; 4861 4862/** 4863 * cvmx_ciu_qlm0 4864 * 4865 * Notes: 4866 * This register is only reset by cold reset. 4867 * 4868 */ 4869union cvmx_ciu_qlm0 4870{ 4871 uint64_t u64; 4872 struct cvmx_ciu_qlm0_s 4873 { 4874#if __BYTE_ORDER == __BIG_ENDIAN 4875 uint64_t g2bypass : 1; /**< QLM0 PCIE Gen2 tx bypass enable */ 4876 uint64_t reserved_53_62 : 10; 4877 uint64_t g2deemph : 5; /**< QLM0 PCIE Gen2 tx bypass de-emphasis value */ 4878 uint64_t reserved_45_47 : 3; 4879 uint64_t g2margin : 5; /**< QLM0 PCIE Gen2 tx bypass margin (amplitude) value */ 4880 uint64_t reserved_32_39 : 8; 4881 uint64_t txbypass : 1; /**< QLM0 transmitter bypass enable */ 4882 uint64_t reserved_21_30 : 10; 4883 uint64_t txdeemph : 5; /**< QLM0 transmitter bypass de-emphasis value */ 4884 uint64_t reserved_13_15 : 3; 4885 uint64_t txmargin : 5; /**< QLM0 transmitter bypass margin (amplitude) value */ 4886 uint64_t reserved_4_7 : 4; 4887 uint64_t lane_en : 4; /**< QLM0 lane enable mask */ 4888#else 4889 uint64_t lane_en : 4; 4890 uint64_t reserved_4_7 : 4; 4891 uint64_t txmargin : 5; 4892 uint64_t reserved_13_15 : 3; 4893 uint64_t txdeemph : 5; 4894 uint64_t reserved_21_30 : 10; 4895 uint64_t txbypass : 1; 4896 uint64_t reserved_32_39 : 8; 4897 uint64_t g2margin : 5; 4898 uint64_t reserved_45_47 : 3; 4899 uint64_t g2deemph : 5; 4900 uint64_t reserved_53_62 : 10; 4901 uint64_t g2bypass : 1; 4902#endif 4903 } s; 4904 struct cvmx_ciu_qlm0_s cn63xx; 4905 struct cvmx_ciu_qlm0_cn63xxp1 4906 { 4907#if __BYTE_ORDER == __BIG_ENDIAN 4908 uint64_t reserved_32_63 : 32; 4909 uint64_t txbypass : 1; /**< QLM0 transmitter bypass enable */ 4910 uint64_t reserved_20_30 : 11; 4911 uint64_t txdeemph : 4; /**< QLM0 transmitter bypass de-emphasis value */ 4912 uint64_t reserved_13_15 : 3; 4913 uint64_t txmargin : 5; /**< QLM0 transmitter bypass margin (amplitude) value */ 4914 uint64_t reserved_4_7 : 4; 4915 uint64_t lane_en : 4; /**< QLM0 lane enable mask */ 4916#else 4917 uint64_t lane_en : 4; 4918 uint64_t reserved_4_7 : 4; 4919 uint64_t txmargin : 5; 4920 uint64_t reserved_13_15 : 3; 4921 uint64_t txdeemph : 4; 4922 uint64_t reserved_20_30 : 11; 4923 uint64_t txbypass : 1; 4924 uint64_t reserved_32_63 : 32; 4925#endif 4926 } cn63xxp1; 4927}; 4928typedef union cvmx_ciu_qlm0 cvmx_ciu_qlm0_t; 4929 4930/** 4931 * cvmx_ciu_qlm1 4932 * 4933 * Notes: 4934 * This register is only reset by cold reset. 4935 * 4936 */ 4937union cvmx_ciu_qlm1 4938{ 4939 uint64_t u64; 4940 struct cvmx_ciu_qlm1_s 4941 { 4942#if __BYTE_ORDER == __BIG_ENDIAN 4943 uint64_t g2bypass : 1; /**< QLM1 PCIE Gen2 tx bypass enable */ 4944 uint64_t reserved_53_62 : 10; 4945 uint64_t g2deemph : 5; /**< QLM1 PCIE Gen2 tx bypass de-emphasis value */ 4946 uint64_t reserved_45_47 : 3; 4947 uint64_t g2margin : 5; /**< QLM1 PCIE Gen2 tx bypass margin (amplitude) value */ 4948 uint64_t reserved_32_39 : 8; 4949 uint64_t txbypass : 1; /**< QLM1 transmitter bypass enable */ 4950 uint64_t reserved_21_30 : 10; 4951 uint64_t txdeemph : 5; /**< QLM1 transmitter bypass de-emphasis value */ 4952 uint64_t reserved_13_15 : 3; 4953 uint64_t txmargin : 5; /**< QLM1 transmitter bypass margin (amplitude) value */ 4954 uint64_t reserved_4_7 : 4; 4955 uint64_t lane_en : 4; /**< QLM1 lane enable mask */ 4956#else 4957 uint64_t lane_en : 4; 4958 uint64_t reserved_4_7 : 4; 4959 uint64_t txmargin : 5; 4960 uint64_t reserved_13_15 : 3; 4961 uint64_t txdeemph : 5; 4962 uint64_t reserved_21_30 : 10; 4963 uint64_t txbypass : 1; 4964 uint64_t reserved_32_39 : 8; 4965 uint64_t g2margin : 5; 4966 uint64_t reserved_45_47 : 3; 4967 uint64_t g2deemph : 5; 4968 uint64_t reserved_53_62 : 10; 4969 uint64_t g2bypass : 1; 4970#endif 4971 } s; 4972 struct cvmx_ciu_qlm1_s cn63xx; 4973 struct cvmx_ciu_qlm1_cn63xxp1 4974 { 4975#if __BYTE_ORDER == __BIG_ENDIAN 4976 uint64_t reserved_32_63 : 32; 4977 uint64_t txbypass : 1; /**< QLM1 transmitter bypass enable */ 4978 uint64_t reserved_20_30 : 11; 4979 uint64_t txdeemph : 4; /**< QLM1 transmitter bypass de-emphasis value */ 4980 uint64_t reserved_13_15 : 3; 4981 uint64_t txmargin : 5; /**< QLM1 transmitter bypass margin (amplitude) value */ 4982 uint64_t reserved_4_7 : 4; 4983 uint64_t lane_en : 4; /**< QLM1 lane enable mask */ 4984#else 4985 uint64_t lane_en : 4; 4986 uint64_t reserved_4_7 : 4; 4987 uint64_t txmargin : 5; 4988 uint64_t reserved_13_15 : 3; 4989 uint64_t txdeemph : 4; 4990 uint64_t reserved_20_30 : 11; 4991 uint64_t txbypass : 1; 4992 uint64_t reserved_32_63 : 32; 4993#endif 4994 } cn63xxp1; 4995}; 4996typedef union cvmx_ciu_qlm1 cvmx_ciu_qlm1_t; 4997 4998/** 4999 * cvmx_ciu_qlm2 5000 * 5001 * Notes: 5002 * This register is only reset by cold reset. 5003 * 5004 */ 5005union cvmx_ciu_qlm2 5006{ 5007 uint64_t u64; 5008 struct cvmx_ciu_qlm2_s 5009 { 5010#if __BYTE_ORDER == __BIG_ENDIAN 5011 uint64_t reserved_32_63 : 32; 5012 uint64_t txbypass : 1; /**< QLM2 transmitter bypass enable */ 5013 uint64_t reserved_21_30 : 10; 5014 uint64_t txdeemph : 5; /**< QLM2 transmitter bypass de-emphasis value */ 5015 uint64_t reserved_13_15 : 3; 5016 uint64_t txmargin : 5; /**< QLM2 transmitter bypass margin (amplitude) value */ 5017 uint64_t reserved_4_7 : 4; 5018 uint64_t lane_en : 4; /**< QLM2 lane enable mask */ 5019#else 5020 uint64_t lane_en : 4; 5021 uint64_t reserved_4_7 : 4; 5022 uint64_t txmargin : 5; 5023 uint64_t reserved_13_15 : 3; 5024 uint64_t txdeemph : 5; 5025 uint64_t reserved_21_30 : 10; 5026 uint64_t txbypass : 1; 5027 uint64_t reserved_32_63 : 32; 5028#endif 5029 } s; 5030 struct cvmx_ciu_qlm2_s cn63xx; 5031 struct cvmx_ciu_qlm2_cn63xxp1 5032 { 5033#if __BYTE_ORDER == __BIG_ENDIAN 5034 uint64_t reserved_32_63 : 32; 5035 uint64_t txbypass : 1; /**< QLM2 transmitter bypass enable */ 5036 uint64_t reserved_20_30 : 11; 5037 uint64_t txdeemph : 4; /**< QLM2 transmitter bypass de-emphasis value */ 5038 uint64_t reserved_13_15 : 3; 5039 uint64_t txmargin : 5; /**< QLM2 transmitter bypass margin (amplitude) value */ 5040 uint64_t reserved_4_7 : 4; 5041 uint64_t lane_en : 4; /**< QLM2 lane enable mask */ 5042#else 5043 uint64_t lane_en : 4; 5044 uint64_t reserved_4_7 : 4; 5045 uint64_t txmargin : 5; 5046 uint64_t reserved_13_15 : 3; 5047 uint64_t txdeemph : 4; 5048 uint64_t reserved_20_30 : 11; 5049 uint64_t txbypass : 1; 5050 uint64_t reserved_32_63 : 32; 5051#endif 5052 } cn63xxp1; 5053}; 5054typedef union cvmx_ciu_qlm2 cvmx_ciu_qlm2_t; 5055 5056/** 5057 * cvmx_ciu_qlm_dcok 5058 */ 5059union cvmx_ciu_qlm_dcok 5060{ 5061 uint64_t u64; 5062 struct cvmx_ciu_qlm_dcok_s 5063 { 5064#if __BYTE_ORDER == __BIG_ENDIAN 5065 uint64_t reserved_4_63 : 60; 5066 uint64_t qlm_dcok : 4; /**< Re-assert dcok for each QLM. The value in this 5067 field is "anded" with the pll_dcok pin and then 5068 sent to each QLM (0..3). */ 5069#else 5070 uint64_t qlm_dcok : 4; 5071 uint64_t reserved_4_63 : 60; 5072#endif 5073 } s; 5074 struct cvmx_ciu_qlm_dcok_cn52xx 5075 { 5076#if __BYTE_ORDER == __BIG_ENDIAN 5077 uint64_t reserved_2_63 : 62; 5078 uint64_t qlm_dcok : 2; /**< Re-assert dcok for each QLM. The value in this 5079 field is "anded" with the pll_dcok pin and then 5080 sent to each QLM (0..3). */ 5081#else 5082 uint64_t qlm_dcok : 2; 5083 uint64_t reserved_2_63 : 62; 5084#endif 5085 } cn52xx; 5086 struct cvmx_ciu_qlm_dcok_cn52xx cn52xxp1; 5087 struct cvmx_ciu_qlm_dcok_s cn56xx; 5088 struct cvmx_ciu_qlm_dcok_s cn56xxp1; 5089}; 5090typedef union cvmx_ciu_qlm_dcok cvmx_ciu_qlm_dcok_t; 5091 5092/** 5093 * cvmx_ciu_qlm_jtgc 5094 */ 5095union cvmx_ciu_qlm_jtgc 5096{ 5097 uint64_t u64; 5098 struct cvmx_ciu_qlm_jtgc_s 5099 { 5100#if __BYTE_ORDER == __BIG_ENDIAN 5101 uint64_t reserved_11_63 : 53; 5102 uint64_t clk_div : 3; /**< Clock divider for QLM JTAG operations. eclk is 5103 divided by 2^(CLK_DIV + 2) */ 5104 uint64_t reserved_6_7 : 2; 5105 uint64_t mux_sel : 2; /**< Selects which QLM JTAG shift out is shifted into 5106 the QLM JTAG shift register: CIU_QLM_JTGD[SHFT_REG] */ 5107 uint64_t bypass : 4; /**< Selects which QLM JTAG shift chains are bypassed 5108 by the QLM JTAG data register (CIU_QLM_JTGD) (one 5109 bit per QLM) */ 5110#else 5111 uint64_t bypass : 4; 5112 uint64_t mux_sel : 2; 5113 uint64_t reserved_6_7 : 2; 5114 uint64_t clk_div : 3; 5115 uint64_t reserved_11_63 : 53; 5116#endif 5117 } s; 5118 struct cvmx_ciu_qlm_jtgc_cn52xx 5119 { 5120#if __BYTE_ORDER == __BIG_ENDIAN 5121 uint64_t reserved_11_63 : 53; 5122 uint64_t clk_div : 3; /**< Clock divider for QLM JTAG operations. eclk is 5123 divided by 2^(CLK_DIV + 2) */ 5124 uint64_t reserved_5_7 : 3; 5125 uint64_t mux_sel : 1; /**< Selects which QLM JTAG shift out is shifted into 5126 the QLM JTAG shift register: CIU_QLM_JTGD[SHFT_REG] */ 5127 uint64_t reserved_2_3 : 2; 5128 uint64_t bypass : 2; /**< Selects which QLM JTAG shift chains are bypassed 5129 by the QLM JTAG data register (CIU_QLM_JTGD) (one 5130 bit per QLM) */ 5131#else 5132 uint64_t bypass : 2; 5133 uint64_t reserved_2_3 : 2; 5134 uint64_t mux_sel : 1; 5135 uint64_t reserved_5_7 : 3; 5136 uint64_t clk_div : 3; 5137 uint64_t reserved_11_63 : 53; 5138#endif 5139 } cn52xx; 5140 struct cvmx_ciu_qlm_jtgc_cn52xx cn52xxp1; 5141 struct cvmx_ciu_qlm_jtgc_s cn56xx; 5142 struct cvmx_ciu_qlm_jtgc_s cn56xxp1; 5143 struct cvmx_ciu_qlm_jtgc_cn63xx 5144 { 5145#if __BYTE_ORDER == __BIG_ENDIAN 5146 uint64_t reserved_11_63 : 53; 5147 uint64_t clk_div : 3; /**< Clock divider for QLM JTAG operations. eclk is 5148 divided by 2^(CLK_DIV + 2) */ 5149 uint64_t reserved_6_7 : 2; 5150 uint64_t mux_sel : 2; /**< Selects which QLM JTAG shift out is shifted into 5151 the QLM JTAG shift register: CIU_QLM_JTGD[SHFT_REG] */ 5152 uint64_t reserved_3_3 : 1; 5153 uint64_t bypass : 3; /**< Selects which QLM JTAG shift chains are bypassed 5154 by the QLM JTAG data register (CIU_QLM_JTGD) (one 5155 bit per QLM) */ 5156#else 5157 uint64_t bypass : 3; 5158 uint64_t reserved_3_3 : 1; 5159 uint64_t mux_sel : 2; 5160 uint64_t reserved_6_7 : 2; 5161 uint64_t clk_div : 3; 5162 uint64_t reserved_11_63 : 53; 5163#endif 5164 } cn63xx; 5165 struct cvmx_ciu_qlm_jtgc_cn63xx cn63xxp1; 5166}; 5167typedef union cvmx_ciu_qlm_jtgc cvmx_ciu_qlm_jtgc_t; 5168 5169/** 5170 * cvmx_ciu_qlm_jtgd 5171 */ 5172union cvmx_ciu_qlm_jtgd 5173{ 5174 uint64_t u64; 5175 struct cvmx_ciu_qlm_jtgd_s 5176 { 5177#if __BYTE_ORDER == __BIG_ENDIAN 5178 uint64_t capture : 1; /**< Perform JTAG capture operation (self-clearing when 5179 op completes) */ 5180 uint64_t shift : 1; /**< Perform JTAG shift operation (self-clearing when 5181 op completes) */ 5182 uint64_t update : 1; /**< Perform JTAG update operation (self-clearing when 5183 op completes) */ 5184 uint64_t reserved_44_60 : 17; 5185 uint64_t select : 4; /**< Selects which QLM JTAG shift chains the JTAG 5186 operations are performed on */ 5187 uint64_t reserved_37_39 : 3; 5188 uint64_t shft_cnt : 5; /**< QLM JTAG shift count (encoded in -1 notation) */ 5189 uint64_t shft_reg : 32; /**< QLM JTAG shift register */ 5190#else 5191 uint64_t shft_reg : 32; 5192 uint64_t shft_cnt : 5; 5193 uint64_t reserved_37_39 : 3; 5194 uint64_t select : 4; 5195 uint64_t reserved_44_60 : 17; 5196 uint64_t update : 1; 5197 uint64_t shift : 1; 5198 uint64_t capture : 1; 5199#endif 5200 } s; 5201 struct cvmx_ciu_qlm_jtgd_cn52xx 5202 { 5203#if __BYTE_ORDER == __BIG_ENDIAN 5204 uint64_t capture : 1; /**< Perform JTAG capture operation (self-clearing when 5205 op completes) */ 5206 uint64_t shift : 1; /**< Perform JTAG shift operation (self-clearing when 5207 op completes) */ 5208 uint64_t update : 1; /**< Perform JTAG update operation (self-clearing when 5209 op completes) */ 5210 uint64_t reserved_42_60 : 19; 5211 uint64_t select : 2; /**< Selects which QLM JTAG shift chains the JTAG 5212 operations are performed on */ 5213 uint64_t reserved_37_39 : 3; 5214 uint64_t shft_cnt : 5; /**< QLM JTAG shift count (encoded in -1 notation) */ 5215 uint64_t shft_reg : 32; /**< QLM JTAG shift register */ 5216#else 5217 uint64_t shft_reg : 32; 5218 uint64_t shft_cnt : 5; 5219 uint64_t reserved_37_39 : 3; 5220 uint64_t select : 2; 5221 uint64_t reserved_42_60 : 19; 5222 uint64_t update : 1; 5223 uint64_t shift : 1; 5224 uint64_t capture : 1; 5225#endif 5226 } cn52xx; 5227 struct cvmx_ciu_qlm_jtgd_cn52xx cn52xxp1; 5228 struct cvmx_ciu_qlm_jtgd_s cn56xx; 5229 struct cvmx_ciu_qlm_jtgd_cn56xxp1 5230 { 5231#if __BYTE_ORDER == __BIG_ENDIAN 5232 uint64_t capture : 1; /**< Perform JTAG capture operation (self-clearing when 5233 op completes) */ 5234 uint64_t shift : 1; /**< Perform JTAG shift operation (self-clearing when 5235 op completes) */ 5236 uint64_t update : 1; /**< Perform JTAG update operation (self-clearing when 5237 op completes) */ 5238 uint64_t reserved_37_60 : 24; 5239 uint64_t shft_cnt : 5; /**< QLM JTAG shift count (encoded in -1 notation) */ 5240 uint64_t shft_reg : 32; /**< QLM JTAG shift register */ 5241#else 5242 uint64_t shft_reg : 32; 5243 uint64_t shft_cnt : 5; 5244 uint64_t reserved_37_60 : 24; 5245 uint64_t update : 1; 5246 uint64_t shift : 1; 5247 uint64_t capture : 1; 5248#endif 5249 } cn56xxp1; 5250 struct cvmx_ciu_qlm_jtgd_cn63xx 5251 { 5252#if __BYTE_ORDER == __BIG_ENDIAN 5253 uint64_t capture : 1; /**< Perform JTAG capture operation (self-clearing when 5254 op completes) */ 5255 uint64_t shift : 1; /**< Perform JTAG shift operation (self-clearing when 5256 op completes) */ 5257 uint64_t update : 1; /**< Perform JTAG update operation (self-clearing when 5258 op completes) */ 5259 uint64_t reserved_43_60 : 18; 5260 uint64_t select : 3; /**< Selects which QLM JTAG shift chains the JTAG 5261 operations are performed on */ 5262 uint64_t reserved_37_39 : 3; 5263 uint64_t shft_cnt : 5; /**< QLM JTAG shift count (encoded in -1 notation) */ 5264 uint64_t shft_reg : 32; /**< QLM JTAG shift register */ 5265#else 5266 uint64_t shft_reg : 32; 5267 uint64_t shft_cnt : 5; 5268 uint64_t reserved_37_39 : 3; 5269 uint64_t select : 3; 5270 uint64_t reserved_43_60 : 18; 5271 uint64_t update : 1; 5272 uint64_t shift : 1; 5273 uint64_t capture : 1; 5274#endif 5275 } cn63xx; 5276 struct cvmx_ciu_qlm_jtgd_cn63xx cn63xxp1; 5277}; 5278typedef union cvmx_ciu_qlm_jtgd cvmx_ciu_qlm_jtgd_t; 5279 5280/** 5281 * cvmx_ciu_soft_bist 5282 */ 5283union cvmx_ciu_soft_bist 5284{ 5285 uint64_t u64; 5286 struct cvmx_ciu_soft_bist_s 5287 { 5288#if __BYTE_ORDER == __BIG_ENDIAN 5289 uint64_t reserved_1_63 : 63; 5290 uint64_t soft_bist : 1; /**< Reserved */ 5291#else 5292 uint64_t soft_bist : 1; 5293 uint64_t reserved_1_63 : 63; 5294#endif 5295 } s; 5296 struct cvmx_ciu_soft_bist_s cn30xx; 5297 struct cvmx_ciu_soft_bist_s cn31xx; 5298 struct cvmx_ciu_soft_bist_s cn38xx; 5299 struct cvmx_ciu_soft_bist_s cn38xxp2; 5300 struct cvmx_ciu_soft_bist_s cn50xx; 5301 struct cvmx_ciu_soft_bist_s cn52xx; 5302 struct cvmx_ciu_soft_bist_s cn52xxp1; 5303 struct cvmx_ciu_soft_bist_s cn56xx; 5304 struct cvmx_ciu_soft_bist_s cn56xxp1; 5305 struct cvmx_ciu_soft_bist_s cn58xx; 5306 struct cvmx_ciu_soft_bist_s cn58xxp1; 5307 struct cvmx_ciu_soft_bist_s cn63xx; 5308 struct cvmx_ciu_soft_bist_s cn63xxp1; 5309}; 5310typedef union cvmx_ciu_soft_bist cvmx_ciu_soft_bist_t; 5311 5312/** 5313 * cvmx_ciu_soft_prst 5314 */ 5315union cvmx_ciu_soft_prst 5316{ 5317 uint64_t u64; 5318 struct cvmx_ciu_soft_prst_s 5319 { 5320#if __BYTE_ORDER == __BIG_ENDIAN 5321 uint64_t reserved_3_63 : 61; 5322 uint64_t host64 : 1; /**< PCX Host Mode Device Capability (0=32b/1=64b) */ 5323 uint64_t npi : 1; /**< When PCI soft reset is asserted, also reset the 5324 NPI and PNI logic */ 5325 uint64_t soft_prst : 1; /**< Resets the PCIe/sRIO logic in all modes, not just 5326 RC mode. The reset value is based on the 5327 corresponding MIO_RST_CTL[PRTMODE] CSR field: 5328 If PRTMODE == 0, then SOFT_PRST resets to 0 5329 If PRTMODE != 0, then SOFT_PRST resets to 1 5330 When OCTEON is configured to drive the PERST*_L 5331 chip pin (ie. MIO_RST_CTL0[RST_DRV] is set), this 5332 controls the PERST*_L chip pin. */ 5333#else 5334 uint64_t soft_prst : 1; 5335 uint64_t npi : 1; 5336 uint64_t host64 : 1; 5337 uint64_t reserved_3_63 : 61; 5338#endif 5339 } s; 5340 struct cvmx_ciu_soft_prst_s cn30xx; 5341 struct cvmx_ciu_soft_prst_s cn31xx; 5342 struct cvmx_ciu_soft_prst_s cn38xx; 5343 struct cvmx_ciu_soft_prst_s cn38xxp2; 5344 struct cvmx_ciu_soft_prst_s cn50xx; 5345 struct cvmx_ciu_soft_prst_cn52xx 5346 { 5347#if __BYTE_ORDER == __BIG_ENDIAN 5348 uint64_t reserved_1_63 : 63; 5349 uint64_t soft_prst : 1; /**< Reset the PCI bus. Only works when Octane is 5350 configured as a HOST. When OCTEON is a PCI host 5351 (i.e. when PCI_HOST_MODE = 1), This controls 5352 PCI_RST_L. Refer to section 10.11.1. */ 5353#else 5354 uint64_t soft_prst : 1; 5355 uint64_t reserved_1_63 : 63; 5356#endif 5357 } cn52xx; 5358 struct cvmx_ciu_soft_prst_cn52xx cn52xxp1; 5359 struct cvmx_ciu_soft_prst_cn52xx cn56xx; 5360 struct cvmx_ciu_soft_prst_cn52xx cn56xxp1; 5361 struct cvmx_ciu_soft_prst_s cn58xx; 5362 struct cvmx_ciu_soft_prst_s cn58xxp1; 5363 struct cvmx_ciu_soft_prst_cn52xx cn63xx; 5364 struct cvmx_ciu_soft_prst_cn52xx cn63xxp1; 5365}; 5366typedef union cvmx_ciu_soft_prst cvmx_ciu_soft_prst_t; 5367 5368/** 5369 * cvmx_ciu_soft_prst1 5370 */ 5371union cvmx_ciu_soft_prst1 5372{ 5373 uint64_t u64; 5374 struct cvmx_ciu_soft_prst1_s 5375 { 5376#if __BYTE_ORDER == __BIG_ENDIAN 5377 uint64_t reserved_1_63 : 63; 5378 uint64_t soft_prst : 1; /**< Resets the PCIe/sRIO logic in all modes, not just 5379 RC mode. The reset value is based on the 5380 corresponding MIO_RST_CTL[PRTMODE] CSR field: 5381 If PRTMODE == 0, then SOFT_PRST resets to 0 5382 If PRTMODE != 0, then SOFT_PRST resets to 1 5383 When OCTEON is configured to drive the PERST*_L 5384 chip pin (ie. MIO_RST_CTL1[RST_DRV] is set), this 5385 controls the PERST*_L chip pin. */ 5386#else 5387 uint64_t soft_prst : 1; 5388 uint64_t reserved_1_63 : 63; 5389#endif 5390 } s; 5391 struct cvmx_ciu_soft_prst1_s cn52xx; 5392 struct cvmx_ciu_soft_prst1_s cn52xxp1; 5393 struct cvmx_ciu_soft_prst1_s cn56xx; 5394 struct cvmx_ciu_soft_prst1_s cn56xxp1; 5395 struct cvmx_ciu_soft_prst1_s cn63xx; 5396 struct cvmx_ciu_soft_prst1_s cn63xxp1; 5397}; 5398typedef union cvmx_ciu_soft_prst1 cvmx_ciu_soft_prst1_t; 5399 5400/** 5401 * cvmx_ciu_soft_rst 5402 */ 5403union cvmx_ciu_soft_rst 5404{ 5405 uint64_t u64; 5406 struct cvmx_ciu_soft_rst_s 5407 { 5408#if __BYTE_ORDER == __BIG_ENDIAN 5409 uint64_t reserved_1_63 : 63; 5410 uint64_t soft_rst : 1; /**< Resets Octeon 5411 When soft reseting Octeon from a remote PCIe/sRIO 5412 host, always read CIU_SOFT_RST (and wait for 5413 result) before writing SOFT_RST to '1'. */ 5414#else 5415 uint64_t soft_rst : 1; 5416 uint64_t reserved_1_63 : 63; 5417#endif 5418 } s; 5419 struct cvmx_ciu_soft_rst_s cn30xx; 5420 struct cvmx_ciu_soft_rst_s cn31xx; 5421 struct cvmx_ciu_soft_rst_s cn38xx; 5422 struct cvmx_ciu_soft_rst_s cn38xxp2; 5423 struct cvmx_ciu_soft_rst_s cn50xx; 5424 struct cvmx_ciu_soft_rst_s cn52xx; 5425 struct cvmx_ciu_soft_rst_s cn52xxp1; 5426 struct cvmx_ciu_soft_rst_s cn56xx; 5427 struct cvmx_ciu_soft_rst_s cn56xxp1; 5428 struct cvmx_ciu_soft_rst_s cn58xx; 5429 struct cvmx_ciu_soft_rst_s cn58xxp1; 5430 struct cvmx_ciu_soft_rst_s cn63xx; 5431 struct cvmx_ciu_soft_rst_s cn63xxp1; 5432}; 5433typedef union cvmx_ciu_soft_rst cvmx_ciu_soft_rst_t; 5434 5435/** 5436 * cvmx_ciu_tim# 5437 */ 5438union cvmx_ciu_timx 5439{ 5440 uint64_t u64; 5441 struct cvmx_ciu_timx_s 5442 { 5443#if __BYTE_ORDER == __BIG_ENDIAN 5444 uint64_t reserved_37_63 : 27; 5445 uint64_t one_shot : 1; /**< One-shot mode */ 5446 uint64_t len : 36; /**< Timeout length in core clock cycles 5447 Periodic interrupts will occur every LEN+1 core 5448 clock cycles when ONE_SHOT==0 5449 Timer disabled when LEN==0 */ 5450#else 5451 uint64_t len : 36; 5452 uint64_t one_shot : 1; 5453 uint64_t reserved_37_63 : 27; 5454#endif 5455 } s; 5456 struct cvmx_ciu_timx_s cn30xx; 5457 struct cvmx_ciu_timx_s cn31xx; 5458 struct cvmx_ciu_timx_s cn38xx; 5459 struct cvmx_ciu_timx_s cn38xxp2; 5460 struct cvmx_ciu_timx_s cn50xx; 5461 struct cvmx_ciu_timx_s cn52xx; 5462 struct cvmx_ciu_timx_s cn52xxp1; 5463 struct cvmx_ciu_timx_s cn56xx; 5464 struct cvmx_ciu_timx_s cn56xxp1; 5465 struct cvmx_ciu_timx_s cn58xx; 5466 struct cvmx_ciu_timx_s cn58xxp1; 5467 struct cvmx_ciu_timx_s cn63xx; 5468 struct cvmx_ciu_timx_s cn63xxp1; 5469}; 5470typedef union cvmx_ciu_timx cvmx_ciu_timx_t; 5471 5472/** 5473 * cvmx_ciu_wdog# 5474 */ 5475union cvmx_ciu_wdogx 5476{ 5477 uint64_t u64; 5478 struct cvmx_ciu_wdogx_s 5479 { 5480#if __BYTE_ORDER == __BIG_ENDIAN 5481 uint64_t reserved_46_63 : 18; 5482 uint64_t gstopen : 1; /**< GSTOPEN */ 5483 uint64_t dstop : 1; /**< DSTOP */ 5484 uint64_t cnt : 24; /**< Number of 256-cycle intervals until next watchdog 5485 expiration. Cleared on write to associated 5486 CIU_PP_POKE register. */ 5487 uint64_t len : 16; /**< Watchdog time expiration length 5488 The 16 bits of LEN represent the most significant 5489 bits of a 24 bit decrementer that decrements 5490 every 256 cycles. 5491 LEN must be set > 0 */ 5492 uint64_t state : 2; /**< Watchdog state 5493 number of watchdog time expirations since last 5494 PP poke. Cleared on write to associated 5495 CIU_PP_POKE register. */ 5496 uint64_t mode : 2; /**< Watchdog mode 5497 0 = Off 5498 1 = Interrupt Only 5499 2 = Interrupt + NMI 5500 3 = Interrupt + NMI + Soft-Reset */ 5501#else 5502 uint64_t mode : 2; 5503 uint64_t state : 2; 5504 uint64_t len : 16; 5505 uint64_t cnt : 24; 5506 uint64_t dstop : 1; 5507 uint64_t gstopen : 1; 5508 uint64_t reserved_46_63 : 18; 5509#endif 5510 } s; 5511 struct cvmx_ciu_wdogx_s cn30xx; 5512 struct cvmx_ciu_wdogx_s cn31xx; 5513 struct cvmx_ciu_wdogx_s cn38xx; 5514 struct cvmx_ciu_wdogx_s cn38xxp2; 5515 struct cvmx_ciu_wdogx_s cn50xx; 5516 struct cvmx_ciu_wdogx_s cn52xx; 5517 struct cvmx_ciu_wdogx_s cn52xxp1; 5518 struct cvmx_ciu_wdogx_s cn56xx; 5519 struct cvmx_ciu_wdogx_s cn56xxp1; 5520 struct cvmx_ciu_wdogx_s cn58xx; 5521 struct cvmx_ciu_wdogx_s cn58xxp1; 5522 struct cvmx_ciu_wdogx_s cn63xx; 5523 struct cvmx_ciu_wdogx_s cn63xxp1; 5524}; 5525typedef union cvmx_ciu_wdogx cvmx_ciu_wdogx_t; 5526 5527#endif 5528