Searched refs:CVMX_CIU_INTX_EN0 (Results 1 - 7 of 7) sorted by relevance

/freebsd-9.3-release/sys/contrib/octeon-sdk/
H A Dcvmx-debug-uart.c219 irq_control.u64 = cvmx_read_csr(CVMX_CIU_INTX_EN0(newcore * 2));
221 cvmx_write_csr(CVMX_CIU_INTX_EN0(newcore * 2), irq_control.u64);
224 irq_control.u64 = cvmx_read_csr(CVMX_CIU_INTX_EN0(oldcore * 2));
226 cvmx_write_csr(CVMX_CIU_INTX_EN0(oldcore* 2), irq_control.u64);
H A Dcvmx-interrupt.h239 uint64_t mask = cvmx_read_csr(CVMX_CIU_INTX_EN0(ciu_offset));
241 cvmx_write_csr(CVMX_CIU_INTX_EN0(ciu_offset), mask);
274 uint64_t mask = cvmx_read_csr(CVMX_CIU_INTX_EN0(ciu_offset));
276 cvmx_write_csr(CVMX_CIU_INTX_EN0(ciu_offset), mask);
H A Dcvmx-interrupt.c315 uint64_t irq_mask = cvmx_read_csr(CVMX_CIU_INTX_SUM0(ciu_offset)) & cvmx_read_csr(CVMX_CIU_INTX_EN0(ciu_offset));
458 cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2), 0);
459 cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2+1), 0);
H A Dcvmx-ciu-defs.h82 static inline uint64_t CVMX_CIU_INTX_EN0(unsigned long offset) function
93 cvmx_warn("CVMX_CIU_INTX_EN0(%lu) is invalid on this chip\n", offset);
97 #define CVMX_CIU_INTX_EN0(offset) (CVMX_ADD_IO_SEG(0x0001070000000200ull) + ((offset) & 63) * 16) macro
/freebsd-9.3-release/sys/mips/cavium/
H A Dciu.c327 mask = cvmx_read_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2));
329 cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2), mask);
339 mask = cvmx_read_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2));
341 cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2), mask);
354 mask = cvmx_read_csr(CVMX_CIU_INTX_EN0(core*2));
359 cvmx_write_csr(CVMX_CIU_INTX_EN0(core*2), mask);
427 en0_mask = cvmx_read_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2));
H A Docteon_machdep.c252 cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2), 0);
253 cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2+1), 0);
259 cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2+1),
/freebsd-9.3-release/sys/mips/cavium/octe/
H A Dethernet.c278 en.u64 = cvmx_read_csr(CVMX_CIU_INTX_EN0(core*2));
280 cvmx_write_csr(CVMX_CIU_INTX_EN0(core*2), en.u64);

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