/freebsd-13-stable/contrib/llvm-project/compiler-rt/lib/builtins/ |
H A D | popcountti2.c | 21 tu_int x3 = (tu_int)a; local 22 x3 = x3 - ((x3 >> 1) & 25 x3 = ((x3 >> 2) & 27 (x3 & (((tu_int)0x3333333333333333uLL << 64) | 0x3333333333333333uLL)); 29 x3 = (x3 + (x3 >> [all...] |
/freebsd-13-stable/sys/arm/freescale/imx/ |
H A D | imx6_ccmreg.h | 42 #define SSI_CLK_SEL_M 0x3 82 #define CCGR0_AIPS_TZ1 (0x3 << 0) 83 #define CCGR0_AIPS_TZ2 (0x3 << 2) 84 #define CCGR0_ABPHDMA (0x3 << 4) 86 #define CCGR1_ECSPI1 (0x3 << 0) 87 #define CCGR1_ECSPI2 (0x3 << 2) 88 #define CCGR1_ECSPI3 (0x3 << 4) 89 #define CCGR1_ECSPI4 (0x3 << 6) 90 #define CCGR1_ECSPI5 (0x3 << 8) 91 #define CCGR1_ENET (0x3 << 1 [all...] |
/freebsd-13-stable/contrib/bearssl/src/symcipher/ |
H A D | aes_x86ni_cbcdec.c | 66 __m128i x0, x1, x2, x3, e0, e1, e2, e3; local 72 x3 = _mm_loadu_si128((void *)(buf + 48)); 80 x3 = x2; 83 x3 = x1; 88 x3 = x0; 94 e3 = x3; 98 x3 = _mm_xor_si128(x3, sk[0]); 102 x3 = _mm_aesdec_si128(x3, s [all...] |
H A D | aes_x86ni_ctr.c | 69 __m128i x0, x1, x2, x3; local 74 x3 = _mm_insert_epi32(ivx, br_bswap32(cc + 3), 3); 78 x3 = _mm_xor_si128(x3, sk[0]); 82 x3 = _mm_aesenc_si128(x3, sk[1]); 86 x3 = _mm_aesenc_si128(x3, sk[2]); 90 x3 = _mm_aesenc_si128(x3, s [all...] |
H A D | aes_pwr8_ctrcbc.c | 231 #define BLOCK_ENCRYPT_X4_128(x0, x1, x2, x3) \ 235 vxor(x3, x3, 0) \ 239 vcipher(x3, x3, 1) \ 243 vcipher(x3, x3, 2) \ 247 vcipher(x3, x3, 3) \ 251 vcipher(x3, x [all...] |
/freebsd-13-stable/sys/dev/hid/ |
H A D | hconf.h | 36 HCONF_INPUT_MODE_MT_TOUCHPAD = 0x3,
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/freebsd-13-stable/contrib/bearssl/src/rsa/ |
H A D | rsa_pkcs1_sig_pad.c | 33 size_t u, x3, xlen; local 37 * 00 01 FF .. FF 00 30 x1 30 x2 06 x3 OID 05 00 04 x4 HASH 48 * -- x3 is equal to the encoded OID value length (hash_oid[0]). 50 * -- x2 = x3 + 4. 52 * -- x1 = x2 + x4 + 4 = x3 + x4 + 8. 72 x3 = hash_oid[0]; 78 if (xlen < (x3 + hash_len + 21)) { 83 u = xlen - x3 - hash_len - 11; 87 x[u + 2] = x3 + hash_len + 8; 89 x[u + 4] = x3 [all...] |
H A D | rsa_pkcs1_sig_unpad.c | 38 size_t u, x2, x3, pad_len, zlen; local 46 * 00 01 FF ... FF 00 30 x1 30 x2 06 x3 OID [ 05 00 ] 04 x4 HASH 57 * -- x3 is equal to the encoded OID value length (so x3 is the 60 * -- If the "05 00" is present, then x2 == x3 + 4; otherwise, 61 * x2 == x3 + 2. 65 * So the total length after the last "FF" is either x3 + x4 + 11 66 * (with the "05 00") or x3 + x4 + 9 (without the "05 00"). 94 x3 = hash_oid[0]; 95 pad_len = x3 [all...] |
/freebsd-13-stable/sys/arm64/iommu/ |
H A D | smmureg.h | 40 #define IDR0_ST_LVL_M (0x3 << IDR0_ST_LVL_S) 45 #define IDR0_STALL_MODEL_M (0x3 << IDR0_STALL_MODEL_S) 49 #define IDR0_TTENDIAN_M (0x3 << IDR0_TTENDIAN_S) 52 #define IDR0_TTENDIAN_BIG (0x3 << IDR0_TTENDIAN_S) 67 #define IDR0_HTTU_M (0x3 << IDR0_HTTU_S) 73 #define IDR0_TTF_M (0x3 << IDR0_TTF_S) 76 #define IDR0_TTF_ALL (0x3 << IDR0_TTF_S) /* AArch32 and AArch64 */ 103 #define IDR5_VAX_M (0x3 << IDR5_VAX_S) 114 #define IDR5_OAS_42 (0x3 << IDR5_OAS_S) 131 #define CR1_TABLE_SH_M (0x3 << CR1_TABLE_SH_ [all...] |
/freebsd-13-stable/sys/dev/qlnx/qlnxe/ |
H A D | ecore_hsi_fcoe.h | 191 #define XSTORM_FCOE_CONN_ST_CTX_LAST_QUEUE_HANDLED_MASK 0x3 279 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 281 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 283 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 285 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 288 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 290 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 292 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 294 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 297 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF8_MASK 0x3 /* cf [all...] |
H A D | ecore_hsi_iscsi.h | 108 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 110 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 112 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 114 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3 /* timer_stop_all */ 117 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 119 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 121 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 123 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 126 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 128 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF9_MASK 0x3 /* cf [all...] |
H A D | ecore_hsi_rdma.h | 63 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 /* cf0 */ 65 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3 /* cf1 */ 67 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_MASK 0x3 /* cf2special */ 120 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 /* cf0 */ 122 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3 /* cf1 */ 124 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3 /* cf2 */ 188 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_MASK 0x3 /* timer0cf */ 191 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_MASK 0x3 /* timer1cf */ 193 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_MASK 0x3 /* timer2cf */ 195 #define E4_USTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3 /* timer_stop_al [all...] |
H A D | ecore_hsi_roce.h | 136 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3 /* Use roce_flavor enum */ 186 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3 /* Use roce_flavor enum */ 368 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_MASK 0x3 505 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 507 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 509 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 543 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 545 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 547 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 589 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_MASK 0x3 /* timer0c [all...] |
H A D | ecore_hsi_eth.h | 101 #define E4_XSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 103 #define E4_XSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 105 #define E4_XSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 107 #define E4_XSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 110 #define E4_XSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 112 #define E4_XSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 114 #define E4_XSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 116 #define E4_XSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 119 #define E4_XSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 121 #define E4_XSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3 /* cf [all...] |
H A D | ecore_hsi_iwarp.h | 110 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 112 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 114 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 116 #define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3 /* timer_stop_all */ 119 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 121 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 123 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 125 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 128 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 130 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF9_MASK 0x3 /* cf [all...] |
/freebsd-13-stable/lib/libc/powerpc/gen/ |
H A D | fpgetround.c | 48 return ((fp_rnd_t)(fpscr & 0x3));
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/freebsd-13-stable/lib/libc/powerpc64/gen/ |
H A D | fpgetround.c | 48 return ((fp_rnd_t)(fpscr & 0x3));
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/freebsd-13-stable/sys/contrib/device-tree/include/dt-bindings/mux/ |
H A D | mux-j721e-wiz.h | 20 #define SERDES1_LANE0_SGMII_LANE0 0x3 25 #define SERDES1_LANE1_SGMII_LANE1 0x3 28 #define SERDES2_LANE0_SGMII_LANE0 0x3 33 #define SERDES2_LANE1_SGMII_LANE1 0x3
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/freebsd-13-stable/sys/contrib/device-tree/include/dt-bindings/soc/ |
H A D | qcom,apr.h | 8 #define APR_DOMAIN_MODEM 0x3 14 #define APR_SVC_ADSP_CORE 0x3
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/freebsd-13-stable/crypto/openssl/crypto/rc2/ |
H A D | rc2_cbc.c | 92 register RC2_INT x0, x1, x2, x3, t; local 100 x3 = (RC2_INT) (l >> 16L); 107 t = (x0 + (x1 & ~x3) + (x2 & x3) + *(p0++)) & 0xffff; 109 t = (x1 + (x2 & ~x0) + (x3 & x0) + *(p0++)) & 0xffff; 111 t = (x2 + (x3 & ~x1) + (x0 & x1) + *(p0++)) & 0xffff; 113 t = (x3 + (x0 & ~x2) + (x1 & x2) + *(p0++)) & 0xffff; 114 x3 = (t << 5) | (t >> 11); 121 x0 += p1[x3 & 0x3f]; 124 x3 138 register RC2_INT x0, x1, x2, x3, t; local [all...] |
/freebsd-13-stable/sys/contrib/device-tree/src/arm/ |
H A D | imx7ulp-pinfunc.h | 41 #define IMX7ULP_PAD_PTC4__LPSPI2_PCS1 0x0010 0x02a0 0x3 0x1 49 #define IMX7ULP_PAD_PTC5__LPSPI2_PCS2 0x0014 0x02a4 0x3 0x1 57 #define IMX7ULP_PAD_PTC6__LPSPI2_PCS3 0x0018 0x02a8 0x3 0x1 71 #define IMX7ULP_PAD_PTC8__LPSPI2_SIN 0x0020 0x02b0 0x3 0x1 79 #define IMX7ULP_PAD_PTC9__LPSPI2_SOUT 0x0024 0x02b4 0x3 0x1 87 #define IMX7ULP_PAD_PTC10__LPSPI2_SCK 0x0028 0x02ac 0x3 0x1 95 #define IMX7ULP_PAD_PTC11__LPSPI2_PCS0 0x002c 0x029c 0x3 0x1 102 #define IMX7ULP_PAD_PTC12__LPSPI3_PCS1 0x0030 0x0314 0x3 0x1 110 #define IMX7ULP_PAD_PTC13__LPSPI3_PCS2 0x0034 0x0318 0x3 0x1 119 #define IMX7ULP_PAD_PTC14__LPSPI3_PCS3 0x0038 0x031c 0x3 [all...] |
/freebsd-13-stable/sys/mips/atheros/ |
H A D | ar933x_uart.h | 51 #define AR933X_UART_CS_PARITY_M 0x3 56 #define AR933X_UART_CS_IF_MODE_M 0x3 61 #define AR933X_UART_CS_FLOW_CTRL_M 0x3
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/freebsd-13-stable/usr.sbin/dumpcis/ |
H A D | cis.h | 167 #define CIS_FEAT_POWER(x) ((x) & 0x3) 171 #define CIS_FEAT_MEMORY(x) (((x) >> 5) & 0x3) 196 #define CIS_WAIT_SCALE(x) ((x) & 0x3) 262 #define CIS_MEM_LENSZ(x) (((x) >> 3) & 0x3) 263 #define CIS_MEM_ADDRSZ(x) (((x) >> 5) & 0x3) 279 #define CIS_MISC_DMA_REQ(x) (((x) >> 2) & 0x3)
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/freebsd-13-stable/libexec/rtld-elf/aarch64/ |
H A D | rtld_start.S | 69 stp x2, x3, [sp, #-16]! 85 lsl x3, x1, #1 /* x3 = 2 * offset */ 86 add x1, x1, x3 /* x1 = x3 + offset = 3 * offset */ 105 ldp x2, x3, [sp], #16 159 stp x3, x4, [sp, #(1 * 16)] 163 .cfi_rel_offset x3, 16 171 ldr x3, [x1] /* tlsdec->dtv_gen */ 172 cmp x2, x3 [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARC/MCTargetDesc/ |
H A D | ARCInfo.h | 28 P = 0x3, 49 BRGE = 0x3,
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