1/* 2 * Copyright (c) 2017-2018 Cavium, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31#ifndef __ECORE_HSI_FCOE__ 32#define __ECORE_HSI_FCOE__ 33/****************************************/ 34/* Add include to common storage target */ 35/****************************************/ 36#include "storage_common.h" 37 38/************************************************************************/ 39/* Add include to common fcoe target for both eCore and protocol driver */ 40/************************************************************************/ 41#include "fcoe_common.h" 42 43/* 44 * The fcoe storm context of Ystorm 45 */ 46struct ystorm_fcoe_conn_st_ctx 47{ 48 u8 func_mode /* Function mode */; 49 u8 cos /* Transmission cos */; 50 u8 conf_version /* Is dcb_version or vntag_version changed */; 51 u8 eth_hdr_size /* Ethernet header size */; 52 __le16 stat_ram_addr /* Statistics ram adderss */; 53 __le16 mtu /* MTU limitation */; 54 __le16 max_fc_payload_len /* Max payload length according to target limitation and mtu. 8 bytes aligned (required for protection fast-path) */; 55 __le16 tx_max_fc_pay_len /* Max payload length according to target limitation */; 56 u8 fcp_cmd_size /* FCP cmd size. for performance reasons */; 57 u8 fcp_rsp_size /* FCP RSP size. for performance reasons */; 58 __le16 mss /* MSS for PBF (MSS we negotiate with target - protection data per segment. If we are not in perf mode it will be according to worse case) */; 59 struct regpair reserved; 60 __le16 min_frame_size /* The minimum ETH frame size required for transmission (including ETH header) */; 61 u8 protection_info_flags; 62#define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK 0x1 /* Does this connection support protection (if couple of GOS share this connection it�� ��������������s enough that one of them support protection) */ 63#define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_SHIFT 0 64#define YSTORM_FCOE_CONN_ST_CTX_VALID_MASK 0x1 /* Are we in protection perf mode (there is only one protection mode for this connection and we manage to create mss that contain fixed amount of protection segment and we are only restrict by the target limitation and not line mss this is critical since if line mss restrict us we can�� ��������������t rely on this size �� �������������� it depends on vlan num) */ 65#define YSTORM_FCOE_CONN_ST_CTX_VALID_SHIFT 1 66#define YSTORM_FCOE_CONN_ST_CTX_RESERVED1_MASK 0x3F 67#define YSTORM_FCOE_CONN_ST_CTX_RESERVED1_SHIFT 2 68 u8 dst_protection_per_mss /* Destination Protection data per mss (if we are not in perf mode it will be worse case). Destination is the data add/remove from the transmitted packet (as opposed to src which is data validate by the nic they might not be identical) */; 69 u8 src_protection_per_mss /* Source Protection data per mss (if we are not in perf mode it will be worse case). Source is the data validated by the nic (as opposed to destination which is data add/remove from the transmitted packet they might not be identical) */; 70 u8 ptu_log_page_size /* 0-4K, 1-8K, 2-16K, 3-32K... */; 71 u8 flags; 72#define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1 /* Inner Vlan flag */ 73#define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT 0 74#define YSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK 0x1 /* Outer Vlan flag */ 75#define YSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_SHIFT 1 76#define YSTORM_FCOE_CONN_ST_CTX_RSRV_MASK 0x3F 77#define YSTORM_FCOE_CONN_ST_CTX_RSRV_SHIFT 2 78 u8 fcp_xfer_size /* FCP xfer size. for performance reasons */; 79}; 80 81/* 82 * FCoE 16-bits vlan structure 83 */ 84struct fcoe_vlan_fields 85{ 86 __le16 fields; 87#define FCOE_VLAN_FIELDS_VID_MASK 0xFFF 88#define FCOE_VLAN_FIELDS_VID_SHIFT 0 89#define FCOE_VLAN_FIELDS_CLI_MASK 0x1 90#define FCOE_VLAN_FIELDS_CLI_SHIFT 12 91#define FCOE_VLAN_FIELDS_PRI_MASK 0x7 92#define FCOE_VLAN_FIELDS_PRI_SHIFT 13 93}; 94 95/* 96 * FCoE 16-bits vlan union 97 */ 98union fcoe_vlan_field_union 99{ 100 struct fcoe_vlan_fields fields /* Parameters field */; 101 __le16 val /* Global value */; 102}; 103 104/* 105 * FCoE 16-bits vlan, vif union 106 */ 107union fcoe_vlan_vif_field_union 108{ 109 union fcoe_vlan_field_union vlan /* Vlan */; 110 __le16 vif /* VIF */; 111}; 112 113/* 114 * Ethernet context section 115 */ 116struct pstorm_fcoe_eth_context_section 117{ 118 u8 remote_addr_3 /* Remote Mac Address, used in PBF Header Builder Command */; 119 u8 remote_addr_2 /* Remote Mac Address, used in PBF Header Builder Command */; 120 u8 remote_addr_1 /* Remote Mac Address, used in PBF Header Builder Command */; 121 u8 remote_addr_0 /* Remote Mac Address, used in PBF Header Builder Command */; 122 u8 local_addr_1 /* Local Mac Address, used in PBF Header Builder Command */; 123 u8 local_addr_0 /* Local Mac Address, used in PBF Header Builder Command */; 124 u8 remote_addr_5 /* Remote Mac Address, used in PBF Header Builder Command */; 125 u8 remote_addr_4 /* Remote Mac Address, used in PBF Header Builder Command */; 126 u8 local_addr_5 /* Local Mac Address, used in PBF Header Builder Command */; 127 u8 local_addr_4 /* Loca lMac Address, used in PBF Header Builder Command */; 128 u8 local_addr_3 /* Local Mac Address, used in PBF Header Builder Command */; 129 u8 local_addr_2 /* Local Mac Address, used in PBF Header Builder Command */; 130 union fcoe_vlan_vif_field_union vif_outer_vlan /* Union of VIF and outer vlan */; 131 __le16 vif_outer_eth_type /* reserved place for Ethernet type */; 132 union fcoe_vlan_vif_field_union inner_vlan /* inner vlan tag */; 133 __le16 inner_eth_type /* reserved place for Ethernet type */; 134}; 135 136/* 137 * The fcoe storm context of Pstorm 138 */ 139struct pstorm_fcoe_conn_st_ctx 140{ 141 u8 func_mode /* Function mode */; 142 u8 cos /* Transmission cos */; 143 u8 conf_version /* Is dcb_version or vntag_version changed */; 144 u8 rsrv; 145 __le16 stat_ram_addr /* Statistics ram adderss */; 146 __le16 mss /* MSS for PBF (MSS we negotiate with target - protection data per segment. If we are not in perf mode it will be according to worse case) */; 147 struct regpair abts_cleanup_addr /* Host addr of ABTS /Cleanup info. since we pass it through session context, we pass only the addr to save space */; 148 struct pstorm_fcoe_eth_context_section eth /* Source mac */; 149 u8 sid_2 /* SID FC address - Third byte that is sent to NW via PBF For example is SID is 01:02:03 then sid_2 is 0x03 */; 150 u8 sid_1 /* SID FC address - Second byte that is sent to NW via PBF */; 151 u8 sid_0 /* SID FC address - First byte that is sent to NW via PBF */; 152 u8 flags; 153#define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_MASK 0x1 /* Is inner vlan taken from vntag default vlan (in this case I have to update inner vlan each time the default change) */ 154#define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_SHIFT 0 155#define PSTORM_FCOE_CONN_ST_CTX_SUPPORT_REC_RR_TOV_MASK 0x1 /* AreSupport rec_tov timer */ 156#define PSTORM_FCOE_CONN_ST_CTX_SUPPORT_REC_RR_TOV_SHIFT 1 157#define PSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1 /* Inner Vlan flag */ 158#define PSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT 2 159#define PSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK 0x1 /* Outer Vlan flag */ 160#define PSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_SHIFT 3 161#define PSTORM_FCOE_CONN_ST_CTX_SINGLE_VLAN_FLAG_MASK 0x1 /* Indicaiton that there should be a single vlan (for UFP mode) */ 162#define PSTORM_FCOE_CONN_ST_CTX_SINGLE_VLAN_FLAG_SHIFT 4 163#define PSTORM_FCOE_CONN_ST_CTX_RESERVED_MASK 0x7 164#define PSTORM_FCOE_CONN_ST_CTX_RESERVED_SHIFT 5 165 u8 did_2 /* DID FC address - Third byte that is sent to NW via PBF */; 166 u8 did_1 /* DID FC address - Second byte that is sent to NW via PBF */; 167 u8 did_0 /* DID FC address - First byte that is sent to NW via PBF */; 168 u8 src_mac_index; 169 __le16 rec_rr_tov_val /* REC_TOV value negotiated during PLOGI (in msec) */; 170 u8 q_relative_offset /* CQ, RQ (and CMDQ) relative offset for connection */; 171 u8 reserved1; 172}; 173 174/* 175 * The fcoe storm context of Xstorm 176 */ 177struct xstorm_fcoe_conn_st_ctx 178{ 179 u8 func_mode /* Function mode */; 180 u8 src_mac_index /* Index to the src_mac arr held in the xStorm RAM. Provided at the xStorm offload connection handler */; 181 u8 conf_version /* Advance if vntag/dcb version advance */; 182 u8 cached_wqes_avail /* Number of cached wqes available */; 183 __le16 stat_ram_addr /* Statistics ram adderss */; 184 u8 flags; 185#define XSTORM_FCOE_CONN_ST_CTX_SQ_DEFERRED_MASK 0x1 /* SQ deferred (happens when we wait for xfer wqe to complete cleanup/abts */ 186#define XSTORM_FCOE_CONN_ST_CTX_SQ_DEFERRED_SHIFT 0 187#define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1 /* Inner vlan flag ����� for calculating eth header size */ 188#define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT 1 189#define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_ORIG_MASK 0x1 /* Original vlan configuration. used when we switch from dcb enable to dcb disabled */ 190#define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_ORIG_SHIFT 2 191#define XSTORM_FCOE_CONN_ST_CTX_LAST_QUEUE_HANDLED_MASK 0x3 192#define XSTORM_FCOE_CONN_ST_CTX_LAST_QUEUE_HANDLED_SHIFT 3 193#define XSTORM_FCOE_CONN_ST_CTX_RSRV_MASK 0x7 194#define XSTORM_FCOE_CONN_ST_CTX_RSRV_SHIFT 5 195 u8 cached_wqes_offset /* Offset of first valid cached wqe */; 196 u8 reserved2; 197 u8 eth_hdr_size /* Ethernet header size */; 198 u8 seq_id /* Sequence id */; 199 u8 max_conc_seqs /* Max concurrent sequence id */; 200 __le16 num_pages_in_pbl /* Num of pages in SQ/RESPQ/XFERQ Pbl */; 201 __le16 reserved; 202 struct regpair sq_pbl_addr /* SQ address */; 203 struct regpair sq_curr_page_addr /* SQ current page address */; 204 struct regpair sq_next_page_addr /* SQ next page address */; 205 struct regpair xferq_pbl_addr /* XFERQ address */; 206 struct regpair xferq_curr_page_addr /* XFERQ current page address */; 207 struct regpair xferq_next_page_addr /* XFERQ next page address */; 208 struct regpair respq_pbl_addr /* RESPQ address */; 209 struct regpair respq_curr_page_addr /* RESPQ current page address */; 210 struct regpair respq_next_page_addr /* RESPQ next page address */; 211 __le16 mtu /* MTU limitation */; 212 __le16 tx_max_fc_pay_len /* Max payload length according to target limitation */; 213 __le16 max_fc_payload_len /* Max payload length according to target limitation and mtu. Aligned to 4 bytes. */; 214 __le16 min_frame_size /* The minimum ETH frame size required for transmission (including ETH header, excluding ETH CRC */; 215 __le16 sq_pbl_next_index /* Next index of SQ Pbl */; 216 __le16 respq_pbl_next_index /* Next index of RESPQ Pbl */; 217 u8 fcp_cmd_byte_credit /* Pre-calculated byte credit that single FCP command can consume */; 218 u8 fcp_rsp_byte_credit /* Pre-calculated byte credit that single FCP RSP can consume. */; 219 __le16 protection_info; 220#define XSTORM_FCOE_CONN_ST_CTX_PROTECTION_PERF_MASK 0x1 /* Intend to accelerate the protection flows */ 221#define XSTORM_FCOE_CONN_ST_CTX_PROTECTION_PERF_SHIFT 0 222#define XSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK 0x1 /* Does this connection support protection (if couple of GOS share this connection is enough that one of them support protection) */ 223#define XSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_SHIFT 1 224#define XSTORM_FCOE_CONN_ST_CTX_VALID_MASK 0x1 /* Are we in protection perf mode (there is only one protection mode for this connection and we manage to create mss that contain fixed amount of protection segment and we are only restrict by the target limitation and not line mss this is critical since if line mss restrict us we can��������t rely on this size ����� it depends on vlan num) */ 225#define XSTORM_FCOE_CONN_ST_CTX_VALID_SHIFT 2 226#define XSTORM_FCOE_CONN_ST_CTX_FRAME_PROT_ALIGNED_MASK 0x1 /* Is size of tx_max_pay_len_prot can be aligned to protection intervals. This means that pure data in each frame is 2k exactly, and protection intervals are no bigger than 2k */ 227#define XSTORM_FCOE_CONN_ST_CTX_FRAME_PROT_ALIGNED_SHIFT 3 228#define XSTORM_FCOE_CONN_ST_CTX_RESERVED3_MASK 0xF 229#define XSTORM_FCOE_CONN_ST_CTX_RESERVED3_SHIFT 4 230#define XSTORM_FCOE_CONN_ST_CTX_DST_PROTECTION_PER_MSS_MASK 0xFF /* Destination Pro tection data per mss (if we are not in perf mode it will be worse case). Destination is the data add/remove from the transmitted packet (as opposed to src which is data validate by the nic they might not be identical) */ 231#define XSTORM_FCOE_CONN_ST_CTX_DST_PROTECTION_PER_MSS_SHIFT 8 232 __le16 xferq_pbl_next_index /* Next index of XFERQ Pbl */; 233 __le16 page_size /* Page size (in bytes) */; 234 u8 mid_seq /* Equals 1 for Middle sequence indication, otherwise 0 */; 235 u8 fcp_xfer_byte_credit /* Pre-calculated byte credit that single FCP command can consume */; 236 u8 reserved1[2]; 237 struct fcoe_wqe cached_wqes[16] /* cached wqe (8) = 8*8*8Bytes */; 238}; 239 240struct e4_xstorm_fcoe_conn_ag_ctx 241{ 242 u8 reserved0 /* cdu_validation */; 243 u8 state /* state */; 244 u8 flags0; 245#define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 246#define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 247#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm1 */ 248#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED1_SHIFT 1 249#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED2_MASK 0x1 /* exist_in_qm2 */ 250#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED2_SHIFT 2 251#define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 252#define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 253#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */ 254#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED3_SHIFT 4 255#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED4_MASK 0x1 /* cf_array_active */ 256#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED4_SHIFT 5 257#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */ 258#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED5_SHIFT 6 259#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */ 260#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED6_SHIFT 7 261 u8 flags1; 262#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */ 263#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED7_SHIFT 0 264#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */ 265#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED8_SHIFT 1 266#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED9_MASK 0x1 /* bit10 */ 267#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED9_SHIFT 2 268#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */ 269#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT11_SHIFT 3 270#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */ 271#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT12_SHIFT 4 272#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT13_MASK 0x1 /* bit13 */ 273#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT13_SHIFT 5 274#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT14_MASK 0x1 /* bit14 */ 275#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT14_SHIFT 6 276#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT15_MASK 0x1 /* bit15 */ 277#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT15_SHIFT 7 278 u8 flags2; 279#define E4_XSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 280#define E4_XSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 0 281#define E4_XSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 282#define E4_XSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 2 283#define E4_XSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 284#define E4_XSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 4 285#define E4_XSTORM_FCOE_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 286#define E4_XSTORM_FCOE_CONN_AG_CTX_CF3_SHIFT 6 287 u8 flags3; 288#define E4_XSTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 289#define E4_XSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 0 290#define E4_XSTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 291#define E4_XSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 2 292#define E4_XSTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 293#define E4_XSTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 4 294#define E4_XSTORM_FCOE_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 295#define E4_XSTORM_FCOE_CONN_AG_CTX_CF7_SHIFT 6 296 u8 flags4; 297#define E4_XSTORM_FCOE_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 298#define E4_XSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT 0 299#define E4_XSTORM_FCOE_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 300#define E4_XSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT 2 301#define E4_XSTORM_FCOE_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 302#define E4_XSTORM_FCOE_CONN_AG_CTX_CF10_SHIFT 4 303#define E4_XSTORM_FCOE_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */ 304#define E4_XSTORM_FCOE_CONN_AG_CTX_CF11_SHIFT 6 305 u8 flags5; 306#define E4_XSTORM_FCOE_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */ 307#define E4_XSTORM_FCOE_CONN_AG_CTX_CF12_SHIFT 0 308#define E4_XSTORM_FCOE_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */ 309#define E4_XSTORM_FCOE_CONN_AG_CTX_CF13_SHIFT 2 310#define E4_XSTORM_FCOE_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */ 311#define E4_XSTORM_FCOE_CONN_AG_CTX_CF14_SHIFT 4 312#define E4_XSTORM_FCOE_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */ 313#define E4_XSTORM_FCOE_CONN_AG_CTX_CF15_SHIFT 6 314 u8 flags6; 315#define E4_XSTORM_FCOE_CONN_AG_CTX_CF16_MASK 0x3 /* cf16 */ 316#define E4_XSTORM_FCOE_CONN_AG_CTX_CF16_SHIFT 0 317#define E4_XSTORM_FCOE_CONN_AG_CTX_CF17_MASK 0x3 /* cf_array_cf */ 318#define E4_XSTORM_FCOE_CONN_AG_CTX_CF17_SHIFT 2 319#define E4_XSTORM_FCOE_CONN_AG_CTX_CF18_MASK 0x3 /* cf18 */ 320#define E4_XSTORM_FCOE_CONN_AG_CTX_CF18_SHIFT 4 321#define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_MASK 0x3 /* cf19 */ 322#define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_SHIFT 6 323 u8 flags7; 324#define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf20 */ 325#define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 326#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED10_MASK 0x3 /* cf21 */ 327#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED10_SHIFT 2 328#define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */ 329#define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_SHIFT 4 330#define E4_XSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 331#define E4_XSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 6 332#define E4_XSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 333#define E4_XSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 7 334 u8 flags8; 335#define E4_XSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 336#define E4_XSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 0 337#define E4_XSTORM_FCOE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 338#define E4_XSTORM_FCOE_CONN_AG_CTX_CF3EN_SHIFT 1 339#define E4_XSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 340#define E4_XSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 2 341#define E4_XSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 342#define E4_XSTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 3 343#define E4_XSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 344#define E4_XSTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 4 345#define E4_XSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 346#define E4_XSTORM_FCOE_CONN_AG_CTX_CF7EN_SHIFT 5 347#define E4_XSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 348#define E4_XSTORM_FCOE_CONN_AG_CTX_CF8EN_SHIFT 6 349#define E4_XSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 350#define E4_XSTORM_FCOE_CONN_AG_CTX_CF9EN_SHIFT 7 351 u8 flags9; 352#define E4_XSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 353#define E4_XSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT 0 354#define E4_XSTORM_FCOE_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */ 355#define E4_XSTORM_FCOE_CONN_AG_CTX_CF11EN_SHIFT 1 356#define E4_XSTORM_FCOE_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */ 357#define E4_XSTORM_FCOE_CONN_AG_CTX_CF12EN_SHIFT 2 358#define E4_XSTORM_FCOE_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */ 359#define E4_XSTORM_FCOE_CONN_AG_CTX_CF13EN_SHIFT 3 360#define E4_XSTORM_FCOE_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */ 361#define E4_XSTORM_FCOE_CONN_AG_CTX_CF14EN_SHIFT 4 362#define E4_XSTORM_FCOE_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */ 363#define E4_XSTORM_FCOE_CONN_AG_CTX_CF15EN_SHIFT 5 364#define E4_XSTORM_FCOE_CONN_AG_CTX_CF16EN_MASK 0x1 /* cf16en */ 365#define E4_XSTORM_FCOE_CONN_AG_CTX_CF16EN_SHIFT 6 366#define E4_XSTORM_FCOE_CONN_AG_CTX_CF17EN_MASK 0x1 /* cf_array_cf_en */ 367#define E4_XSTORM_FCOE_CONN_AG_CTX_CF17EN_SHIFT 7 368 u8 flags10; 369#define E4_XSTORM_FCOE_CONN_AG_CTX_CF18EN_MASK 0x1 /* cf18en */ 370#define E4_XSTORM_FCOE_CONN_AG_CTX_CF18EN_SHIFT 0 371#define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 /* cf19en */ 372#define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_SHIFT 1 373#define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 /* cf20en */ 374#define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 375#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED11_MASK 0x1 /* cf21en */ 376#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED11_SHIFT 3 377#define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 378#define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 379#define E4_XSTORM_FCOE_CONN_AG_CTX_CF23EN_MASK 0x1 /* cf23en */ 380#define E4_XSTORM_FCOE_CONN_AG_CTX_CF23EN_SHIFT 5 381#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED12_MASK 0x1 /* rule0en */ 382#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED12_SHIFT 6 383#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED13_MASK 0x1 /* rule1en */ 384#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED13_SHIFT 7 385 u8 flags11; 386#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED14_MASK 0x1 /* rule2en */ 387#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED14_SHIFT 0 388#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED15_MASK 0x1 /* rule3en */ 389#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED15_SHIFT 1 390#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED16_MASK 0x1 /* rule4en */ 391#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED16_SHIFT 2 392#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 393#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 3 394#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 395#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 4 396#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 397#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 5 398#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */ 399#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 400#define E4_XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_MASK 0x1 /* rule9en */ 401#define E4_XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_SHIFT 7 402 u8 flags12; 403#define E4_XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_MASK 0x1 /* rule10en */ 404#define E4_XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_SHIFT 0 405#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */ 406#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE11EN_SHIFT 1 407#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */ 408#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 409#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */ 410#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 411#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE14EN_MASK 0x1 /* rule14en */ 412#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE14EN_SHIFT 4 413#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */ 414#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE15EN_SHIFT 5 415#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */ 416#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE16EN_SHIFT 6 417#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */ 418#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE17EN_SHIFT 7 419 u8 flags13; 420#define E4_XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_MASK 0x1 /* rule18en */ 421#define E4_XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_SHIFT 0 422#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */ 423#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE19EN_SHIFT 1 424#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */ 425#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 426#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */ 427#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 428#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */ 429#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 430#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */ 431#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 432#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */ 433#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 434#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */ 435#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 436 u8 flags14; 437#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT16_MASK 0x1 /* bit16 */ 438#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT16_SHIFT 0 439#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT17_MASK 0x1 /* bit17 */ 440#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT17_SHIFT 1 441#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT18_MASK 0x1 /* bit18 */ 442#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT18_SHIFT 2 443#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT19_MASK 0x1 /* bit19 */ 444#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT19_SHIFT 3 445#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT20_MASK 0x1 /* bit20 */ 446#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT20_SHIFT 4 447#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT21_MASK 0x1 /* bit21 */ 448#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT21_SHIFT 5 449#define E4_XSTORM_FCOE_CONN_AG_CTX_CF23_MASK 0x3 /* cf23 */ 450#define E4_XSTORM_FCOE_CONN_AG_CTX_CF23_SHIFT 6 451 u8 byte2 /* byte2 */; 452 __le16 physical_q0 /* physical_q0 */; 453 __le16 word1 /* physical_q1 */; 454 __le16 word2 /* physical_q2 */; 455 __le16 sq_cons /* word3 */; 456 __le16 sq_prod /* word4 */; 457 __le16 xferq_prod /* word5 */; 458 __le16 xferq_cons /* conn_dpi */; 459 u8 byte3 /* byte3 */; 460 u8 byte4 /* byte4 */; 461 u8 byte5 /* byte5 */; 462 u8 byte6 /* byte6 */; 463 __le32 remain_io /* reg0 */; 464 __le32 reg1 /* reg1 */; 465 __le32 reg2 /* reg2 */; 466 __le32 reg3 /* reg3 */; 467 __le32 reg4 /* reg4 */; 468 __le32 reg5 /* cf_array0 */; 469 __le32 reg6 /* cf_array1 */; 470 __le16 respq_prod /* word7 */; 471 __le16 respq_cons /* word8 */; 472 __le16 word9 /* word9 */; 473 __le16 word10 /* word10 */; 474 __le32 reg7 /* reg7 */; 475 __le32 reg8 /* reg8 */; 476}; 477 478/* 479 * The fcoe storm context of Ustorm 480 */ 481struct ustorm_fcoe_conn_st_ctx 482{ 483 struct regpair respq_pbl_addr /* RespQ Pbl base address */; 484 __le16 num_pages_in_pbl /* Number of RespQ pbl pages (both have same wqe size) */; 485 u8 ptu_log_page_size /* 0-4K, 1-8K, 2-16K, 3-32K... */; 486 u8 log_page_size; 487 __le16 respq_prod /* RespQ producer */; 488 u8 reserved[2]; 489}; 490 491struct e4_tstorm_fcoe_conn_ag_ctx 492{ 493 u8 reserved0 /* cdu_validation */; 494 u8 state /* state */; 495 u8 flags0; 496#define E4_TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 497#define E4_TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 498#define E4_TSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 499#define E4_TSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1 500#define E4_TSTORM_FCOE_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 501#define E4_TSTORM_FCOE_CONN_AG_CTX_BIT2_SHIFT 2 502#define E4_TSTORM_FCOE_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 503#define E4_TSTORM_FCOE_CONN_AG_CTX_BIT3_SHIFT 3 504#define E4_TSTORM_FCOE_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 505#define E4_TSTORM_FCOE_CONN_AG_CTX_BIT4_SHIFT 4 506#define E4_TSTORM_FCOE_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */ 507#define E4_TSTORM_FCOE_CONN_AG_CTX_BIT5_SHIFT 5 508#define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_MASK 0x3 /* timer0cf */ 509#define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_SHIFT 6 510 u8 flags1; 511#define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* timer1cf */ 512#define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 0 513#define E4_TSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 514#define E4_TSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 2 515#define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3 /* timer_stop_all */ 516#define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4 517#define E4_TSTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 518#define E4_TSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 6 519 u8 flags2; 520#define E4_TSTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 521#define E4_TSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 0 522#define E4_TSTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 523#define E4_TSTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 2 524#define E4_TSTORM_FCOE_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 525#define E4_TSTORM_FCOE_CONN_AG_CTX_CF7_SHIFT 4 526#define E4_TSTORM_FCOE_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 527#define E4_TSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT 6 528 u8 flags3; 529#define E4_TSTORM_FCOE_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 530#define E4_TSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT 0 531#define E4_TSTORM_FCOE_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 532#define E4_TSTORM_FCOE_CONN_AG_CTX_CF10_SHIFT 2 533#define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_MASK 0x1 /* cf0en */ 534#define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_SHIFT 4 535#define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf1en */ 536#define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5 537#define E4_TSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 538#define E4_TSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 6 539#define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1 /* cf3en */ 540#define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7 541 u8 flags4; 542#define E4_TSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 543#define E4_TSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 0 544#define E4_TSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 545#define E4_TSTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 1 546#define E4_TSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 547#define E4_TSTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 2 548#define E4_TSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 549#define E4_TSTORM_FCOE_CONN_AG_CTX_CF7EN_SHIFT 3 550#define E4_TSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 551#define E4_TSTORM_FCOE_CONN_AG_CTX_CF8EN_SHIFT 4 552#define E4_TSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 553#define E4_TSTORM_FCOE_CONN_AG_CTX_CF9EN_SHIFT 5 554#define E4_TSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 555#define E4_TSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT 6 556#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 557#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 7 558 u8 flags5; 559#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 560#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 0 561#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 562#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 1 563#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 564#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 2 565#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 566#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 3 567#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 568#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 4 569#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 570#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 5 571#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 572#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 6 573#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 574#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE8EN_SHIFT 7 575 __le32 reg0 /* reg0 */; 576 __le32 reg1 /* reg1 */; 577}; 578 579struct e4_ustorm_fcoe_conn_ag_ctx 580{ 581 u8 byte0 /* cdu_validation */; 582 u8 byte1 /* state */; 583 u8 flags0; 584#define E4_USTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 585#define E4_USTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0 586#define E4_USTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 587#define E4_USTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1 588#define E4_USTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 589#define E4_USTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2 590#define E4_USTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 591#define E4_USTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4 592#define E4_USTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 593#define E4_USTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6 594 u8 flags1; 595#define E4_USTORM_FCOE_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 596#define E4_USTORM_FCOE_CONN_AG_CTX_CF3_SHIFT 0 597#define E4_USTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 598#define E4_USTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 2 599#define E4_USTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 600#define E4_USTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 4 601#define E4_USTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 602#define E4_USTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 6 603 u8 flags2; 604#define E4_USTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 605#define E4_USTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0 606#define E4_USTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 607#define E4_USTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1 608#define E4_USTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 609#define E4_USTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2 610#define E4_USTORM_FCOE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 611#define E4_USTORM_FCOE_CONN_AG_CTX_CF3EN_SHIFT 3 612#define E4_USTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 613#define E4_USTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 4 614#define E4_USTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 615#define E4_USTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 5 616#define E4_USTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 617#define E4_USTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 6 618#define E4_USTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 619#define E4_USTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 7 620 u8 flags3; 621#define E4_USTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 622#define E4_USTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 0 623#define E4_USTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 624#define E4_USTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 1 625#define E4_USTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 626#define E4_USTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 2 627#define E4_USTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 628#define E4_USTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 3 629#define E4_USTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 630#define E4_USTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 4 631#define E4_USTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 632#define E4_USTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 5 633#define E4_USTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 634#define E4_USTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 6 635#define E4_USTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 636#define E4_USTORM_FCOE_CONN_AG_CTX_RULE8EN_SHIFT 7 637 u8 byte2 /* byte2 */; 638 u8 byte3 /* byte3 */; 639 __le16 word0 /* conn_dpi */; 640 __le16 word1 /* word1 */; 641 __le32 reg0 /* reg0 */; 642 __le32 reg1 /* reg1 */; 643 __le32 reg2 /* reg2 */; 644 __le32 reg3 /* reg3 */; 645 __le16 word2 /* word2 */; 646 __le16 word3 /* word3 */; 647}; 648 649/* 650 * The fcoe storm context of Tstorm 651 */ 652struct tstorm_fcoe_conn_st_ctx 653{ 654 __le16 stat_ram_addr /* Statistics ram adderss */; 655 __le16 rx_max_fc_payload_len /* Max rx fc payload length. provided in ramrod */; 656 __le16 e_d_tov_val /* E_D_TOV value negotiated during PLOGI (in msec) */; 657 u8 flags; 658#define TSTORM_FCOE_CONN_ST_CTX_INC_SEQ_CNT_MASK 0x1 /* Does the target support increment sequence counter */ 659#define TSTORM_FCOE_CONN_ST_CTX_INC_SEQ_CNT_SHIFT 0 660#define TSTORM_FCOE_CONN_ST_CTX_SUPPORT_CONF_MASK 0x1 /* Does the connection support CONF REQ transmission */ 661#define TSTORM_FCOE_CONN_ST_CTX_SUPPORT_CONF_SHIFT 1 662#define TSTORM_FCOE_CONN_ST_CTX_DEF_Q_IDX_MASK 0x3F /* Default queue index the connection associated to */ 663#define TSTORM_FCOE_CONN_ST_CTX_DEF_Q_IDX_SHIFT 2 664 u8 timers_cleanup_invocation_cnt /* This variable is incremented each time the tStorm handler for timers cleanup is invoked within the same timers cleanup flow */; 665 __le32 reserved1[2]; 666 __le32 dstMacAddressBytes0To3 /* destination MAC address: Bytes 0-3. */; 667 __le16 dstMacAddressBytes4To5 /* destination MAC address: Bytes 4-5. */; 668 __le16 ramrodEcho /* Saved ramrod echo - needed for 2nd round of terminate_conn (flush Q0) */; 669 u8 flags1; 670#define TSTORM_FCOE_CONN_ST_CTX_MODE_MASK 0x3 /* Indicate the mode of the connection: Target or Initiator, use enum fcoe_mode_type */ 671#define TSTORM_FCOE_CONN_ST_CTX_MODE_SHIFT 0 672#define TSTORM_FCOE_CONN_ST_CTX_RESERVED_MASK 0x3F 673#define TSTORM_FCOE_CONN_ST_CTX_RESERVED_SHIFT 2 674 u8 cq_relative_offset /* CQ relative offset for connection */; 675 u8 cmdq_relative_offset /* CmdQ relative offset for connection */; 676 u8 bdq_resource_id /* The BDQ resource ID to which this function is mapped */; 677 u8 reserved0[4] /* Alignment to 128b */; 678}; 679 680struct e4_mstorm_fcoe_conn_ag_ctx 681{ 682 u8 byte0 /* cdu_validation */; 683 u8 byte1 /* state */; 684 u8 flags0; 685#define E4_MSTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 686#define E4_MSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0 687#define E4_MSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 688#define E4_MSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1 689#define E4_MSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 690#define E4_MSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2 691#define E4_MSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 692#define E4_MSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4 693#define E4_MSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 694#define E4_MSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6 695 u8 flags1; 696#define E4_MSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 697#define E4_MSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0 698#define E4_MSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 699#define E4_MSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1 700#define E4_MSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 701#define E4_MSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2 702#define E4_MSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 703#define E4_MSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 3 704#define E4_MSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 705#define E4_MSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 4 706#define E4_MSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 707#define E4_MSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 5 708#define E4_MSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 709#define E4_MSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 6 710#define E4_MSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 711#define E4_MSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 7 712 __le16 word0 /* word0 */; 713 __le16 word1 /* word1 */; 714 __le32 reg0 /* reg0 */; 715 __le32 reg1 /* reg1 */; 716}; 717 718/* 719 * Fast path part of the fcoe storm context of Mstorm 720 */ 721struct fcoe_mstorm_fcoe_conn_st_ctx_fp 722{ 723 __le16 xfer_prod /* XferQ producer */; 724 u8 num_cqs /* Number of CQs per function (internal to FW) */; 725 u8 reserved1; 726 u8 protection_info; 727#define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_SUPPORT_PROTECTION_MASK 0x1 /* Does this connection support protection (if couple of GOS share this connection it is enough that one of them support protection) */ 728#define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_SUPPORT_PROTECTION_SHIFT 0 729#define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_VALID_MASK 0x1 /* Are we in protection perf mode (there is only one protection mode for this connection and we manage to create mss that contain fixed amount of protection segment and we are only restrict by the target limitation and not line mss ����� this is critical since if line mss restrict us we can��������t rely on this size ����� it depends on vlan num) */ 730#define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_VALID_SHIFT 1 731#define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_RESERVED0_MASK 0x3F 732#define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_RESERVED0_SHIFT 2 733 u8 q_relative_offset /* CQ, RQ and CMDQ relative offset for connection */; 734 u8 reserved2[2]; 735}; 736 737/* 738 * Non fast path part of the fcoe storm context of Mstorm 739 */ 740struct fcoe_mstorm_fcoe_conn_st_ctx_non_fp 741{ 742 __le16 conn_id /* Driver connection ID. To be used by slowpaths to fill EQ placement params */; 743 __le16 stat_ram_addr /* Statistics ram adderss */; 744 __le16 num_pages_in_pbl /* Number of XferQ/RespQ pbl pages (both have same wqe size) */; 745 u8 ptu_log_page_size /* 0-4K, 1-8K, 2-16K, 3-32K... */; 746 u8 log_page_size; 747 __le16 unsolicited_cq_count /* Counts number of CQs done due to unsolicited packets on this connection */; 748 __le16 cmdq_count /* Counts number of CMDQs done on this connection */; 749 u8 bdq_resource_id /* BDQ Resource ID */; 750 u8 reserved0[3] /* Padding bytes for 2nd RegPair */; 751 struct regpair xferq_pbl_addr /* XferQ Pbl base address */; 752 struct regpair reserved1; 753 struct regpair reserved2[3]; 754}; 755 756/* 757 * The fcoe storm context of Mstorm 758 */ 759struct mstorm_fcoe_conn_st_ctx 760{ 761 struct fcoe_mstorm_fcoe_conn_st_ctx_fp fp /* Fast path part of the fcoe storm context of Mstorm */; 762 struct fcoe_mstorm_fcoe_conn_st_ctx_non_fp non_fp /* Non fast path part of the fcoe storm context of Mstorm */; 763}; 764 765/* 766 * fcoe connection context 767 */ 768struct e4_fcoe_conn_context 769{ 770 struct ystorm_fcoe_conn_st_ctx ystorm_st_context /* ystorm storm context */; 771 struct pstorm_fcoe_conn_st_ctx pstorm_st_context /* pstorm storm context */; 772 struct regpair pstorm_st_padding[2] /* padding */; 773 struct xstorm_fcoe_conn_st_ctx xstorm_st_context /* xstorm storm context */; 774 struct e4_xstorm_fcoe_conn_ag_ctx xstorm_ag_context /* xstorm aggregative context */; 775 struct regpair xstorm_ag_padding[6] /* padding */; 776 struct ustorm_fcoe_conn_st_ctx ustorm_st_context /* ustorm storm context */; 777 struct regpair ustorm_st_padding[2] /* padding */; 778 struct e4_tstorm_fcoe_conn_ag_ctx tstorm_ag_context /* tstorm aggregative context */; 779 struct regpair tstorm_ag_padding[2] /* padding */; 780 struct timers_context timer_context /* timer context */; 781 struct e4_ustorm_fcoe_conn_ag_ctx ustorm_ag_context /* ustorm aggregative context */; 782 struct tstorm_fcoe_conn_st_ctx tstorm_st_context /* tstorm storm context */; 783 struct e4_mstorm_fcoe_conn_ag_ctx mstorm_ag_context /* mstorm aggregative context */; 784 struct mstorm_fcoe_conn_st_ctx mstorm_st_context /* mstorm storm context */; 785}; 786 787struct e5_xstorm_fcoe_conn_ag_ctx 788{ 789 u8 reserved0 /* cdu_validation */; 790 u8 state_and_core_id /* state_and_core_id */; 791 u8 flags0; 792#define E5_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 793#define E5_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 794#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm1 */ 795#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED1_SHIFT 1 796#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED2_MASK 0x1 /* exist_in_qm2 */ 797#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED2_SHIFT 2 798#define E5_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 799#define E5_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 800#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */ 801#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED3_SHIFT 4 802#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED4_MASK 0x1 /* cf_array_active */ 803#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED4_SHIFT 5 804#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */ 805#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED5_SHIFT 6 806#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */ 807#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED6_SHIFT 7 808 u8 flags1; 809#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */ 810#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED7_SHIFT 0 811#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */ 812#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED8_SHIFT 1 813#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED9_MASK 0x1 /* bit10 */ 814#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED9_SHIFT 2 815#define E5_XSTORM_FCOE_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */ 816#define E5_XSTORM_FCOE_CONN_AG_CTX_BIT11_SHIFT 3 817#define E5_XSTORM_FCOE_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */ 818#define E5_XSTORM_FCOE_CONN_AG_CTX_BIT12_SHIFT 4 819#define E5_XSTORM_FCOE_CONN_AG_CTX_BIT13_MASK 0x1 /* bit13 */ 820#define E5_XSTORM_FCOE_CONN_AG_CTX_BIT13_SHIFT 5 821#define E5_XSTORM_FCOE_CONN_AG_CTX_BIT14_MASK 0x1 /* bit14 */ 822#define E5_XSTORM_FCOE_CONN_AG_CTX_BIT14_SHIFT 6 823#define E5_XSTORM_FCOE_CONN_AG_CTX_BIT15_MASK 0x1 /* bit15 */ 824#define E5_XSTORM_FCOE_CONN_AG_CTX_BIT15_SHIFT 7 825 u8 flags2; 826#define E5_XSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 827#define E5_XSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 0 828#define E5_XSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 829#define E5_XSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 2 830#define E5_XSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 831#define E5_XSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 4 832#define E5_XSTORM_FCOE_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 833#define E5_XSTORM_FCOE_CONN_AG_CTX_CF3_SHIFT 6 834 u8 flags3; 835#define E5_XSTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 836#define E5_XSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 0 837#define E5_XSTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 838#define E5_XSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 2 839#define E5_XSTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 840#define E5_XSTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 4 841#define E5_XSTORM_FCOE_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 842#define E5_XSTORM_FCOE_CONN_AG_CTX_CF7_SHIFT 6 843 u8 flags4; 844#define E5_XSTORM_FCOE_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 845#define E5_XSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT 0 846#define E5_XSTORM_FCOE_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 847#define E5_XSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT 2 848#define E5_XSTORM_FCOE_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 849#define E5_XSTORM_FCOE_CONN_AG_CTX_CF10_SHIFT 4 850#define E5_XSTORM_FCOE_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */ 851#define E5_XSTORM_FCOE_CONN_AG_CTX_CF11_SHIFT 6 852 u8 flags5; 853#define E5_XSTORM_FCOE_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */ 854#define E5_XSTORM_FCOE_CONN_AG_CTX_CF12_SHIFT 0 855#define E5_XSTORM_FCOE_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */ 856#define E5_XSTORM_FCOE_CONN_AG_CTX_CF13_SHIFT 2 857#define E5_XSTORM_FCOE_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */ 858#define E5_XSTORM_FCOE_CONN_AG_CTX_CF14_SHIFT 4 859#define E5_XSTORM_FCOE_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */ 860#define E5_XSTORM_FCOE_CONN_AG_CTX_CF15_SHIFT 6 861 u8 flags6; 862#define E5_XSTORM_FCOE_CONN_AG_CTX_CF16_MASK 0x3 /* cf16 */ 863#define E5_XSTORM_FCOE_CONN_AG_CTX_CF16_SHIFT 0 864#define E5_XSTORM_FCOE_CONN_AG_CTX_CF17_MASK 0x3 /* cf_array_cf */ 865#define E5_XSTORM_FCOE_CONN_AG_CTX_CF17_SHIFT 2 866#define E5_XSTORM_FCOE_CONN_AG_CTX_CF18_MASK 0x3 /* cf18 */ 867#define E5_XSTORM_FCOE_CONN_AG_CTX_CF18_SHIFT 4 868#define E5_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_MASK 0x3 /* cf19 */ 869#define E5_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_SHIFT 6 870 u8 flags7; 871#define E5_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf20 */ 872#define E5_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 873#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED10_MASK 0x3 /* cf21 */ 874#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED10_SHIFT 2 875#define E5_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */ 876#define E5_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_SHIFT 4 877#define E5_XSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 878#define E5_XSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 6 879#define E5_XSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 880#define E5_XSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 7 881 u8 flags8; 882#define E5_XSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 883#define E5_XSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 0 884#define E5_XSTORM_FCOE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 885#define E5_XSTORM_FCOE_CONN_AG_CTX_CF3EN_SHIFT 1 886#define E5_XSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 887#define E5_XSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 2 888#define E5_XSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 889#define E5_XSTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 3 890#define E5_XSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 891#define E5_XSTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 4 892#define E5_XSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 893#define E5_XSTORM_FCOE_CONN_AG_CTX_CF7EN_SHIFT 5 894#define E5_XSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 895#define E5_XSTORM_FCOE_CONN_AG_CTX_CF8EN_SHIFT 6 896#define E5_XSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 897#define E5_XSTORM_FCOE_CONN_AG_CTX_CF9EN_SHIFT 7 898 u8 flags9; 899#define E5_XSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 900#define E5_XSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT 0 901#define E5_XSTORM_FCOE_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */ 902#define E5_XSTORM_FCOE_CONN_AG_CTX_CF11EN_SHIFT 1 903#define E5_XSTORM_FCOE_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */ 904#define E5_XSTORM_FCOE_CONN_AG_CTX_CF12EN_SHIFT 2 905#define E5_XSTORM_FCOE_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */ 906#define E5_XSTORM_FCOE_CONN_AG_CTX_CF13EN_SHIFT 3 907#define E5_XSTORM_FCOE_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */ 908#define E5_XSTORM_FCOE_CONN_AG_CTX_CF14EN_SHIFT 4 909#define E5_XSTORM_FCOE_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */ 910#define E5_XSTORM_FCOE_CONN_AG_CTX_CF15EN_SHIFT 5 911#define E5_XSTORM_FCOE_CONN_AG_CTX_CF16EN_MASK 0x1 /* cf16en */ 912#define E5_XSTORM_FCOE_CONN_AG_CTX_CF16EN_SHIFT 6 913#define E5_XSTORM_FCOE_CONN_AG_CTX_CF17EN_MASK 0x1 /* cf_array_cf_en */ 914#define E5_XSTORM_FCOE_CONN_AG_CTX_CF17EN_SHIFT 7 915 u8 flags10; 916#define E5_XSTORM_FCOE_CONN_AG_CTX_CF18EN_MASK 0x1 /* cf18en */ 917#define E5_XSTORM_FCOE_CONN_AG_CTX_CF18EN_SHIFT 0 918#define E5_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 /* cf19en */ 919#define E5_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_SHIFT 1 920#define E5_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 /* cf20en */ 921#define E5_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 922#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED11_MASK 0x1 /* cf21en */ 923#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED11_SHIFT 3 924#define E5_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 925#define E5_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 926#define E5_XSTORM_FCOE_CONN_AG_CTX_CF23EN_MASK 0x1 /* cf23en */ 927#define E5_XSTORM_FCOE_CONN_AG_CTX_CF23EN_SHIFT 5 928#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED12_MASK 0x1 /* rule0en */ 929#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED12_SHIFT 6 930#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED13_MASK 0x1 /* rule1en */ 931#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED13_SHIFT 7 932 u8 flags11; 933#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED14_MASK 0x1 /* rule2en */ 934#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED14_SHIFT 0 935#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED15_MASK 0x1 /* rule3en */ 936#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED15_SHIFT 1 937#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED16_MASK 0x1 /* rule4en */ 938#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED16_SHIFT 2 939#define E5_XSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 940#define E5_XSTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 3 941#define E5_XSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 942#define E5_XSTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 4 943#define E5_XSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 944#define E5_XSTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 5 945#define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */ 946#define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 947#define E5_XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_MASK 0x1 /* rule9en */ 948#define E5_XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_SHIFT 7 949 u8 flags12; 950#define E5_XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_MASK 0x1 /* rule10en */ 951#define E5_XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_SHIFT 0 952#define E5_XSTORM_FCOE_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */ 953#define E5_XSTORM_FCOE_CONN_AG_CTX_RULE11EN_SHIFT 1 954#define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */ 955#define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 956#define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */ 957#define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 958#define E5_XSTORM_FCOE_CONN_AG_CTX_RULE14EN_MASK 0x1 /* rule14en */ 959#define E5_XSTORM_FCOE_CONN_AG_CTX_RULE14EN_SHIFT 4 960#define E5_XSTORM_FCOE_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */ 961#define E5_XSTORM_FCOE_CONN_AG_CTX_RULE15EN_SHIFT 5 962#define E5_XSTORM_FCOE_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */ 963#define E5_XSTORM_FCOE_CONN_AG_CTX_RULE16EN_SHIFT 6 964#define E5_XSTORM_FCOE_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */ 965#define E5_XSTORM_FCOE_CONN_AG_CTX_RULE17EN_SHIFT 7 966 u8 flags13; 967#define E5_XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_MASK 0x1 /* rule18en */ 968#define E5_XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_SHIFT 0 969#define E5_XSTORM_FCOE_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */ 970#define E5_XSTORM_FCOE_CONN_AG_CTX_RULE19EN_SHIFT 1 971#define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */ 972#define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 973#define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */ 974#define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 975#define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */ 976#define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 977#define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */ 978#define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 979#define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */ 980#define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 981#define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */ 982#define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 983 u8 flags14; 984#define E5_XSTORM_FCOE_CONN_AG_CTX_BIT16_MASK 0x1 /* bit16 */ 985#define E5_XSTORM_FCOE_CONN_AG_CTX_BIT16_SHIFT 0 986#define E5_XSTORM_FCOE_CONN_AG_CTX_BIT17_MASK 0x1 /* bit17 */ 987#define E5_XSTORM_FCOE_CONN_AG_CTX_BIT17_SHIFT 1 988#define E5_XSTORM_FCOE_CONN_AG_CTX_BIT18_MASK 0x1 /* bit18 */ 989#define E5_XSTORM_FCOE_CONN_AG_CTX_BIT18_SHIFT 2 990#define E5_XSTORM_FCOE_CONN_AG_CTX_BIT19_MASK 0x1 /* bit19 */ 991#define E5_XSTORM_FCOE_CONN_AG_CTX_BIT19_SHIFT 3 992#define E5_XSTORM_FCOE_CONN_AG_CTX_BIT20_MASK 0x1 /* bit20 */ 993#define E5_XSTORM_FCOE_CONN_AG_CTX_BIT20_SHIFT 4 994#define E5_XSTORM_FCOE_CONN_AG_CTX_BIT21_MASK 0x1 /* bit21 */ 995#define E5_XSTORM_FCOE_CONN_AG_CTX_BIT21_SHIFT 5 996#define E5_XSTORM_FCOE_CONN_AG_CTX_CF23_MASK 0x3 /* cf23 */ 997#define E5_XSTORM_FCOE_CONN_AG_CTX_CF23_SHIFT 6 998 u8 byte2 /* byte2 */; 999 __le16 physical_q0 /* physical_q0 */; 1000 __le16 word1 /* physical_q1 */; 1001 __le16 word2 /* physical_q2 */; 1002 __le16 sq_cons /* word3 */; 1003 __le16 sq_prod /* word4 */; 1004 __le16 xferq_prod /* word5 */; 1005 __le16 xferq_cons /* conn_dpi */; 1006 u8 byte3 /* byte3 */; 1007 u8 byte4 /* byte4 */; 1008 u8 byte5 /* byte5 */; 1009 u8 byte6 /* byte6 */; 1010 __le32 remain_io /* reg0 */; 1011 __le32 reg1 /* reg1 */; 1012 __le32 reg2 /* reg2 */; 1013 __le32 reg3 /* reg3 */; 1014 __le32 reg4 /* reg4 */; 1015 __le32 reg5 /* cf_array0 */; 1016 __le32 reg6 /* cf_array1 */; 1017 u8 flags15; 1018#define E5_XSTORM_FCOE_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit22 */ 1019#define E5_XSTORM_FCOE_CONN_AG_CTX_E4_RESERVED1_SHIFT 0 1020#define E5_XSTORM_FCOE_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit23 */ 1021#define E5_XSTORM_FCOE_CONN_AG_CTX_E4_RESERVED2_SHIFT 1 1022#define E5_XSTORM_FCOE_CONN_AG_CTX_E4_RESERVED3_MASK 0x1 /* bit24 */ 1023#define E5_XSTORM_FCOE_CONN_AG_CTX_E4_RESERVED3_SHIFT 2 1024#define E5_XSTORM_FCOE_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf24 */ 1025#define E5_XSTORM_FCOE_CONN_AG_CTX_E4_RESERVED4_SHIFT 3 1026#define E5_XSTORM_FCOE_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf24en */ 1027#define E5_XSTORM_FCOE_CONN_AG_CTX_E4_RESERVED5_SHIFT 5 1028#define E5_XSTORM_FCOE_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule26en */ 1029#define E5_XSTORM_FCOE_CONN_AG_CTX_E4_RESERVED6_SHIFT 6 1030#define E5_XSTORM_FCOE_CONN_AG_CTX_E4_RESERVED7_MASK 0x1 /* rule27en */ 1031#define E5_XSTORM_FCOE_CONN_AG_CTX_E4_RESERVED7_SHIFT 7 1032 u8 byte7 /* byte7 */; 1033 __le16 respq_prod /* word7 */; 1034 __le16 respq_cons /* word8 */; 1035 __le16 word9 /* word9 */; 1036 __le16 word10 /* word10 */; 1037 __le16 word11 /* word11 */; 1038 __le32 reg7 /* reg7 */; 1039}; 1040 1041struct e5_tstorm_fcoe_conn_ag_ctx 1042{ 1043 u8 reserved0 /* cdu_validation */; 1044 u8 state_and_core_id /* state_and_core_id */; 1045 u8 flags0; 1046#define E5_TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1047#define E5_TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 1048#define E5_TSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1049#define E5_TSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1 1050#define E5_TSTORM_FCOE_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 1051#define E5_TSTORM_FCOE_CONN_AG_CTX_BIT2_SHIFT 2 1052#define E5_TSTORM_FCOE_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 1053#define E5_TSTORM_FCOE_CONN_AG_CTX_BIT3_SHIFT 3 1054#define E5_TSTORM_FCOE_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 1055#define E5_TSTORM_FCOE_CONN_AG_CTX_BIT4_SHIFT 4 1056#define E5_TSTORM_FCOE_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */ 1057#define E5_TSTORM_FCOE_CONN_AG_CTX_BIT5_SHIFT 5 1058#define E5_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_MASK 0x3 /* timer0cf */ 1059#define E5_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_SHIFT 6 1060 u8 flags1; 1061#define E5_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* timer1cf */ 1062#define E5_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 0 1063#define E5_TSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 1064#define E5_TSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 2 1065#define E5_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3 /* timer_stop_all */ 1066#define E5_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4 1067#define E5_TSTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 1068#define E5_TSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 6 1069 u8 flags2; 1070#define E5_TSTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 1071#define E5_TSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 0 1072#define E5_TSTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 1073#define E5_TSTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 2 1074#define E5_TSTORM_FCOE_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 1075#define E5_TSTORM_FCOE_CONN_AG_CTX_CF7_SHIFT 4 1076#define E5_TSTORM_FCOE_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 1077#define E5_TSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT 6 1078 u8 flags3; 1079#define E5_TSTORM_FCOE_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 1080#define E5_TSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT 0 1081#define E5_TSTORM_FCOE_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 1082#define E5_TSTORM_FCOE_CONN_AG_CTX_CF10_SHIFT 2 1083#define E5_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_MASK 0x1 /* cf0en */ 1084#define E5_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_SHIFT 4 1085#define E5_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf1en */ 1086#define E5_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5 1087#define E5_TSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1088#define E5_TSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 6 1089#define E5_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1 /* cf3en */ 1090#define E5_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7 1091 u8 flags4; 1092#define E5_TSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 1093#define E5_TSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 0 1094#define E5_TSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 1095#define E5_TSTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 1 1096#define E5_TSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 1097#define E5_TSTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 2 1098#define E5_TSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 1099#define E5_TSTORM_FCOE_CONN_AG_CTX_CF7EN_SHIFT 3 1100#define E5_TSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 1101#define E5_TSTORM_FCOE_CONN_AG_CTX_CF8EN_SHIFT 4 1102#define E5_TSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 1103#define E5_TSTORM_FCOE_CONN_AG_CTX_CF9EN_SHIFT 5 1104#define E5_TSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 1105#define E5_TSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT 6 1106#define E5_TSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1107#define E5_TSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 7 1108 u8 flags5; 1109#define E5_TSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1110#define E5_TSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 0 1111#define E5_TSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1112#define E5_TSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 1 1113#define E5_TSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1114#define E5_TSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 2 1115#define E5_TSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1116#define E5_TSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 3 1117#define E5_TSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1118#define E5_TSTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 4 1119#define E5_TSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 1120#define E5_TSTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 5 1121#define E5_TSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 1122#define E5_TSTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 6 1123#define E5_TSTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 1124#define E5_TSTORM_FCOE_CONN_AG_CTX_RULE8EN_SHIFT 7 1125 u8 flags6; 1126#define E5_TSTORM_FCOE_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit6 */ 1127#define E5_TSTORM_FCOE_CONN_AG_CTX_E4_RESERVED1_SHIFT 0 1128#define E5_TSTORM_FCOE_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit7 */ 1129#define E5_TSTORM_FCOE_CONN_AG_CTX_E4_RESERVED2_SHIFT 1 1130#define E5_TSTORM_FCOE_CONN_AG_CTX_E4_RESERVED3_MASK 0x1 /* bit8 */ 1131#define E5_TSTORM_FCOE_CONN_AG_CTX_E4_RESERVED3_SHIFT 2 1132#define E5_TSTORM_FCOE_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf11 */ 1133#define E5_TSTORM_FCOE_CONN_AG_CTX_E4_RESERVED4_SHIFT 3 1134#define E5_TSTORM_FCOE_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf11en */ 1135#define E5_TSTORM_FCOE_CONN_AG_CTX_E4_RESERVED5_SHIFT 5 1136#define E5_TSTORM_FCOE_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule9en */ 1137#define E5_TSTORM_FCOE_CONN_AG_CTX_E4_RESERVED6_SHIFT 6 1138#define E5_TSTORM_FCOE_CONN_AG_CTX_E4_RESERVED7_MASK 0x1 /* rule10en */ 1139#define E5_TSTORM_FCOE_CONN_AG_CTX_E4_RESERVED7_SHIFT 7 1140 u8 byte2 /* byte2 */; 1141 __le16 word0 /* word0 */; 1142 __le32 reg0 /* reg0 */; 1143}; 1144 1145struct e5_ustorm_fcoe_conn_ag_ctx 1146{ 1147 u8 byte0 /* cdu_validation */; 1148 u8 byte1 /* state_and_core_id */; 1149 u8 flags0; 1150#define E5_USTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1151#define E5_USTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0 1152#define E5_USTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1153#define E5_USTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1 1154#define E5_USTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 1155#define E5_USTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2 1156#define E5_USTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 1157#define E5_USTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4 1158#define E5_USTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 1159#define E5_USTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6 1160 u8 flags1; 1161#define E5_USTORM_FCOE_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 1162#define E5_USTORM_FCOE_CONN_AG_CTX_CF3_SHIFT 0 1163#define E5_USTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 1164#define E5_USTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 2 1165#define E5_USTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 1166#define E5_USTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 4 1167#define E5_USTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 1168#define E5_USTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 6 1169 u8 flags2; 1170#define E5_USTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1171#define E5_USTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0 1172#define E5_USTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1173#define E5_USTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1 1174#define E5_USTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1175#define E5_USTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2 1176#define E5_USTORM_FCOE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 1177#define E5_USTORM_FCOE_CONN_AG_CTX_CF3EN_SHIFT 3 1178#define E5_USTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 1179#define E5_USTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 4 1180#define E5_USTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 1181#define E5_USTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 5 1182#define E5_USTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 1183#define E5_USTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 6 1184#define E5_USTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1185#define E5_USTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 7 1186 u8 flags3; 1187#define E5_USTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1188#define E5_USTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 0 1189#define E5_USTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1190#define E5_USTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 1 1191#define E5_USTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1192#define E5_USTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 2 1193#define E5_USTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1194#define E5_USTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 3 1195#define E5_USTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1196#define E5_USTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 4 1197#define E5_USTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 1198#define E5_USTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 5 1199#define E5_USTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 1200#define E5_USTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 6 1201#define E5_USTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 1202#define E5_USTORM_FCOE_CONN_AG_CTX_RULE8EN_SHIFT 7 1203 u8 flags4; 1204#define E5_USTORM_FCOE_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit2 */ 1205#define E5_USTORM_FCOE_CONN_AG_CTX_E4_RESERVED1_SHIFT 0 1206#define E5_USTORM_FCOE_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit3 */ 1207#define E5_USTORM_FCOE_CONN_AG_CTX_E4_RESERVED2_SHIFT 1 1208#define E5_USTORM_FCOE_CONN_AG_CTX_E4_RESERVED3_MASK 0x3 /* cf7 */ 1209#define E5_USTORM_FCOE_CONN_AG_CTX_E4_RESERVED3_SHIFT 2 1210#define E5_USTORM_FCOE_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf8 */ 1211#define E5_USTORM_FCOE_CONN_AG_CTX_E4_RESERVED4_SHIFT 4 1212#define E5_USTORM_FCOE_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf7en */ 1213#define E5_USTORM_FCOE_CONN_AG_CTX_E4_RESERVED5_SHIFT 6 1214#define E5_USTORM_FCOE_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* cf8en */ 1215#define E5_USTORM_FCOE_CONN_AG_CTX_E4_RESERVED6_SHIFT 7 1216 u8 byte2 /* byte2 */; 1217 __le16 word0 /* conn_dpi */; 1218 __le16 word1 /* word1 */; 1219 __le32 reg0 /* reg0 */; 1220 __le32 reg1 /* reg1 */; 1221 __le32 reg2 /* reg2 */; 1222 __le32 reg3 /* reg3 */; 1223 __le16 word2 /* word2 */; 1224 __le16 word3 /* word3 */; 1225}; 1226 1227struct e5_mstorm_fcoe_conn_ag_ctx 1228{ 1229 u8 byte0 /* cdu_validation */; 1230 u8 byte1 /* state_and_core_id */; 1231 u8 flags0; 1232#define E5_MSTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1233#define E5_MSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0 1234#define E5_MSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1235#define E5_MSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1 1236#define E5_MSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 1237#define E5_MSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2 1238#define E5_MSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 1239#define E5_MSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4 1240#define E5_MSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 1241#define E5_MSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6 1242 u8 flags1; 1243#define E5_MSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1244#define E5_MSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0 1245#define E5_MSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1246#define E5_MSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1 1247#define E5_MSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1248#define E5_MSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2 1249#define E5_MSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1250#define E5_MSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 3 1251#define E5_MSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1252#define E5_MSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 4 1253#define E5_MSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1254#define E5_MSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 5 1255#define E5_MSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1256#define E5_MSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 6 1257#define E5_MSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1258#define E5_MSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 7 1259 __le16 word0 /* word0 */; 1260 __le16 word1 /* word1 */; 1261 __le32 reg0 /* reg0 */; 1262 __le32 reg1 /* reg1 */; 1263}; 1264 1265/* 1266 * fcoe connection context 1267 */ 1268struct e5_fcoe_conn_context 1269{ 1270 struct ystorm_fcoe_conn_st_ctx ystorm_st_context /* ystorm storm context */; 1271 struct pstorm_fcoe_conn_st_ctx pstorm_st_context /* pstorm storm context */; 1272 struct regpair pstorm_st_padding[2] /* padding */; 1273 struct xstorm_fcoe_conn_st_ctx xstorm_st_context /* xstorm storm context */; 1274 struct e5_xstorm_fcoe_conn_ag_ctx xstorm_ag_context /* xstorm aggregative context */; 1275 struct ustorm_fcoe_conn_st_ctx ustorm_st_context /* ustorm storm context */; 1276 struct regpair ustorm_st_padding[2] /* padding */; 1277 struct e5_tstorm_fcoe_conn_ag_ctx tstorm_ag_context /* tstorm aggregative context */; 1278 struct regpair tstorm_ag_padding[2] /* padding */; 1279 struct timers_context timer_context /* timer context */; 1280 struct e5_ustorm_fcoe_conn_ag_ctx ustorm_ag_context /* ustorm aggregative context */; 1281 struct tstorm_fcoe_conn_st_ctx tstorm_st_context /* tstorm storm context */; 1282 struct e5_mstorm_fcoe_conn_ag_ctx mstorm_ag_context /* mstorm aggregative context */; 1283 struct mstorm_fcoe_conn_st_ctx mstorm_st_context /* mstorm storm context */; 1284}; 1285 1286/* 1287 * FCoE connection offload params passed by driver to FW in FCoE offload ramrod 1288 */ 1289struct fcoe_conn_offload_ramrod_params 1290{ 1291 struct fcoe_conn_offload_ramrod_data offload_ramrod_data; 1292}; 1293 1294/* 1295 * FCoE connection terminate params passed by driver to FW in FCoE terminate conn ramrod 1296 */ 1297struct fcoe_conn_terminate_ramrod_params 1298{ 1299 struct fcoe_conn_terminate_ramrod_data terminate_ramrod_data; 1300}; 1301 1302/* 1303 * FCoE event type 1304 */ 1305enum fcoe_event_type 1306{ 1307 FCOE_EVENT_INIT_FUNC /* Slowpath completion on INIT_FUNC ramrod */, 1308 FCOE_EVENT_DESTROY_FUNC /* Slowpath completion on DESTROY_FUNC ramrod */, 1309 FCOE_EVENT_STAT_FUNC /* Slowpath completion on STAT_FUNC ramrod */, 1310 FCOE_EVENT_OFFLOAD_CONN /* Slowpath completion on OFFLOAD_CONN ramrod */, 1311 FCOE_EVENT_TERMINATE_CONN /* Slowpath completion on TERMINATE_CONN ramrod */, 1312 FCOE_EVENT_ERROR /* Error event */, 1313 MAX_FCOE_EVENT_TYPE 1314}; 1315 1316/* 1317 * FCoE init params passed by driver to FW in FCoE init ramrod 1318 */ 1319struct fcoe_init_ramrod_params 1320{ 1321 struct fcoe_init_func_ramrod_data init_ramrod_data; 1322}; 1323 1324/* 1325 * FCoE ramrod Command IDs 1326 */ 1327enum fcoe_ramrod_cmd_id 1328{ 1329 FCOE_RAMROD_CMD_ID_INIT_FUNC /* FCoE function init ramrod */, 1330 FCOE_RAMROD_CMD_ID_DESTROY_FUNC /* FCoE function destroy ramrod */, 1331 FCOE_RAMROD_CMD_ID_STAT_FUNC /* FCoE statistics ramrod */, 1332 FCOE_RAMROD_CMD_ID_OFFLOAD_CONN /* FCoE connection offload ramrod */, 1333 FCOE_RAMROD_CMD_ID_TERMINATE_CONN /* FCoE connection offload ramrod. Command ID known only to FW and VBD */, 1334 MAX_FCOE_RAMROD_CMD_ID 1335}; 1336 1337/* 1338 * FCoE statistics params buffer passed by driver to FW in FCoE statistics ramrod 1339 */ 1340struct fcoe_stat_ramrod_params 1341{ 1342 struct fcoe_stat_ramrod_data stat_ramrod_data; 1343}; 1344 1345struct e4_ystorm_fcoe_conn_ag_ctx 1346{ 1347 u8 byte0 /* cdu_validation */; 1348 u8 byte1 /* state */; 1349 u8 flags0; 1350#define E4_YSTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1351#define E4_YSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0 1352#define E4_YSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1353#define E4_YSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1 1354#define E4_YSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 1355#define E4_YSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2 1356#define E4_YSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 1357#define E4_YSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4 1358#define E4_YSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 1359#define E4_YSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6 1360 u8 flags1; 1361#define E4_YSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1362#define E4_YSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0 1363#define E4_YSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1364#define E4_YSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1 1365#define E4_YSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1366#define E4_YSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2 1367#define E4_YSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1368#define E4_YSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 3 1369#define E4_YSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1370#define E4_YSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 4 1371#define E4_YSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1372#define E4_YSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 5 1373#define E4_YSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1374#define E4_YSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 6 1375#define E4_YSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1376#define E4_YSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 7 1377 u8 byte2 /* byte2 */; 1378 u8 byte3 /* byte3 */; 1379 __le16 word0 /* word0 */; 1380 __le32 reg0 /* reg0 */; 1381 __le32 reg1 /* reg1 */; 1382 __le16 word1 /* word1 */; 1383 __le16 word2 /* word2 */; 1384 __le16 word3 /* word3 */; 1385 __le16 word4 /* word4 */; 1386 __le32 reg2 /* reg2 */; 1387 __le32 reg3 /* reg3 */; 1388}; 1389 1390struct e5_ystorm_fcoe_conn_ag_ctx 1391{ 1392 u8 byte0 /* cdu_validation */; 1393 u8 byte1 /* state_and_core_id */; 1394 u8 flags0; 1395#define E5_YSTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1396#define E5_YSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0 1397#define E5_YSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1398#define E5_YSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1 1399#define E5_YSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 1400#define E5_YSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2 1401#define E5_YSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 1402#define E5_YSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4 1403#define E5_YSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 1404#define E5_YSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6 1405 u8 flags1; 1406#define E5_YSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1407#define E5_YSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0 1408#define E5_YSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1409#define E5_YSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1 1410#define E5_YSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1411#define E5_YSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2 1412#define E5_YSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1413#define E5_YSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 3 1414#define E5_YSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1415#define E5_YSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 4 1416#define E5_YSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1417#define E5_YSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 5 1418#define E5_YSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1419#define E5_YSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 6 1420#define E5_YSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1421#define E5_YSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 7 1422 u8 byte2 /* byte2 */; 1423 u8 byte3 /* byte3 */; 1424 __le16 word0 /* word0 */; 1425 __le32 reg0 /* reg0 */; 1426 __le32 reg1 /* reg1 */; 1427 __le16 word1 /* word1 */; 1428 __le16 word2 /* word2 */; 1429 __le16 word3 /* word3 */; 1430 __le16 word4 /* word4 */; 1431 __le32 reg2 /* reg2 */; 1432 __le32 reg3 /* reg3 */; 1433}; 1434 1435#endif /* __ECORE_HSI_FCOE__ */ 1436