Lines Matching refs:x3
110 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
112 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
114 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
116 #define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3 /* timer_stop_all */
119 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */
121 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */
123 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
125 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */
128 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */
130 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */
132 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */
134 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */
137 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */
139 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */
141 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_MASK 0x3 /* cf14 */
143 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */
146 #define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_MASK 0x3 /* cf16 */
148 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF17_MASK 0x3 /* cf_array_cf */
150 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF18_MASK 0x3 /* cf18 */
152 #define E4_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_MASK 0x3 /* cf19 */
155 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf20 */
157 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_MASK 0x3 /* cf21 */
159 #define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */
280 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF23_MASK 0x3 /* cf23 */
346 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
349 #define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_MASK 0x3 /* timer1cf */
351 #define E4_TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_MASK 0x3 /* timer2cf */
353 #define E4_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3 /* timer_stop_all */
355 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */
358 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */
360 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
362 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */
364 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */
367 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPLETE_MASK 0x3 /* cf9 */
369 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_MASK 0x3 /* cf10 */
518 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
520 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
522 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
524 #define E5_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3 /* timer_stop_all */
527 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */
529 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */
531 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
533 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */
536 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */
538 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */
540 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */
542 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */
545 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */
547 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */
549 #define E5_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_MASK 0x3 /* cf14 */
551 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */
554 #define E5_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_MASK 0x3 /* cf16 */
556 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF17_MASK 0x3 /* cf_array_cf */
558 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF18_MASK 0x3 /* cf18 */
560 #define E5_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_MASK 0x3 /* cf19 */
563 #define E5_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf20 */
565 #define E5_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_MASK 0x3 /* cf21 */
567 #define E5_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */
680 #define E5_XSTORM_IWARP_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3 /* bit18 */
686 #define E5_XSTORM_IWARP_CONN_AG_CTX_CF23_MASK 0x3 /* cf23 */
714 #define E5_XSTORM_IWARP_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf24 */
766 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
769 #define E5_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_MASK 0x3 /* timer1cf */
771 #define E5_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_MASK 0x3 /* timer2cf */
773 #define E5_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3 /* timer_stop_all */
775 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */
778 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */
780 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
782 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */
784 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */
787 #define E5_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf9 */
789 #define E5_TSTORM_IWARP_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */
840 #define E5_TSTORM_IWARP_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf11 */
1240 #define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_MASK 0x3 /* cf0 */
1242 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */
1244 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */
1278 #define E4_USTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
1280 #define E4_USTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
1282 #define E4_USTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
1285 #define E4_USTORM_IWARP_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */
1287 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3 /* cf4 */
1289 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3 /* cf5 */
1291 #define E4_USTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
1348 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */
1350 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */
1352 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */
1393 #define E5_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_MASK 0x3 /* cf0 */
1395 #define E5_MSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */
1397 #define E5_MSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */
1431 #define E5_USTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */
1433 #define E5_USTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */
1435 #define E5_USTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */
1438 #define E5_USTORM_IWARP_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */
1440 #define E5_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3 /* cf4 */
1442 #define E5_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3 /* cf5 */
1444 #define E5_USTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */
1485 #define E5_USTORM_IWARP_CONN_AG_CTX_E4_RESERVED3_MASK 0x3 /* cf7 */
1487 #define E5_USTORM_IWARP_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf8 */
1513 #define E5_YSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */
1515 #define E5_YSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */
1517 #define E5_YSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */