Searched refs:v8i1 (Results 1 - 12 of 12) sorted by relevance

/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp1394 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 }, member in class:MVT
1395 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, member in class:MVT
1407 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 }, member in class:MVT
1408 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, member in class:MVT
1421 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 }, // widen to zmm member in class:MVT
1422 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 2 }, // widen to zmm member in class:MVT
1454 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 3 }, // sext+vpslld+vptestmd
1458 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 3 }, // sext+vpsllq+vptestmq
1462 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i32, 2 }, // zmm vpslld+vptestmd
1466 { ISD::TRUNCATE, MVT::v8i1, MV
1569 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, 1 }, member in class:MVT
1570 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, member in class:MVT
1580 { ISD::ZERO_EXTEND, MVT::v8i8, MVT::v8i1, 2 }, member in class:MVT
1581 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, member in class:MVT
1591 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i8, 2 }, // vpsllw+vptestmb member in class:MVT
1592 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 2 }, // vpsllw+vptestmw member in class:MVT
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H A DX86ISelLowering.cpp1383 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1390 setOperationPromotedToType(ISD::FP_TO_SINT, MVT::v8i1, MVT::v8i32);
1391 setOperationPromotedToType(ISD::FP_TO_UINT, MVT::v8i1, MVT::v8i32);
1394 setOperationPromotedToType(ISD::STRICT_FP_TO_SINT, MVT::v8i1, MVT::v8i32);
1395 setOperationPromotedToType(ISD::STRICT_FP_TO_UINT, MVT::v8i1, MVT::v8i32);
1408 setOperationAction(ISD::LOAD, MVT::v8i1, Custom);
1413 setOperationAction(ISD::STORE, MVT::v8i1, Custom);
1416 // Extends of v16i1/v8i1/v4i1/v2i1 to 128-bit vectors.
1423 for (auto VT : { MVT::v1i1, MVT::v2i1, MVT::v4i1, MVT::v8i1, MVT::v16i1 }) {
1434 for (auto VT : { MVT::v2i1, MVT::v4i1, MVT::v8i1, MV
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H A DX86ISelDAGToDAG.cpp4239 case MVT::v8i1: return X86::VK8RegClassID;
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/Support/
H A DMachineValueType.h64 v8i1 = 18, // 8 x i1
460 case v8i1:
659 case v8i1:
781 case v8i1: return TypeSize::Fixed(8);
1021 if (NumElements == 8) return MVT::v8i1;
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp661 { ISD::SELECT, MVT::v8i1, MVT::v8i32, 8 },
664 { ISD::SELECT, MVT::v8i1, MVT::v8i64, 8 * AmortizationCost },
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DValueTypes.cpp203 case MVT::v8i1:
/freebsd-13-stable/contrib/llvm-project/llvm/utils/TableGen/
H A DCodeGenTarget.cpp84 case MVT::v8i1: return "MVT::v8i1";
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1449 addRegisterClass(MVT::v8i1, &Hexagon::PredRegsRegClass); // hgfedcba
1665 for (MVT NativeVT : {MVT::v8i1, MVT::v4i1, MVT::v2i1, MVT::v4i8,
1703 // Custom-lower bitcasts from i8 to v8i1.
2275 // Handle conversion from i8 to v8i1.
2277 if (ResTy == MVT::v8i1) {
2497 // Each bool vector (v2i1, v4i1, v8i1) always occupies 8 bits in
2677 if (VecTy == MVT::v8i1 || VecTy == MVT::v4i1 || VecTy == MVT::v2i1) {
2730 assert(VecTy == MVT::v2i1 || VecTy == MVT::v4i1 || VecTy == MVT::v8i1);
3119 // Handle a bitcast from v8i1 to i8.
H A DHexagonISelDAGToDAG.cpp809 SDNode *Pu = CurDAG->getMachineNode(Hexagon::C2_tfrrp, dl, MVT::v8i1,
H A DHexagonISelLoweringHVX.cpp582 assert(PredTy == MVT::v2i1 || PredTy == MVT::v4i1 || PredTy == MVT::v8i1);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp595 { ISD::SELECT, MVT::v8i1, MVT::v8i64, 50 },
H A DARMISelLowering.cpp429 const MVT pTypes[] = {MVT::v16i1, MVT::v8i1, MVT::v4i1};
8074 case MVT::v8i1:
8100 // If the real predicate is an v8i1 or v4i1 (not v16i1) then we need to recast
8153 // which will generate a real predicate, i.e. v4i1, v8i1 or v16i1.
8566 // We now have Op1 + Op2 promoted to vectors of integers, where v8i1 gets
8573 // the promoted vector is v4i32. The result of concatentation gives a v8i1,
8594 // which will generate a real predicate, i.e. v4i1, v8i1 or v16i1.
8641 // We now have Op1 promoted to a vector of integers, where v8i1 gets
8656 // which will generate a real predicate, i.e. v4i1, v8i1 or v16i1.
9380 assert((MemVT == MVT::v4i1 || MemVT == MVT::v8i1 || MemV
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