Lines Matching refs:v8i1
1383 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1390 setOperationPromotedToType(ISD::FP_TO_SINT, MVT::v8i1, MVT::v8i32);
1391 setOperationPromotedToType(ISD::FP_TO_UINT, MVT::v8i1, MVT::v8i32);
1394 setOperationPromotedToType(ISD::STRICT_FP_TO_SINT, MVT::v8i1, MVT::v8i32);
1395 setOperationPromotedToType(ISD::STRICT_FP_TO_UINT, MVT::v8i1, MVT::v8i32);
1408 setOperationAction(ISD::LOAD, MVT::v8i1, Custom);
1413 setOperationAction(ISD::STORE, MVT::v8i1, Custom);
1416 // Extends of v16i1/v8i1/v4i1/v2i1 to 128-bit vectors.
1423 for (auto VT : { MVT::v1i1, MVT::v2i1, MVT::v4i1, MVT::v8i1, MVT::v16i1 }) {
1434 for (auto VT : { MVT::v2i1, MVT::v4i1, MVT::v8i1, MVT::v16i1 }) {
1449 for (auto VT : { MVT::v1i1, MVT::v2i1, MVT::v4i1, MVT::v8i1 })
2064 // v2i1/v4i1/v8i1/v16i1 all pass in xmm registers unless the calling
2572 if ((ValVT == MVT::v8i1 && (ValLoc == MVT::i8 || ValLoc == MVT::i32)) ||
2575 // bitcast: v8i1 -> i8 / v16i1 -> i16
2577 EVT TempValLoc = ValVT == MVT::v8i1 ? MVT::i8 : MVT::i16;
2937 /// to a mask value of the expected size (v8i1/v16i1/v32i1/v64i1)
2954 case MVT::v8i1:
3634 else if (RegVT == MVT::v8i1)
5248 if (!Subtarget.hasDQI() && BitcastVT == MVT::v8i1 && LoadVT == MVT::i8)
6025 WideOpVT = Subtarget.hasDQI() ? MVT::v8i1 : MVT::v16i1;
8706 if ((EltType == MVT::i64 && MaskVT == MVT::v8i1) || // for broadcastmb2q
8994 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
9052 MVT VecVT = VT.getSizeInBits() >= 8 ? VT : MVT::v8i1;
9071 MVT VecVT = VT.getSizeInBits() >= 8 ? VT : MVT::v8i1;
10567 ShiftVT = Subtarget.hasDQI() ? MVT::v8i1 : MVT::v16i1;
17608 WideVT = Subtarget.hasDQI() ? MVT::v8i1 : MVT::v16i1;
17711 WideVT = Subtarget.hasDQI() ? MVT::v8i1 : MVT::v16i1;
17745 case MVT::v8i1:
18138 /// Extract one bit from mask vector, like v16i1 or v8i1.
18156 // Extending v8i1/v16i1 to 512-bit get better performance on KNL
18173 WideVecVT = Subtarget.hasDQI() ? MVT::v8i1 : MVT::v16i1;
18331 /// Insert one bit to mask vector, like v16i1 or v8i1.
18567 WideVecVT = Subtarget.hasDQI() ? MVT::v8i1 : MVT::v16i1;
20263 SDValue Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v8i1, In,
20265 SDValue Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v8i1, In,
20508 Lo = DAG.getNode(ISD::TRUNCATE, DL, MVT::v8i1, Lo);
20509 Hi = DAG.getNode(ISD::TRUNCATE, DL, MVT::v8i1, Hi);
20711 TruncVT = MVT::v8i1;
22666 !(Subtarget.hasDQI() && VT == MVT::v8i1) &&
22681 if (Subtarget.hasDQI() && (VT == MVT::v8i1 || VT == MVT::v16i1))
23549 // Without AVX512DQ, we need to use a scalar type for v2i1/v4i1/v8i1 stores.
23633 // Without AVX512DQ, we need to use a scalar type for v2i1/v4i1/v8i1 loads.
24274 DAG.getBitcast(MVT::v8i1, Mask),
24709 SDValue Ins = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, MVT::v8i1,
24710 DAG.getConstant(0, dl, MVT::v8i1),
24755 SDValue Ins = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, MVT::v8i1,
24756 DAG.getConstant(0, dl, MVT::v8i1),
38068 // For example, t0 := (v8i16 sext(v8i1 x)) needs to be shuffled as:
38087 case MVT::v8i1:
38089 // For cases such as (i8 bitcast (v8i1 setcc v8i32 v1, v2)),
38381 N0 = DAG.getBitcast(MVT::v8i1, N0);
38404 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i1, Ops);
38413 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i1, Ops);
38429 // Look for (i8 (bitcast (v8i1 (extract_subvector (v16i1 X), 0)))) and
38434 if (VT == MVT::i8 && SrcVT == MVT::v8i1 && Subtarget.hasAVX512() &&
42474 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
44142 // Widen v2i1/v4i1 stores to v8i1.
44148 StoredVal = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i1, Ops);
44155 if ((VT == MVT::v8i1 || VT == MVT::v16i1 || VT == MVT::v32i1 ||