Searched refs:v64i8 (Results 1 - 10 of 10) sorted by relevance

/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp304 { ISD::SHL, MVT::v64i8, 2 }, // psllw + pand.
305 { ISD::SRL, MVT::v64i8, 2 }, // psrlw + pand.
306 { ISD::SRA, MVT::v64i8, 4 }, // psrlw, pand, pxor, psubb.
321 { ISD::SHL, MVT::v64i8, 4 }, // psllw + pand.
322 { ISD::SRL, MVT::v64i8, 4 }, // psrlw + pand.
323 { ISD::SRA, MVT::v64i8, 8 }, // psrlw, pand, pxor, psubb.
367 { ISD::SDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence
368 { ISD::SREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence
369 { ISD::UDIV, MVT::v64i8, 14 }, // 2*ext+2*pmulhw sequence
370 { ISD::UREM, MVT::v64i8, 1
1400 { ISD::SIGN_EXTEND, MVT::v64i8, MVT::v64i1, 1 }, member in class:MVT
1413 { ISD::ZERO_EXTEND, MVT::v64i8, MVT::v64i1, 2 }, member in class:MVT
1427 { ISD::TRUNCATE, MVT::v64i1, MVT::v64i8, 2 }, member in class:MVT
[all...]
H A DX86ISelLowering.cpp1464 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1547 setOperationAction(ISD::SIGN_EXTEND, MVT::v64i8, Custom);
1548 setOperationAction(ISD::ZERO_EXTEND, MVT::v64i8, Custom);
1549 setOperationAction(ISD::ANY_EXTEND, MVT::v64i8, Custom);
1574 setOperationAction(ISD::ADD, MVT::v64i8, HasBWI ? Legal : Custom);
1575 setOperationAction(ISD::SUB, MVT::v64i8, HasBWI ? Legal : Custom);
1580 setOperationAction(ISD::MUL, MVT::v64i8, Custom);
1586 setOperationAction(ISD::MULHS, MVT::v64i8, Custom);
1587 setOperationAction(ISD::MULHU, MVT::v64i8, Custom);
1589 setOperationAction(ISD::BITREVERSE, MVT::v64i8, Custo
[all...]
H A DX86ISelDAGToDAG.cpp851 // Emulate v32i16/v64i8 broadcast without BWI.
852 if (!Subtarget->hasBWI() && (VT == MVT::v32i16 || VT == MVT::v64i8)) {
875 // Emulate v32i16/v64i8 broadcast without BWI.
876 if (!Subtarget->hasBWI() && (VT == MVT::v32i16 || VT == MVT::v64i8)) {
4102 VPTESTM_CASE(v64i8, BZ##SUFFIX) \
H A DX86FastISel.cpp456 case MVT::v64i8:
628 case MVT::v64i8:
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/Support/
H A DMachineValueType.h79 v64i8 = 32, // 64 x i8
393 SimpleTy == MVT::v512i1 || SimpleTy == MVT::v64i8 ||
481 case v64i8:
620 case v64i8:
877 case v64i8:
1037 if (NumElements == 64) return MVT::v64i8;
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DValueTypes.cpp231 case MVT::v64i8:
/freebsd-13-stable/contrib/llvm-project/llvm/utils/TableGen/
H A DCodeGenTarget.cpp97 case MVT::v64i8: return "MVT::v64i8";
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp17 static const MVT LegalV64[] = { MVT::v64i8, MVT::v32i16, MVT::v16i32 };
26 addRegisterClass(MVT::v64i8, &Hexagon::HvxVRRegClass);
60 MVT ByteV = Use64b ? MVT::v64i8 : MVT::v128i8;
182 // v64i8 -> v64i1 (single)
210 for (MVT T: {MVT::v64i8, MVT::v64i16, MVT::v32i8, MVT::v32i16, MVT::v32i32})
H A DHexagonISelDAGToDAG.cpp108 case MVT::v64i8:
498 case MVT::v64i8:
H A DHexagonInstrInfo.cpp2687 case MVT::v64i8:

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