Searched refs:v64i1 (Results 1 - 9 of 9) sorted by relevance

/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/Support/
H A DMachineValueType.h67 v64i1 = 21, // 64 x i1
364 return (SimpleTy == MVT::v64i1 || SimpleTy == MVT::v8i8 ||
463 case v64i1:
619 case v64i1:
816 case v64i1:
1024 if (NumElements == 64) return MVT::v64i1;
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DValueTypes.cpp209 case MVT::v64i1:
/freebsd-13-stable/contrib/llvm-project/llvm/utils/TableGen/
H A DCodeGenTarget.cpp87 case MVT::v64i1: return "MVT::v64i1";
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAGHVX.cpp2206 SDVTList VTs = CurDAG->getVTList(MVT::v16i32, MVT::v64i1);
2220 SDVTList VTs = CurDAG->getVTList(MVT::v16i32, MVT::v64i1);
H A DHexagonISelLoweringHVX.cpp42 addRegisterClass(MVT::v64i1, &Hexagon::HvxQRRegClass);
51 addRegisterClass(MVT::v64i1, &Hexagon::HvxQRRegClass);
182 // v64i8 -> v64i1 (single)
183 // v64i16 -> v64i1 (pair)
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FrameLowering.cpp2425 VT = STI.hasBWI() ? MVT::v64i1 : MVT::v16i1;
2505 VT = STI.hasBWI() ? MVT::v64i1 : MVT::v16i1;
2585 VT = STI.hasBWI() ? MVT::v64i1 : MVT::v16i1;
H A DX86TargetTransformInfo.cpp1400 { ISD::SIGN_EXTEND, MVT::v64i8, MVT::v64i1, 1 }, member in class:MVT
1413 { ISD::ZERO_EXTEND, MVT::v64i8, MVT::v64i1, 2 }, member in class:MVT
1427 { ISD::TRUNCATE, MVT::v64i1, MVT::v64i8, 2 }, member in class:MVT
3219 { ISD::AND, MVT::v64i1, 13 },
3225 { ISD::OR, MVT::v64i1, 13 },
H A DX86ISelLowering.cpp1546 // Extends from v64i1 masks to 512-bit vectors.
1792 // This block control legalization of v32i1/v64i1 which are available with
1797 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1799 for (auto VT : { MVT::v32i1, MVT::v64i1 }) {
2050 if ((VT == MVT::v32i1 || VT == MVT::v64i1) && Subtarget.hasAVX512() &&
2080 // Split v64i1 vectors if we don't have v64i8 available.
2146 // Split v64i1 vectors if we don't have v64i8 available.
2147 if (VT == MVT::v64i1 && Subtarget.hasBWI() && !Subtarget.useAVX512Regs() &&
2585 (ValVT == MVT::v64i1 && ValLoc == MVT::i64)) {
2587 // bitcast: v32i1 -> i32 / v64i1
[all...]
H A DX86ISelDAGToDAG.cpp4242 case MVT::v64i1: return X86::VK64RegClassID;

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