Lines Matching refs:v64i1
1546 // Extends from v64i1 masks to 512-bit vectors.
1792 // This block control legalization of v32i1/v64i1 which are available with
1797 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1799 for (auto VT : { MVT::v32i1, MVT::v64i1 }) {
2050 if ((VT == MVT::v32i1 || VT == MVT::v64i1) && Subtarget.hasAVX512() &&
2080 // Split v64i1 vectors if we don't have v64i8 available.
2146 // Split v64i1 vectors if we don't have v64i8 available.
2147 if (VT == MVT::v64i1 && Subtarget.hasBWI() && !Subtarget.useAVX512Regs() &&
2585 (ValVT == MVT::v64i1 && ValLoc == MVT::i64)) {
2587 // bitcast: v32i1 -> i32 / v64i1 -> i64
2594 /// Breaks v64i1 value into two registers and adds the new node to the DAG
2716 assert(VA.getValVT() == MVT::v64i1 &&
2717 "Currently the only custom case is when we split v64i1 to 2 regs");
2894 assert(VA.getValVT() == MVT::v64i1 &&
2933 return DAG.getNode(ISD::CONCAT_VECTORS, Dl, MVT::v64i1, Lo, Hi);
2937 /// to a mask value of the expected size (v8i1/v16i1/v32i1/v64i1)
2947 if (ValVT == MVT::v64i1) {
3033 assert(VA.getValVT() == MVT::v64i1 &&
3034 "Currently the only custom case is when we split v64i1 to 2 regs");
3599 VA.getValVT() == MVT::v64i1 &&
3600 "Currently the only custom case is when we split v64i1 to 2 regs");
3602 // v64i1 values, in regcall calling convention, that are
3640 else if (RegVT == MVT::v64i1)
4066 assert(VA.getValVT() == MVT::v64i1 &&
4067 "Currently the only custom case is when we split v64i1 to 2 regs");
4068 // Split v64i1 value into two registers
6118 if (WideOpVT != MVT::v64i1 || Subtarget.is64Bit()) {
9041 if (VT == MVT::v64i1 && !Subtarget.is64Bit()) {
9046 return DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v64i1, Select, Select);
9062 if (VT == MVT::v64i1 && !Subtarget.is64Bit()) {
9067 DstVec = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v64i1, ImmL, ImmH);
17761 case MVT::v64i1:
22667 !(Subtarget.hasBWI() && (VT == MVT::v32i1 || VT == MVT::v64i1)))
22683 if (Subtarget.hasBWI() && (VT == MVT::v32i1 || VT == MVT::v64i1))
24207 assert(MaskVT == MVT::v64i1 && "Expected v64i1 mask!");
24219 return DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v64i1, Lo, Hi);
27079 SDValue CMP = DAG.getSetCC(dl, MVT::v64i1, Zeros, R, ISD::SETGT);
28272 // Legalize (v64i1 (bitcast i64 (X))) by splitting the i64, bitcasting each
28274 if (SrcVT == MVT::i64 && DstVT == MVT::v64i1) {
28284 return DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v64i1, Lo, Hi);
30187 // If this is a bitcast from a v64i1 k-register to a i64 on a 32-bit target
30189 if (SrcVT == MVT::v64i1 && DstVT == MVT::i64 && Subtarget.hasBWI()) {
38110 case MVT::v64i1:
40323 (DCI.isBeforeLegalize() || (VT != MVT::v64i1 || Subtarget.is64Bit()))) {
44156 VT == MVT::v64i1) && VT == StVT && TLI.isTypeLegal(VT) &&
44158 // If its a v64i1 store without 64-bit support, we need two stores.
44159 if (!DCI.isBeforeLegalize() && VT == MVT::v64i1 && !Subtarget.is64Bit()) {
46435 CmpVT = MVT::v64i1;
46493 EVT KRegVT = CmpVT == MVT::v64i1 ? MVT::i64 :