Searched refs:v32i1 (Results 1 - 7 of 7) sorted by relevance

/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/Support/
H A DMachineValueType.h66 v32i1 = 20, // 32 x i1
356 return (SimpleTy == MVT::v32i1 || SimpleTy == MVT::v4i8 ||
462 case v32i1:
628 case v32i1:
796 case v32i1:
1023 if (NumElements == 32) return MVT::v32i1;
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp1398 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, member in class:MVT
1399 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i1, 1 }, member in class:MVT
1411 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, member in class:MVT
1412 { ISD::ZERO_EXTEND, MVT::v32i16, MVT::v32i1, 2 }, member in class:MVT
1425 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i8, 2 }, // widen to zmm member in class:MVT
1426 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i16, 2 }, member in class:MVT
1573 { ISD::SIGN_EXTEND, MVT::v32i8, MVT::v32i1, 1 }, member in class:MVT
1584 { ISD::ZERO_EXTEND, MVT::v32i8, MVT::v32i1, 2 }, member in class:MVT
1595 { ISD::TRUNCATE, MVT::v32i1, MVT::v32i8, 2 }, // vpsllw+vptestmb member in class:MVT
3218 { ISD::AND, MVT::v32i1, 1
[all...]
H A DX86ISelLowering.cpp1212 setOperationAction(ISD::BITCAST, MVT::v32i1, Custom);
1792 // This block control legalization of v32i1/v64i1 which are available with
1796 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1799 for (auto VT : { MVT::v32i1, MVT::v64i1 }) {
1820 for (auto VT : { MVT::v16i1, MVT::v32i1 })
1823 // Extends from v32i1 masks to 256-bit vectors.
2050 if ((VT == MVT::v32i1 || VT == MVT::v64i1) && Subtarget.hasAVX512() &&
2076 // v32i1 passes in ymm unless we have BWI and the calling convention is
2150 IntermediateVT = MVT::v32i1;
2584 if ((ValVT == MVT::v32i1
[all...]
H A DX86ISelDAGToDAG.cpp4241 case MVT::v32i1: return X86::VK32RegClassID;
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DValueTypes.cpp207 case MVT::v32i1:
/freebsd-13-stable/contrib/llvm-project/llvm/utils/TableGen/
H A DCodeGenTarget.cpp86 case MVT::v32i1: return "MVT::v32i1";
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp41 addRegisterClass(MVT::v32i1, &Hexagon::HvxQRRegClass);
50 addRegisterClass(MVT::v32i1, &Hexagon::HvxQRRegClass);
68 // Handle bitcasts of vector predicates to scalars (e.g. v32i1 to i32).

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