Lines Matching refs:v32i1
1212 setOperationAction(ISD::BITCAST, MVT::v32i1, Custom);
1792 // This block control legalization of v32i1/v64i1 which are available with
1796 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1799 for (auto VT : { MVT::v32i1, MVT::v64i1 }) {
1820 for (auto VT : { MVT::v16i1, MVT::v32i1 })
1823 // Extends from v32i1 masks to 256-bit vectors.
2050 if ((VT == MVT::v32i1 || VT == MVT::v64i1) && Subtarget.hasAVX512() &&
2076 // v32i1 passes in ymm unless we have BWI and the calling convention is
2150 IntermediateVT = MVT::v32i1;
2584 if ((ValVT == MVT::v32i1 && ValLoc == MVT::i32) ||
2587 // bitcast: v32i1 -> i32 / v64i1 -> i64
2926 // Convert the i32 type into v32i1 type.
2927 Lo = DAG.getBitcast(MVT::v32i1, ArgValueLo);
2929 // Convert the i32 type into v32i1 type.
2930 Hi = DAG.getBitcast(MVT::v32i1, ArgValueHi);
2937 /// to a mask value of the expected size (v8i1/v16i1/v32i1/v64i1)
2960 case MVT::v32i1:
3638 else if (RegVT == MVT::v32i1)
9045 Select = DAG.getBitcast(MVT::v32i1, Select);
9065 ImmL = DAG.getBitcast(MVT::v32i1, ImmL);
9066 ImmH = DAG.getBitcast(MVT::v32i1, ImmH);
17755 case MVT::v32i1:
22667 !(Subtarget.hasBWI() && (VT == MVT::v32i1 || VT == MVT::v64i1)))
22683 if (Subtarget.hasBWI() && (VT == MVT::v32i1 || VT == MVT::v64i1))
24216 Lo = DAG.getBitcast(MVT::v32i1, Lo);
24217 Hi = DAG.getBitcast(MVT::v32i1, Hi);
28273 // half to v32i1 and concatenating the result.
28280 Lo = DAG.getBitcast(MVT::v32i1, Lo);
28283 Hi = DAG.getBitcast(MVT::v32i1, Hi);
28288 if ((SrcVT == MVT::v16i1 || SrcVT == MVT::v32i1) && DstVT.isScalarInteger()) {
38107 case MVT::v32i1:
44155 if ((VT == MVT::v8i1 || VT == MVT::v16i1 || VT == MVT::v32i1 ||
44160 SDValue Lo = DAG.getBuildVector(MVT::v32i1, dl,
44163 SDValue Hi = DAG.getBuildVector(MVT::v32i1, dl,
46428 CmpVT = PreferKOT ? MVT::v32i1 : VecVT;
46494 CmpVT == MVT::v32i1 ? MVT::i32 : MVT::i16;