Searched refs:v2i64 (Results 1 - 25 of 30) sorted by relevance

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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp216 // v2i64/v4i64 mul is custom lowered as a series of long:
221 { ISD::MUL, MVT::v2i64, 17 },
223 { ISD::ADD, MVT::v2i64, 4 },
224 { ISD::SUB, MVT::v2i64, 4 },
317 { ISD::SRA, MVT::v2i64, 1 },
514 { ISD::SHL, MVT::v2i64, 1 }, // psllq.
518 { ISD::SRL, MVT::v2i64, 1 }, // psrlq.
533 { ISD::MUL, MVT::v2i64, 1 },
566 { ISD::SRA, MVT::v2i64, 1 },
600 { ISD::SHL, MVT::v2i64,
[all...]
H A DX86ISelLowering.cpp874 addRegisterClass(MVT::v2i64, Subtarget.hasVLX() ? &X86::VR128XRegClass
891 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
903 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
920 setOperationAction(ISD::UADDSAT, MVT::v2i64, Custom);
921 setOperationAction(ISD::USUBSAT, MVT::v2i64, Custom);
927 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
948 for (auto VT : { MVT::v2f64, MVT::v2i64 }) {
953 if (VT == MVT::v2i64 && !Subtarget.is64Bit())
960 // Custom lower v2i64 and v2f64 selects.
962 setOperationAction(ISD::SELECT, MVT::v2i64, Custo
[all...]
H A DX86ISelDAGToDAG.cpp4090 VPTESTM_CASE(v2i64, QZ128##SUFFIX) \
5453 else if (IndexVT == MVT::v2i64 && NumElts == 4 && EltSize == 32)
5459 else if (IndexVT == MVT::v2i64 && NumElts == 2 && EltSize == 64)
5476 else if (IndexVT == MVT::v2i64 && NumElts == 4 && EltSize == 32)
5480 else if (IndexVT == MVT::v2i64 && NumElts == 2 && EltSize == 64)
5547 else if (IndexVT == MVT::v2i64 && NumElts == 4 && EltSize == 32)
5553 else if (IndexVT == MVT::v2i64 && NumElts == 2 && EltSize == 64)
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp326 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i32, 1 },
327 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i32, 1 },
336 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i8, 3 },
337 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i8, 3 },
338 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i16, 2 },
339 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i16, 2 },
482 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i8, 10 },
483 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i8, 2 },
486 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i16, 10 },
487 { ISD::ZERO_EXTEND, MVT::v2i64, MV
[all...]
H A DARMISelLowering.cpp217 VT != MVT::v2i64 && VT != MVT::v1i64)
387 const MVT LongTypes[] = { MVT::v2i64, MVT::v2f64 };
395 // We can do bitwise operations on v2i64 vectors
396 setOperationAction(ISD::AND, MVT::v2i64, Legal);
397 setOperationAction(ISD::OR, MVT::v2i64, Legal);
398 setOperationAction(ISD::XOR, MVT::v2i64, Legal);
797 addQRTypeForNEON(MVT::v2i64);
882 // Neon does not support some operations on v1i64 and v2i64 types.
887 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
917 setOperationAction(ISD::CTPOP, MVT::v2i64, Custo
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp339 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 },
342 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 },
347 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 2 },
350 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 2 },
380 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 },
383 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 },
385 // Complex, from v2f32: legal type is v2i32 (no cost) or v2i64 (1 ext).
386 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 2 },
389 { ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f32, 2 },
1044 { TTI::SK_Broadcast, MVT::v2i64,
[all...]
H A DAArch64ISelDAGToDAG.cpp699 case MVT::v2i64:
710 case MVT::v2i64:
3526 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3553 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3580 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3607 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3634 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3661 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3688 } else if (VT == MVT::v2i64 || VT == MVT::v2f64) {
3715 } else if (VT == MVT::v2i64 || V
[all...]
H A DAArch64SelectionDAGInfo.cpp101 MVT::v2i64,
H A DAArch64ISelLowering.cpp171 addQRTypeForNEON(MVT::v2i64);
808 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Custom);
809 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Custom);
830 setOperationAction(ISD::CTLZ, MVT::v2i64, Expand);
833 setOperationAction(ISD::MUL, MVT::v2i64, Expand);
837 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
840 MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
1043 if (!VT.isFloatingPoint() && VT != MVT::v2i64 && VT != MVT::v1i64)
1330 // Disregard v2i64. Memcpy lowering produces those and splitting
1332 VT == MVT::v2i64;
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/MCTargetDesc/
H A DWebAssemblyMCTargetDesc.cpp146 case MVT::v2i64:
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/Support/
H A DMachineValueType.h109 v2i64 = 59, // 2 x i64
375 SimpleTy == MVT::v2i64 || SimpleTy == MVT::v1i128 ||
527 case v2i64:
706 case v2i64:
844 case v2i64:
1070 if (NumElements == 2) return MVT::v2i64;
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp64 addRegisterClass(MVT::v2i64, &WebAssembly::V128RegClass);
117 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64})
136 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64,
141 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64,
147 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64})
152 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64,
161 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64,
168 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64})
185 setCondCodeAction(static_cast<ISD::CondCode>(CC), MVT::v2i64, Custom); member in class:MVT
190 for (auto T : {MVT::v2i64, MV
[all...]
H A DWebAssemblyAsmPrinter.cpp61 MVT::v4i32, MVT::v2i64, MVT::v4f32, MVT::v2f64})
H A DWebAssemblyFastISel.cpp142 case MVT::v2i64:
695 case MVT::v2i64:
800 case MVT::v2i64:
1321 case MVT::v2i64:
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp637 // For v2i64, these are only valid with P8Vector. This is corrected after
742 setOperationAction(ISD::SMAX, MVT::v2i64, Expand);
743 setOperationAction(ISD::SMIN, MVT::v2i64, Expand);
744 setOperationAction(ISD::UMAX, MVT::v2i64, Expand);
745 setOperationAction(ISD::UMIN, MVT::v2i64, Expand);
748 for (auto VT : {MVT::v2i64, MVT::v4i32, MVT::v8i16, MVT::v16i8})
779 // Without hasP8Altivec set, v2i64 SMAX isn't available.
782 setOperationAction(ISD::ABS, MVT::v2i64, Expand);
792 setOperationAction(ISD::ROTL, MVT::v2i64, Legal);
840 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i64, Lega
[all...]
H A DPPCTargetTransformInfo.cpp918 (LT.second == MVT::v2f64 || LT.second == MVT::v2i64);
H A DPPCISelDAGToDAG.cpp3939 // only support the altivec types (v16i8, v8i16, v4i32, v2i64, and v4f32).
4018 else if (VecVT == MVT::v2i64)
4028 else if (VecVT == MVT::v2i64)
4038 else if (VecVT == MVT::v2i64)
5105 N->getValueType(0) == MVT::v2i64)
5117 N->getValueType(0) == MVT::v2i64)) {
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelDAGToDAG.cpp1089 ViaVecTy = MVT::v2i64;
1181 CurDAG->getMachineNode(Mips::FILL_D, DL, MVT::v2i64, SDValue(Res, 0));
1271 Mips::SPLATI_D, DL, MVT::v2i64, SDValue(Res, 0),
1318 Res = CurDAG->getMachineNode(Mips::FILL_D, DL, MVT::v2i64,
H A DMipsSEISelLowering.cpp121 addMSAIntType(MVT::v2i64, &Mips::MSA128DRegClass);
355 if (Ty == MVT::v4i32 || Ty == MVT::v2i64) {
1380 // When ResVecTy == MVT::v2i64, LaneA is the upper 32 bits of the lane and
1386 if (ResVecTy == MVT::v2i64) {
1434 if (VecTy == MVT::v2i64) {
1435 // v2i64 BUILD_VECTOR must be performed via v4i32 so split into i32's.
1472 if (VecTy == MVT::v2i64) {
1484 ISD::BITCAST, DL, MVT::v2i64,
1495 if (VecTy == MVT::v2i64)
1512 MVT ResEltTy = ResTy == MVT::v2i64
[all...]
H A DMipsSEInstrInfo.cpp280 else if (TRI->isTypeLegalForClass(*RC, MVT::v2i64) ||
358 else if (TRI->isTypeLegalForClass(*RC, MVT::v2i64) ||
/freebsd-13-stable/contrib/llvm-project/clang/lib/Headers/
H A Dmsa.h26 typedef long long v2i64 __attribute__((vector_size(16), aligned(16))); typedef
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp108 addRegisterClass(MVT::v2i64, &SystemZ::VR128BitRegClass);
359 if (VT != MVT::v2i64)
401 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
403 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
405 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
407 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
410 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v2i64, Legal);
412 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v2i64, Legal);
414 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v2i64, Legal);
416 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v2i64, Lega
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp101 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
102 AddPromotedToType(ISD::LOAD, MVT::v2i64, MVT::v4i32);
221 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
222 AddPromotedToType(ISD::STORE, MVT::v2i64, MVT::v4i32);
253 setTruncStoreAction(MVT::v2i64, MVT::v2i1, Expand);
254 setTruncStoreAction(MVT::v2i64, MVT::v2i8, Expand);
255 setTruncStoreAction(MVT::v2i64, MVT::v2i16, Expand);
256 setTruncStoreAction(MVT::v2i64, MVT::v2i32, Expand);
352 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i64, Custom);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DValueTypes.cpp285 case MVT::v2i64:
/freebsd-13-stable/contrib/llvm-project/llvm/utils/TableGen/
H A DCodeGenTarget.cpp124 case MVT::v2i64: return "MVT::v2i64";

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