Lines Matching refs:v2i64
108 addRegisterClass(MVT::v2i64, &SystemZ::VR128BitRegClass);
359 if (VT != MVT::v2i64)
401 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
403 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
405 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
407 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
410 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v2i64, Legal);
412 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v2i64, Legal);
414 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v2i64, Legal);
416 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v2i64, Legal);
1330 Value = DAG.getBuildVector(MVT::v2i64, DL, {Value, DAG.getUNDEF(MVT::i64)});
1351 // bitcast to v2i64 and then extract first element.
1354 Value = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Value);
1418 case MVT::v2i64:
2789 SDVTList VTs = DAG.getVTList(MVT::v2i64, MVT::Other);
2800 SDValue HRes = DAG.getNode(Opcode, DL, MVT::v2i64, H0, H1);
2801 SDValue LRes = DAG.getNode(Opcode, DL, MVT::v2i64, L0, L1);
4886 // Extend GPR scalars Op0 and Op1 to doublewords and return a v2i64
4891 return DAG.getUNDEF(MVT::v2i64);
4902 return DAG.getNode(SystemZISD::JOIN_DWORDS, DL, MVT::v2i64, Op0, Op1);
5009 // The best way of building a v2i64 from two i64s is to use VLVGP.
5010 if (VT == MVT::v2i64 && !AllLoads)
5035 Op01 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Op01);
5036 Op23 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Op23);
5038 DL, MVT::v2i64, Op01, Op23);
5994 if (VT == MVT::v8i16 || VT == MVT::v4i32 || VT == MVT::v2i64)
6325 // v2f64 = uint_to_fp (v2i64 zero_extend v2i16)