Searched refs:getNode (Results 1 - 25 of 183) sorted by relevance

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/freebsd-13-stable/contrib/llvm-project/llvm/lib/BinaryFormat/
H A DMsgPackDocument.cpp31 return find(getDocument()->getNode(S));
37 return (*this)[getDocument()->getNode(S)];
53 return (*this)[getDocument()->getNode(Key)];
56 return (*this)[getDocument()->getNode(Key)];
59 return (*this)[getDocument()->getNode(Key)];
62 return (*this)[getDocument()->getNode(Key)];
80 *this = getDocument()->getNode(Val);
84 *this = getDocument()->getNode(Val);
88 *this = getDocument()->getNode(Val);
92 *this = getDocument()->getNode(Va
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H A DMsgPackDocumentYAML.cpp75 *this = getDocument()->getNode(uint64_t(0));
78 *this = getDocument()->getNode(int64_t(0));
85 *this = getDocument()->getNode();
89 *this = getDocument()->getNode(false);
95 *this = getDocument()->getNode(0.0);
104 *this = getDocument()->getNode(V, /*Copy=*/true);
116 ScalarDocNode N = getDocument()->getNode();
211 ScalarDocNode KeyObj = M.getDocument()->getNode();
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp822 if (!allUsesHaveSourceMods(Op.getNode()))
1125 return DAG.getNode(AMDGPUISD::ENDPGM, DL, MVT::Other, Chain);
1157 for (SDNode::use_iterator U = DAG.getEntryNode().getNode()->use_begin(),
1158 UE = DAG.getEntryNode().getNode()->use_end();
1176 return DAG.getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, ArgChains);
1311 SDValue Trap = DAG.getNode(ISD::TRAP, DL, MVT::Other, DAG.getEntryNode());
1312 SDValue OutputChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
1343 SDValue Lo = DAG.getNode(ISD::BITCAST, SL, MVT::i32, Op.getOperand(0));
1344 SDValue Hi = DAG.getNode(ISD::BITCAST, SL, MVT::i32, Op.getOperand(1));
1347 return DAG.getNode(IS
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H A DAMDGPUHSAMetadataStreamer.cpp587 Dims.push_back(Dims.getDocument()->getNode(
594 Version.push_back(Version.getDocument()->getNode(VersionMajor));
595 Version.push_back(Version.getDocument()->getNode(VersionMinor));
607 Printf.push_back(Printf.getDocument()->getNode(
622 Kern[".language"] = Kern.getDocument()->getNode("OpenCL C");
624 LanguageVersion.push_back(Kern.getDocument()->getNode(
626 LanguageVersion.push_back(Kern.getDocument()->getNode(
639 Kern[".vec_type_hint"] = Kern.getDocument()->getNode(
646 Kern[".device_enqueue_symbol"] = Kern.getDocument()->getNode(
729 Arg[".name"] = Arg.getDocument()->getNode(Nam
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H A DR600ISelLowering.cpp493 assert((!Result.getNode() ||
494 Result.getNode()->getNumValues() == 2) &&
519 return DAG.getNode(AMDGPUISD::R600_EXPORT, DL, Op.getValueType(), Args);
569 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, MVT::v4f32, TexArgs);
573 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
575 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
577 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
579 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2),
581 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1),
583 DAG.getNode(IS
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp331 AddToWorklist(Op.getNode());
394 // SDValue.getNode() == 0 - No change was made
395 // SDValue.getNode() == N - N was replaced, is dead and has been handled.
865 AddToWorklist(Op.getNode());
903 !TLI.isConstTrueVal(N.getOperand(2).getNode()) ||
904 !TLI.isConstFalseVal(N.getOperand(3).getNode()))
922 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse())
931 return N.getNode();
932 if (ISD::isBuildVectorOfConstantFPSDNodes(N.getNode()))
933 return N.getNode();
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H A DLegalizeIntegerTypes.cpp211 if (Res.getNode())
224 return DAG.getNode(ISD::AssertSext, SDLoc(N),
231 return DAG.getNode(ISD::AssertZext, SDLoc(N),
324 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp));
328 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp));
331 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftPromotedHalf(InOp));
335 return DAG.getNode(ISD::FP_TO_FP16, dl, NOutVT, GetPromotedFloat(InOp));
344 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
361 InOp = DAG.getNode(ISD::ANY_EXTEND, dl,
365 return DAG.getNode(IS
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H A DLegalizeDAG.cpp225 UpdatedNodes->insert(New.getNode());
226 ReplacedNode(Old.getNode());
237 UpdatedNodes->insert(New[i].getNode());
248 UpdatedNodes->insert(New.getNode());
249 ReplacedNode(Old.getNode());
380 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
408 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
478 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
496 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
530 Value = DAG.getNode(IS
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H A DResourcePriorityQueue.cpp78 const SDNode *ScegN = PredSU->getNode();
116 const SDNode *ScegN = SuccSU->getNode();
135 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo());
244 if (!SU || !SU->getNode())
249 if (SU->getNode()->getGluedNode())
254 if (SU->getNode()->isMachineOpcode())
255 switch (SU->getNode()->getMachineOpcode()) {
258 SU->getNode()->getMachineOpcode())))
289 if (!isResourceAvailable(SU) || SU->getNode()->getGluedNode()) {
294 if (SU->getNode()
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H A DLegalizeVectorTypes.cpp180 if (R.getNode())
187 return DAG.getNode(N->getOpcode(), SDLoc(N),
195 return DAG.getNode(N->getOpcode(), SDLoc(N), Op0.getValueType(), Op0, Op1,
203 return DAG.getNode(N->getOpcode(), SDLoc(N), Op0.getValueType(), Op0, Op1,
229 SDValue Result = DAG.getNode(N->getOpcode(), dl, DAG.getVTList(ValueVTs),
258 SDNode *ScalarNode = DAG.getNode(
259 N->getOpcode(), DL, ScalarVTs, ScalarLHS, ScalarRHS).getNode();
268 SDValue OtherVal = DAG.getNode(
289 return DAG.getNode(ISD::BITCAST, SDLoc(N),
299 return DAG.getNode(IS
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H A DTargetLowering.cpp417 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Call.second,
419 NewLHS = DAG.getNode(ShouldInvertCC ? ISD::AND : ISD::OR, dl,
495 return TLO.New.getNode();
516 SDValue NewOp = TLO.DAG.getNode(Opcode, DL, VT, Op.getOperand(0), NewC);
545 assert(Op.getNode()->getNumValues() == 1 &&
557 if (!Op.getNode()->hasOneUse())
572 SDValue X = DAG.getNode(
574 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, Op.getOperand(0)),
575 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, Op.getOperand(1)));
577 SDValue Z = DAG.getNode(IS
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H A DLegalizeTypesGeneric.cpp58 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
59 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
69 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
70 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
77 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
78 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
83 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
84 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
96 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
97 Hi = DAG.getNode(IS
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H A DLegalizeVectorOps.cpp255 SDNode *Node = DAG.UpdateNodeOperands(Op.getNode(), Ops);
530 if (!Res.getNode())
599 Operands[j] = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(j));
601 Operands[j] = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(j));
607 DAG.getNode(Node->getOpcode(), dl, NVT, Operands, Node->getFlags());
612 Res = DAG.getNode(ISD::FP_ROUND, dl, VT, Res, DAG.getIntPtrConstant(0, dl));
614 Res = DAG.getNode(ISD::BITCAST, dl, VT, Res);
638 Operands[j] = DAG.getNode(Opc, dl, NVT, Node->getOperand(j));
644 SDValue Res = DAG.getNode(Node->getOpcode(), dl,
652 DAG.getNode(Nod
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/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachinePostDominators.h47 return PDT->getNode(BB);
50 MachineDomTreeNode *getNode(MachineBasicBlock *BB) const { function in class:llvm::MachinePostDominatorTree
51 return PDT->getNode(BB);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZSelectionDAGInfo.cpp41 return DAG.getNode(Loop, DL, MVT::Other, Chain, Dst, Src,
44 return DAG.getNode(Sequence, DL, MVT::Other, Chain, Dst, Src,
103 Dst = DAG.getNode(ISD::ADD, DL, PtrVT, Dst,
109 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chain1, Chain2);
118 SDValue Dst2 = DAG.getNode(ISD::ADD, DL, PtrVT, Dst,
123 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chain1, Chain2);
137 SDValue DstPlus1 = DAG.getNode(ISD::ADD, DL, PtrVT, Dst,
160 return DAG.getNode(SystemZISD::CLC_LOOP, DL, VTs, Chain, Src1, Src2,
163 return DAG.getNode(SystemZISD::CLC, DL, VTs, Chain, Src1, Src2,
173 SDValue IPM = DAG.getNode(SystemZIS
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp215 case ISD::SUB: return ExpandADDSUB(Op.getNode(), DAG);
256 return DAG.getNode(XCoreISD::PCRelativeWrapper, dl, MVT::i32, GA);
261 return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, GA);
263 return DAG.getNode(XCoreISD::DPRelativeWrapper, dl, MVT::i32, GA);
294 GA = DAG.getNode(ISD::ADD, DL, MVT::i32, GA, Remaining);
319 return DAG.getNode(XCoreISD::PCRelativeWrapper, DL, PtrVT, Result);
337 return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, Res);
359 return DAG.getNode(XCoreISD::BR_JT, dl, MVT::Other, Chain, TargetJT, Index);
362 SDValue ScaledIndex = DAG.getNode(ISD::SHL, dl, MVT::i32, Index,
364 return DAG.getNode(XCoreIS
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineDominators.cpp104 MachineDomTreeNode *SuccDTNode = DT->getNode(Succ);
127 if (!DT->dominates(SuccDTNode, DT->getNode(PredBB))) {
145 DT->changeImmediateDominator(DT->getNode(Edge.ToBB), NewDTNode);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp354 if (Result.getNode()) {
471 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue,
474 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue,
478 ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue);
520 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain);
586 if (Flag.getNode())
590 return DAG.getNode(Opc, DL, MVT::Other,
667 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
670 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
673 Arg = DAG.getNode(IS
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp2040 Val = DAG.getNode(ISD::BITCAST, dl, MVT::getIntegerVT(LocVT.getSizeInBits()),
2043 Val = DAG.getNode(ARMISD::VMOVhr, dl, ValVT, Val);
2045 Val = DAG.getNode(ISD::TRUNCATE, dl,
2047 Val = DAG.getNode(ISD::BITCAST, dl, ValVT, Val);
2056 Val = DAG.getNode(ARMISD::VMOVrh, dl,
2059 Val = DAG.getNode(ISD::BITCAST, dl,
2061 Val = DAG.getNode(ISD::ZERO_EXTEND, dl,
2064 return DAG.getNode(ISD::BITCAST, dl, LocVT, Val);
2108 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
2111 SDValue Vec = DAG.getNode(IS
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp2387 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
2569 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, Dl, ValLoc, ValArg,
2580 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, Dl, ValLoc, ValToCopy);
2591 return DAG.getNode(ISD::ANY_EXTEND, Dl, ValLoc, ValArg);
2610 Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, Dl, MVT::i32, Arg,
2612 Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, Dl, MVT::i32, Arg,
2657 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2659 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2664 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2693 ValToCopy = DAG.getNode(IS
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1181 New = TLO.DAG.getNode(Op.getOpcode(), DL, VT, Op.getOperand(0),
1895 return DAG.getNode(Opcode, dl, {VT, MVT::Other}, {Chain, LHS, RHS});
1907 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, LHS);
1908 RHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, RHS);
1911 return DAG.getNode(AArch64ISD::FCMP, dl, VT, LHS, RHS);
1934 const SDValue ANDSNode = DAG.getNode(AArch64ISD::ANDS, dl,
1947 return DAG.getNode(Opcode, dl, DAG.getVTList(VT, MVT_CC), LHS, RHS)
2016 LHS = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, LHS);
2017 RHS = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, RHS);
2035 return DAG.getNode(Opcod
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp419 SDValue Tmp = DAG.getNode(MipsISD::MTC1_D64, DL, MVT::f64, Op->getOperand(0));
420 return DAG.getNode(MipsISD::FSELECT, DL, ResTy, Tmp, Op->getOperand(1),
516 return DAG.getNode(MipsISD::VEXTRACT_ZEXT_ELT, SDLoc(Op0),
535 BuildVectorSDNode *Node = dyn_cast<BuildVectorSDNode>(N.getNode());
643 if (!IfClr.getNode() && isVSplat(Op0Op1, Mask, IsLittleEndian)) {
660 if (!IfClr.getNode()) {
697 if (!IfClr.getNode())
700 assert(Cond.getNode() && IfSet.getNode());
711 return DAG.getNode(IS
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.cpp104 OutVal = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), OutVal);
107 OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), OutVal);
110 OutVal = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), OutVal);
128 if (Flag.getNode())
131 return DAG.getNode(VEISD::RET_FLAG, DL, MVT::Other, RetOps);
168 Arg = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), Arg,
175 Arg = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Arg,
179 Arg = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Arg,
188 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg);
336 Callee = DAG.getNode(VEIS
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp242 SDValue Part0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32,
245 SDValue Part1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32,
282 if (Flag.getNode())
285 return DAG.getNode(SPISD::RET_FLAG, DL, MVT::Other, RetOps);
323 OutVal = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), OutVal);
326 OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), OutVal);
329 OutVal = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), OutVal);
338 OutVal = DAG.getNode(ISD::SHL, DL, MVT::i64, OutVal,
344 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, OutVals[i+1]);
345 OutVal = DAG.getNode(IS
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp224 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, ResTy, IntOps);
271 return DAG.getNode(ISD::CONCAT_VECTORS, dl, typeJoin(ty(Ops)),
339 return DAG.getNode(ISD::SHL, dl, MVT::i32,
355 SDValue SubIdx = DAG.getNode(ISD::AND, dl, MVT::i32, {Idx, Mask});
423 if (!SplatV.getNode())
431 assert(SplatV.getNode());
432 auto *IdxN = dyn_cast<ConstantSDNode>(SplatV.getNode());
435 return DAG.getNode(HexagonISD::VSPLATW, dl, VecTy, SplatV);
472 if (Vec.getNode() != nullptr && T.getNode() !
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