/freebsd-13-stable/sys/contrib/octeon-sdk/ |
H A D | cvmx-helper-rgmii.c | 161 cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 1); 162 cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x200); 163 cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0x2000); 164 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64); 166 cvmx_write_csr(CVMX_ASXX_PRT_LOOP(interface), (1 << index) | tmp); 168 cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(interface), (1 << index) | tmp); 170 cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface), (1 << index) | tmp); 172 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64); 203 cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(interface), asx_tx.u64); 207 cvmx_write_csr(CVMX_ASXX_RX_PRT_E [all...] |
H A D | cvmx-zip.c | 82 cvmx_write_csr(CVMX_ZIP_CMD_BUF, zip_cmd_buf.u64); 83 cvmx_write_csr(CVMX_ZIP_ERROR, 1); 123 cvmx_write_csr(CVMX_ZIP_QUEX_BUF(queue), zip_que_buf.u64); 128 cvmx_write_csr(CVMX_ZIP_QUEX_MAP(queue), que_map.u64); 133 cvmx_write_csr(CVMX_ZIP_QUE_ENA, que_ena.u64); 136 cvmx_write_csr(CVMX_ZIP_QUE_PRI, 0x3); 144 cvmx_write_csr(CVMX_ZIP_INT_REG, int_reg.u64); 168 cvmx_write_csr(CVMX_ZIP_CMD_CTL, zip_cmd_ctl.u64); 195 cvmx_write_csr(CVMX_ZIP_CMD_CTL, zip_cmd_ctl.u64); 213 cvmx_write_csr(CVMX_ADDR_DI [all...] |
H A D | cvmx-gpio.h | 89 cvmx_write_csr(CVMX_CIU_INTX_SUM0(core * 2), ciu_sum0.u64); 92 cvmx_write_csr(CVMX_GPIO_INT_CLR, (clear_mask & ~0xf0)); 100 cvmx_write_csr(CVMX_GPIO_INT_CLR, gpio_int_clr.u64); 123 cvmx_write_csr(CVMX_GPIO_XBIT_CFGX(bit), gpio_xbit.u64); 136 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(bit), gpio_bit.u64); 163 cvmx_write_csr(CVMX_GPIO_TX_CLR, gpio_tx_clr.u64); 177 cvmx_write_csr(CVMX_GPIO_TX_SET, gpio_tx_set.u64);
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H A D | cvmx-helper-xaui.c | 123 cvmx_write_csr(CVMX_CIU_QLM2, ciu_qlm.u64); 142 cvmx_write_csr(CVMX_CIU_QLM2, ciu_qlm.u64); 163 cvmx_write_csr(CVMX_GMXX_INF_MODE(interface), mode.u64); 183 cvmx_write_csr(CVMX_PKO_MEM_PORT_PTRS, pko_mem_port_ptrs.u64); 211 cvmx_write_csr (CVMX_PCSXX_MISC_CTL_REG(interface), xauiMiscCtl.u64); 214 cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0,interface), 0x0); 215 cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), 0x0); 216 cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), 0x0); 224 cvmx_write_csr (CVMX_GMXX_TX_XAUI_CTL(interface), gmxXauiTxCtl.u64); 237 cvmx_write_csr (CVMX_PCSXX_CONTROL1_RE [all...] |
H A D | cvmx-uart.c | 62 cvmx_write_csr(CVMX_MIO_UARTX_IER(uart), ier.u64); 110 cvmx_write_csr(CVMX_MIO_UARTX_FCR(uart_index), fcrval.u64); 128 cvmx_write_csr(CVMX_MIO_UARTX_LCR(uart_index), lcrval.u64); 130 cvmx_write_csr(CVMX_MIO_UARTX_DLL(uart_index), divisor & 0xff); 131 cvmx_write_csr(CVMX_MIO_UARTX_DLH(uart_index), (divisor>>8) & 0xff); 134 cvmx_write_csr(CVMX_MIO_UARTX_LCR(uart_index), lcrval.u64); 155 cvmx_write_csr(CVMX_MIO_UARTX_MCR(uart_index), mcrval.u64);
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H A D | cvmx-ipd.h | 124 cvmx_write_csr(CVMX_IPD_1ST_MBUFF_SKIP, first_skip.u64); 128 cvmx_write_csr(CVMX_IPD_NOT_1ST_MBUFF_SKIP, not_first_skip.u64); 132 cvmx_write_csr(CVMX_IPD_PACKET_MBUFF_SIZE, size.u64); 136 cvmx_write_csr(CVMX_IPD_1st_NEXT_PTR_BACK, first_back_struct.u64); 140 cvmx_write_csr(CVMX_IPD_2nd_NEXT_PTR_BACK,second_back_struct.u64); 144 cvmx_write_csr(CVMX_IPD_WQE_FPA_QUEUE, wqe_pool.u64); 149 cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_ctl_reg.u64); 182 cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_reg.u64); 194 cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_reg.u64);
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H A D | cvmx-raid.c | 81 cvmx_write_csr(CVMX_RAD_REG_POLYNOMIAL, polynomial.u64); 94 cvmx_write_csr(CVMX_RAD_REG_CMD_BUF, rad_reg_cmd_buf.u64); 119 cvmx_write_csr(CVMX_RAD_REG_CTL, rad_reg_ctl.u64); 123 cvmx_write_csr(CVMX_RAD_REG_CMD_BUF, 0); 142 cvmx_write_csr(CVMX_ADDR_DID(CVMX_FULL_DID(14, 0)), num_words);
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H A D | cvmx-crypto.c | 61 cvmx_write_csr(CVMX_RNM_EER_KEY, v.u64);
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H A D | cvmx-gmx.h | 86 cvmx_write_csr(CVMX_GMXX_TX_OVR_BP(interface), gmxx_tx_ovr_bp.u64);
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H A D | cvmx-dma-engine.c | 122 cvmx_write_csr(CVMX_PEXP_NPEI_DMAX_IBUFF_SADDR(engine), dmax_ibuff_saddr.u64); 130 cvmx_write_csr(CVMX_DPI_DMAX_IBUFF_SADDR(engine), dpi_dmax_ibuff_saddr.u64); 136 cvmx_write_csr(CVMX_NPI_HIGHP_IBUFF_SADDR, address); 138 cvmx_write_csr(CVMX_NPI_LOWP_IBUFF_SADDR, address); 157 cvmx_write_csr(CVMX_PEXP_NPEI_DMA_CONTROL, dma_control.u64); 168 cvmx_write_csr(CVMX_PEXP_NPEI_DMA_PCIE_REQ_NUM, pcie_req_num.u64); 182 cvmx_write_csr(CVMX_DPI_ENGX_BUF(0), dpi_engx_buf.u64); 183 cvmx_write_csr(CVMX_DPI_ENGX_BUF(1), dpi_engx_buf.u64); 184 cvmx_write_csr(CVMX_DPI_ENGX_BUF(2), dpi_engx_buf.u64); 185 cvmx_write_csr(CVMX_DPI_ENGX_BU [all...] |
H A D | cvmx-spi.c | 235 cvmx_write_csr(CVMX_SPXX_INT_MSK(interface), 0); 237 cvmx_write_csr(CVMX_STXX_INT_MSK(interface), 0); 240 cvmx_write_csr(CVMX_SRXX_COM_CTL(interface), 0); 241 cvmx_write_csr(CVMX_STXX_COM_CTL(interface), 0); 244 cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64); 262 cvmx_write_csr(CVMX_SRXX_SPI4_CALX(index, interface), srxx_spi4_calx.u64); 266 cvmx_write_csr(CVMX_STXX_SPI4_CALX(index, interface), stxx_spi4_calx.u64); 270 cvmx_write_csr(CVMX_SPXX_INT_REG(interface), cvmx_read_csr(CVMX_SPXX_INT_REG(interface))); 271 cvmx_write_csr(CVMX_SPXX_INT_MSK(interface), spxx_int_msk.u64); 272 cvmx_write_csr(CVMX_STXX_INT_RE [all...] |
H A D | cvmx-helper-errata.c | 123 cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), 0); 144 cvmx_write_csr(CVMX_ASXX_PRT_LOOP(INTERFACE(FIX_IPD_OUTPORT)), 1 << INDEX(FIX_IPD_OUTPORT)); 193 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)), gmx_cfg.u64); 194 cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), 1 << INDEX(FIX_IPD_OUTPORT)); 195 cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), 1 << INDEX(FIX_IPD_OUTPORT)); 197 cvmx_write_csr(CVMX_GMXX_RXX_JABBER(INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)), 65392-14-4); 198 cvmx_write_csr(CVMX_GMXX_RXX_FRM_MAX(INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)), 65392-14-4); 222 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)), prtx_cfg); 223 cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), tx_ptr_en); 224 cvmx_write_csr(CVMX_ASXX_RX_PRT_E [all...] |
H A D | cvmx-ilk.c | 201 cvmx_write_csr (CVMX_ILK_SER_CFG, ilk_ser_cfg.u64); 207 cvmx_write_csr (CVMX_ILK_TXX_CFG0(interface), ilk_txx_cfg0.u64); 208 cvmx_write_csr (CVMX_ILK_RXX_CFG0(interface), ilk_rxx_cfg0.u64); 256 cvmx_write_csr (CVMX_ILK_TXX_PIPE(interface), ilk_txx_pipe.u64); 295 cvmx_write_csr(CVMX_ILK_TXX_IDX_PMAP(interface), ilk_txx_idx_pmap.u64); 296 cvmx_write_csr(CVMX_ILK_TXX_MEM_PMAP(interface), pch->chan); 338 cvmx_write_csr (CVMX_ILK_RXF_IDX_PMAP, ilk_rxf_idx_pmap.u64); 339 cvmx_write_csr (CVMX_ILK_RXF_MEM_PMAP, chpknd->pknd); 390 cvmx_write_csr (CVMX_ILK_RXX_CFG0(interface), ilk_rxx_cfg0.u64); 397 cvmx_write_csr (CVMX_ILK_RXX_IDX_CA [all...] |
H A D | cvmx-dfa.c | 82 cvmx_write_csr(CVMX_DFA_DIFCTL, control.u64); 91 cvmx_write_csr(CVMX_DFA_DIFRDPTR, cvmx_ptr_to_phys(initial_base_address));
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H A D | cvmx-ipd.c | 124 cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL, ipd_pwp_ptr_fifo_ctl.u64); 132 cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL, ipd_pwp_ptr_fifo_ctl.u64); 151 cvmx_write_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL, ipd_prc_port_ptr_fifo_ctl.u64); 156 cvmx_write_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL, ipd_prc_port_ptr_fifo_ctl.u64); 169 cvmx_write_csr(CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL, ipd_prc_hold_ptr_fifo_ctl.u64); 174 cvmx_write_csr(CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL, ipd_prc_hold_ptr_fifo_ctl.u64); 186 cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL, ipd_pwp_ptr_fifo_ctl.u64); 191 cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL, ipd_pwp_ptr_fifo_ctl.u64); 231 cvmx_write_csr(CVMX_IPD_FREE_PTR_FIFO_CTL, ipd_free_ptr_fifo_ctl.u64); 240 cvmx_write_csr(CVMX_IPD_FREE_PTR_FIFO_CT [all...] |
H A D | cvmx-helper-sgmii.c | 112 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64); 135 cvmx_write_csr(CVMX_PCSX_LINKX_TIMER_COUNT_REG(index, interface), pcsx_linkx_timer_count_reg.u64); 152 cvmx_write_csr(CVMX_PCSX_ANX_ADV_REG(index, interface), pcsx_anx_adv_reg.u64); 163 cvmx_write_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface), pcsx_miscx_ctl_reg.u64); 173 cvmx_write_csr(CVMX_PCSX_SGMX_AN_ADV_REG(index, interface), pcsx_sgmx_an_adv_reg.u64); 236 cvmx_write_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface), control_reg.u64); 248 cvmx_write_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface), control_reg.u64); 289 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64); 320 cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 64); 321 cvmx_write_csr(CVMX_GMXX_TXX_BURS [all...] |
H A D | cvmx-llm.c | 714 cvmx_write_csr (CVMX_DFA_DDR2_CFG, dfaCfg.u64); 721 cvmx_write_csr (CVMX_DFA_DDR2_PLL, dfaPll.u64); 724 cvmx_write_csr (CVMX_DFA_DDR2_PLL, dfaPll.u64); 728 cvmx_write_csr (CVMX_DFA_DDR2_PLL, dfaPll.u64); 733 cvmx_write_csr (CVMX_DFA_ECLKCFG, dfaEcklCfg.u64); 743 cvmx_write_csr (CVMX_DFA_DDR2_CFG, dfaCfg.u64); 747 cvmx_write_csr (CVMX_DFA_ECLKCFG, dfaEcklCfg.u64); 753 cvmx_write_csr (CVMX_DFA_DDR2_ADDR, dfaAddr.u64); 772 cvmx_write_csr (CVMX_DFA_DDR2_TMG, dfaTmg.u64); 776 cvmx_write_csr (CVMX_DFA_DDR2_CF [all...] |
H A D | cvmx-interrupt.c | 149 cvmx_write_csr(CVMX_MIO_UARTX_THR(0), '\r'); 150 cvmx_write_csr(CVMX_MIO_UARTX_THR(0), *ptr++); 406 cvmx_write_csr(CVMX_CIU_EN2_PPX_IP2(core), cvmx_interrupt_ciu_61xx_timer_mirror); 420 cvmx_write_csr(CVMX_CIU_INTX_EN0(ciu_offset), cvmx_interrupt_ciu_en0_mirror); 438 cvmx_write_csr(CVMX_CIU_INTX_EN1(ciu_offset), cvmx_interrupt_ciu_en1_mirror); 478 cvmx_write_csr(CVMX_CIU_INTX_EN1(ciu_offset), cvmx_interrupt_ciu_en1_mirror); 520 cvmx_write_csr(mask_reg, 1ull << (sum_bit - 60)); 545 cvmx_write_csr(mask_reg, 1ull << src_bit); 741 cvmx_write_csr(reg, 1ull << bit); 784 cvmx_write_csr(CVMX_CIU_EN2_PPX_IP [all...] |
H A D | cvmx-pcie.c | 215 cvmx_write_csr(CVMX_PEXP_NPEI_CTL_STATUS2, npei_ctl_status2.u64); 228 cvmx_write_csr(CVMX_DPI_SLI_PRTX_CFG(pcie_port), prt_cfg.u64); 232 cvmx_write_csr(CVMX_PEXP_SLI_S2M_PORTX_CTL(pcie_port), sli_s2m_portx_ctl.u64); 409 cvmx_write_csr(CVMX_PESCX_CTL_STATUS(pcie_port),pescx_ctl_status.u64); 415 cvmx_write_csr(CVMX_PESCX_CTL_STATUS(pcie_port), pescx_ctl_status.u64); 435 cvmx_write_csr(CVMX_PEXP_NPEI_INT_SUM, cvmx_read_csr(CVMX_PEXP_NPEI_INT_SUM)); 531 cvmx_write_csr(CVMX_PEXP_NPEI_CTL_STATUS, npei_ctl_status.u64); 550 cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64); 553 cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64); 559 cvmx_write_csr(CVMX_CIU_SOFT_PRST [all...] |
H A D | cvmx-helper-jtag.c | 100 cvmx_write_csr(CVMX_CIU_QLM_JTGC, jtgc.u64); 129 cvmx_write_csr(CVMX_CIU_QLM_JTGC, jtgc.u64); 138 cvmx_write_csr(CVMX_CIU_QLM_JTGD, jtgd.u64); 187 cvmx_write_csr(CVMX_CIU_QLM_JTGC, jtgc.u64); 195 cvmx_write_csr(CVMX_CIU_QLM_JTGD, jtgd.u64); 218 cvmx_write_csr(CVMX_CIU_QLM_JTGC, jtgc.u64); 225 cvmx_write_csr(CVMX_CIU_QLM_JTGD, jtgd.u64);
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H A D | cvmx-helper.c | 474 cvmx_write_csr(CVMX_PIP_PRT_CFGBX(pknd), prt_cfgbx.u64); 543 cvmx_write_csr(CVMX_PIP_SUB_PKIND_FCSX(0), pkind_fcsx.u64); 551 cvmx_write_csr(CVMX_PIP_PRT_CFGX(pknd), port_cfg.u64); 825 cvmx_write_csr(CVMX_IOB_FAU_TIMEOUT, fau_to.u64); 838 cvmx_write_csr(CVMX_PKO_REG_MIN_PKT, min_pkt.u64); 904 cvmx_write_csr(CVMX_IPD_INT_ENB, 0); 909 cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_reg.u64); 914 cvmx_write_csr(CVMX_IPD_PORTX_BP_PAGE_CNT(port0), 1<<17); 916 cvmx_write_csr(CVMX_IPD_SUB_PORT_BP_PAGE_CNT, (port0<<25) | 1000); 922 cvmx_write_csr(CVMX_IPD_PORTX_BP_PAGE_CN [all...] |
H A D | cvmx-higig.h | 343 cvmx_write_csr(CVMX_PIP_PRT_CFGX(pknd), pip_prt_cfg.u64); 355 cvmx_write_csr(CVMX_PIP_HG_PRI_QOS, pip_hg_pri_qos.u64); 363 cvmx_write_csr(CVMX_GMXX_RXX_UDD_SKP(0, interface), gmx_rx_udd_skp.u64); 368 cvmx_write_csr(CVMX_GMXX_RXX_FRM_CTL(0, interface), gmx_rx_frm_ctl.u64); 373 cvmx_write_csr(CVMX_GMXX_TXX_MIN_PKT(0, interface), gmx_tx_min_pkt.u64); 378 cvmx_write_csr(CVMX_GMXX_TXX_APPEND(0, interface), gmx_tx_append.u64); 384 cvmx_write_csr(CVMX_GMXX_TX_IFG(interface), gmx_tx_ifg.u64); 391 cvmx_write_csr(CVMX_GMXX_TX_OVR_BP(interface), gmx_tx_ovr_bp.u64); 403 cvmx_write_csr(CVMX_GMXX_HG2_CONTROL(interface), gmx_hg2_control.u64); 409 cvmx_write_csr(CVMX_GMXX_TX_XAUI_CT [all...] |
/freebsd-13-stable/sys/mips/cavium/octe/ |
H A D | ethernet-common.c | 81 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64 & ~1ull); 83 cvmx_write_csr(CVMX_GMXX_RXX_ADR_CTL(index, interface), control.u64); 85 cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM_EN(index, interface), 0); 87 cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM_EN(index, interface), 1); 89 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64); 152 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64 & ~1ull); 154 cvmx_write_csr(CVMX_GMXX_SMACX(index, interface), mac); 155 cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM0(index, interface), ptr[0]); 156 cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM1(index, interface), ptr[1]); 157 cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM [all...] |
H A D | ethernet-spi.c | 68 cvmx_write_csr(CVMX_SPXX_INT_REG(1), spx_int_reg.u64); 96 cvmx_write_csr(CVMX_STXX_INT_REG(1), stx_int_reg.u64); 119 cvmx_write_csr(CVMX_SPXX_INT_MSK(1), 0); 120 cvmx_write_csr(CVMX_STXX_INT_MSK(1), 0); 130 cvmx_write_csr(CVMX_SPXX_INT_REG(0), spx_int_reg.u64); 158 cvmx_write_csr(CVMX_STXX_INT_REG(0), stx_int_reg.u64); 181 cvmx_write_csr(CVMX_SPXX_INT_MSK(0), 0); 182 cvmx_write_csr(CVMX_STXX_INT_MSK(0), 0); 206 cvmx_write_csr(CVMX_SPXX_INT_MSK(interface), spxx_int_msk.u64); 217 cvmx_write_csr(CVMX_STXX_INT_MS [all...] |
/freebsd-13-stable/sys/mips/cavium/ |
H A D | octeon_mp.c | 53 cvmx_write_csr(CVMX_CIU_MBOX_SETX(cpuid), 1); 64 cvmx_write_csr(CVMX_CIU_MBOX_CLRX(PCPU_GET(cpuid)), action); 94 cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cpuid), 0xffffffff); 144 cvmx_write_csr(CVMX_CIU_PP_RST, (uint64_t)(cores_in_reset));
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