Lines Matching refs:cvmx_write_csr
122 cvmx_write_csr(CVMX_PEXP_NPEI_DMAX_IBUFF_SADDR(engine), dmax_ibuff_saddr.u64);
130 cvmx_write_csr(CVMX_DPI_DMAX_IBUFF_SADDR(engine), dpi_dmax_ibuff_saddr.u64);
136 cvmx_write_csr(CVMX_NPI_HIGHP_IBUFF_SADDR, address);
138 cvmx_write_csr(CVMX_NPI_LOWP_IBUFF_SADDR, address);
157 cvmx_write_csr(CVMX_PEXP_NPEI_DMA_CONTROL, dma_control.u64);
168 cvmx_write_csr(CVMX_PEXP_NPEI_DMA_PCIE_REQ_NUM, pcie_req_num.u64);
182 cvmx_write_csr(CVMX_DPI_ENGX_BUF(0), dpi_engx_buf.u64);
183 cvmx_write_csr(CVMX_DPI_ENGX_BUF(1), dpi_engx_buf.u64);
184 cvmx_write_csr(CVMX_DPI_ENGX_BUF(2), dpi_engx_buf.u64);
185 cvmx_write_csr(CVMX_DPI_ENGX_BUF(3), dpi_engx_buf.u64);
186 cvmx_write_csr(CVMX_DPI_ENGX_BUF(4), dpi_engx_buf.u64);
188 cvmx_write_csr(CVMX_DPI_ENGX_BUF(5), dpi_engx_buf.u64);
198 cvmx_write_csr(CVMX_DPI_DMA_CONTROL, dma_control.u64);
203 cvmx_write_csr(CVMX_DPI_DMA_ENGX_EN(5), dpi_dma_engx_en.u64);
206 cvmx_write_csr(CVMX_DPI_CTL, dpi_ctl.u64);
219 cvmx_write_csr(CVMX_NPI_DMA_CONTROL, dma_control.u64);
257 cvmx_write_csr(CVMX_PEXP_NPEI_DMA_CONTROL, dma_control.u64);
266 cvmx_write_csr(CVMX_DPI_DMA_CONTROL, dma_control.u64);
276 cvmx_write_csr(CVMX_NPI_DMA_CONTROL, dma_control.u64);
285 cvmx_write_csr(CVMX_PEXP_NPEI_DMAX_IBUFF_SADDR(engine), 0);
287 cvmx_write_csr(CVMX_DPI_DMAX_IBUFF_SADDR(engine), 0);
291 cvmx_write_csr(CVMX_NPI_HIGHP_IBUFF_SADDR, 0);
293 cvmx_write_csr(CVMX_NPI_LOWP_IBUFF_SADDR, 0);
356 cvmx_write_csr(CVMX_DPI_DMAX_DBELL(engine), cmd_count);
360 cvmx_write_csr(CVMX_NPI_HIGHP_DBELL, cmd_count);
362 cvmx_write_csr(CVMX_NPI_LOWP_DBELL, cmd_count);