Lines Matching refs:cvmx_write_csr
161 cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 1);
162 cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x200);
163 cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0x2000);
164 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64);
166 cvmx_write_csr(CVMX_ASXX_PRT_LOOP(interface), (1 << index) | tmp);
168 cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(interface), (1 << index) | tmp);
170 cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface), (1 << index) | tmp);
172 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64);
203 cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(interface), asx_tx.u64);
207 cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface), asx_rx.u64);
220 cvmx_write_csr(CVMX_GMXX_RXX_FRM_CTL(port, interface), frm_ctl.u64);
226 cvmx_write_csr(CVMX_GMXX_TXX_PAUSE_PKT_TIME(port, interface), 20000);
227 cvmx_write_csr(CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL(port, interface), 19000);
233 cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(port, interface), 26);
234 cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(port, interface), 26);
244 cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(port, interface), 4);
246 cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(port, interface), 7);
248 cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(port, interface), 0);
257 cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(port, interface), 16);
258 cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(port, interface), 16);
262 cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(port, interface), 24);
263 cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(port, interface), 24);
278 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(port, interface), gmx_cfg.u64);
352 cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface),
360 cvmx_write_csr(CVMX_PKO_REG_READ_IDX, queue);
366 cvmx_write_csr(CVMX_PKO_MEM_QUEUE_QOS, pko_mem_queue_qos.u64);
374 cvmx_write_csr(CVMX_GMXX_TX_OVR_BP(interface), gmx_tx_ovr_bp.u64);
381 cvmx_write_csr(CVMX_NPI_DBG_SELECT, interface*0x800 + index*0x100 + 0x880);
387 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), new_gmx_cfg.u64);
416 cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 50);
417 cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x40);
418 cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0);
422 cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 5);
423 cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x40);
424 cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0);
428 cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 1);
429 cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x200);
430 cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0x2000);
454 cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 1);
463 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), new_gmx_cfg.u64);
466 cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface),
473 cvmx_write_csr(CVMX_PKO_REG_READ_IDX, queue);
474 cvmx_write_csr(CVMX_PKO_MEM_QUEUE_QOS, pko_mem_queue_qos_save[i].u64);
478 cvmx_write_csr(CVMX_GMXX_TX_OVR_BP(interface), gmx_tx_ovr_bp_save.u64);
482 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), new_gmx_cfg.u64);
521 cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 1);
522 cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x200);
523 cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0x2000);
525 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64);
537 cvmx_write_csr(CVMX_ASXX_PRT_LOOP(interface), asxx_prt_loop.u64);
544 cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(interface), (1 << index) | tmp);
546 cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface), (1 << index) | tmp);
552 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64);