/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | LiveRegMatrix.cpp | 104 void LiveRegMatrix::assign(LiveInterval &VirtReg, unsigned PhysReg) { argument 105 LLVM_DEBUG(dbgs() << "assigning " << printReg(VirtReg.reg, TRI) << " to " 107 assert(!VRM->hasPhys(VirtReg.reg) && "Duplicate VirtReg assignment"); 108 VRM->assignVirt2Phys(VirtReg.reg, PhysReg); 111 TRI, VirtReg, PhysReg, [&](unsigned Unit, const LiveRange &Range) { 113 Matrix[Unit].unify(VirtReg, Range); 121 void LiveRegMatrix::unassign(LiveInterval &VirtReg) { argument 122 Register PhysReg = VRM->getPhys(VirtReg.reg); 123 LLVM_DEBUG(dbgs() << "unassigning " << printReg(VirtReg 146 checkRegMaskInterference(LiveInterval &VirtReg, unsigned PhysReg) argument 164 checkRegUnitInterference(LiveInterval &VirtReg, unsigned PhysReg) argument 186 checkInterference(LiveInterval &VirtReg, unsigned PhysReg) argument [all...] |
H A D | RegAllocBase.cpp | 89 while (LiveInterval *VirtReg = dequeue()) { 90 assert(!VRM->hasPhys(VirtReg->reg) && "Register already assigned"); 93 if (MRI->reg_nodbg_empty(VirtReg->reg)) { 94 LLVM_DEBUG(dbgs() << "Dropping unused " << *VirtReg << '\n'); 95 aboutToRemoveInterval(*VirtReg); 96 LIS->removeInterval(VirtReg->reg); 107 << TRI->getRegClassName(MRI->getRegClass(VirtReg->reg)) 108 << ':' << *VirtReg << " w=" << VirtReg->weight << '\n'); 113 unsigned AvailablePhysReg = selectOrSplit(*VirtReg, SplitVReg [all...] |
H A D | RegAllocBasic.cpp | 103 Register selectOrSplit(LiveInterval &VirtReg, 117 bool spillInterferences(LiveInterval &VirtReg, Register PhysReg, 144 bool RABasic::LRE_CanEraseVirtReg(unsigned VirtReg) { argument 145 LiveInterval &LI = LIS->getInterval(VirtReg); 146 if (VRM->hasPhys(VirtReg)) { 154 // dump will show the right state for that VirtReg. 159 void RABasic::LRE_WillShrinkVirtReg(unsigned VirtReg) { argument 160 if (!VRM->hasPhys(VirtReg)) 164 LiveInterval &LI = LIS->getInterval(VirtReg); 202 // that interfere with VirtReg 204 spillInterferences(LiveInterval &VirtReg, Register PhysReg, SmallVectorImpl<Register> &SplitVRegs) argument 256 selectOrSplit(LiveInterval &VirtReg, SmallVectorImpl<Register> &SplitVRegs) argument [all...] |
H A D | AllocationOrder.cpp | 29 AllocationOrder::AllocationOrder(unsigned VirtReg, argument 36 Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg)); 37 if (TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM, Matrix))
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H A D | RegAllocFast.cpp | 86 Register VirtReg; ///< Virtual register number. member in struct:__anon3551::RegAllocFast::LiveReg 91 explicit LiveReg(Register VirtReg) : VirtReg(VirtReg) {} argument 94 return Register::virtReg2Index(VirtReg); 193 void killVirtReg(Register VirtReg); 195 void spillVirtReg(MachineBasicBlock::iterator MI, Register VirtReg); 203 LiveRegMap::iterator findLiveVirtReg(Register VirtReg) { argument 204 return LiveVirtRegs.find(Register::virtReg2Index(VirtReg)); 207 LiveRegMap::const_iterator findLiveVirtReg(Register VirtReg) cons 248 getStackSpaceFor(Register VirtReg) argument 267 mayLiveOut(Register VirtReg) argument 296 mayLiveIn(Register VirtReg) argument 315 spill(MachineBasicBlock::iterator Before, Register VirtReg, MCPhysReg AssignedReg, bool Kill) argument 343 reload(MachineBasicBlock::iterator Before, Register VirtReg, MCPhysReg PhysReg) argument 397 killVirtReg(Register VirtReg) argument 407 spillVirtReg(MachineBasicBlock::iterator MI, Register VirtReg) argument 612 Register VirtReg = LR.VirtReg; local 663 const Register VirtReg = LR.VirtReg; local 754 Register VirtReg = MO.getReg(); local 778 defineVirtReg(MachineInstr &MI, unsigned OpNum, Register VirtReg, Register Hint) argument 809 reloadVirtReg(MachineInstr &MI, unsigned OpNum, Register VirtReg, Register Hint) argument [all...] |
H A D | RegAllocGreedy.cpp | 249 LiveRangeStage getStage(const LiveInterval &VirtReg) const { 250 return ExtraRegInfo[VirtReg.reg].Stage; 253 void setStage(const LiveInterval &VirtReg, LiveRangeStage Stage) { argument 255 ExtraRegInfo[VirtReg.reg].Stage = Stage; 459 Register canReassign(LiveInterval &VirtReg, Register PrevReg); 463 bool canEvictInterferenceInRange(LiveInterval &VirtReg, Register oPhysReg, 467 LiveInterval &VirtReg, SlotIndex Start, 471 bool mayRecolorAllInterferences(unsigned PhysReg, LiveInterval &VirtReg, 484 unsigned calculateRegionSplitCost(LiveInterval &VirtReg, 490 unsigned doRegionSplit(LiveInterval &VirtReg, unsigne 629 LRE_CanEraseVirtReg(unsigned VirtReg) argument 644 LRE_WillShrinkVirtReg(unsigned VirtReg) argument 755 tryAssign(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<Register> &NewVRegs, const SmallVirtRegSet &FixedRegisters) argument 802 canReassign(LiveInterval &VirtReg, Register PrevReg) argument 865 canEvictInterference(LiveInterval &VirtReg, Register PhysReg, bool IsHint, EvictionCost &MaxCost, const SmallVirtRegSet &FixedRegisters) argument 962 canEvictInterferenceInRange(LiveInterval &VirtReg, Register PhysReg, SlotIndex Start, SlotIndex End, EvictionCost &MaxCost) argument 1015 getCheapestEvicteeWeight(const AllocationOrder &Order, LiveInterval &VirtReg, SlotIndex Start, SlotIndex End, float *BestEvictweight) argument 1041 evictInterference(LiveInterval &VirtReg, Register PhysReg, SmallVectorImpl<Register> &NewVRegs) argument 1099 tryEvict(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<Register> &NewVRegs, unsigned CostPerUseLimit, const SmallVirtRegSet &FixedRegisters) argument 1811 tryRegionSplit(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<Register> &NewVRegs) argument 1854 calculateRegionSplitCost(LiveInterval &VirtReg, AllocationOrder &Order, BlockFrequency &BestCost, unsigned &NumCands, bool IgnoreCSR, bool *CanCauseEvictionChain) argument 1954 doRegionSplit(LiveInterval &VirtReg, unsigned BestCand, bool HasCompact, SmallVectorImpl<Register> &NewVRegs) argument 2001 tryBlockSplit(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<Register> &NewVRegs) argument 2068 tryInstructionSplit(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<Register> &NewVRegs) argument 2211 tryLocalSplit(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl<Register> &NewVRegs) argument [all...] |
H A D | LiveIntervalUnion.cpp | 29 void LiveIntervalUnion::unify(LiveInterval &VirtReg, const LiveRange &Range) { argument 40 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); 50 SegPos.insert(RegEnd->start, RegEnd->end, &VirtReg); 52 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); 56 void LiveIntervalUnion::extract(LiveInterval &VirtReg, const LiveRange &Range) { argument 67 assert(SegPos.value() == &VirtReg && "Inconsistent LiveInterval"); 104 bool LiveIntervalUnion::Query::isSeenInterference(LiveInterval *VirtReg) const { 105 return is_contained(InterferingVRegs, VirtReg);
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H A D | RegisterCoalescer.h | 62 CoalescerPair(unsigned VirtReg, unsigned PhysReg, argument 64 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg) {}
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H A D | AllocationOrder.h | 40 /// Create a new AllocationOrder for VirtReg. 41 /// @param VirtReg Virtual register to allocate for. 44 AllocationOrder(unsigned VirtReg,
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H A D | VirtRegMap.cpp | 101 bool VirtRegMap::hasPreferredPhys(Register VirtReg) { argument 102 Register Hint = MRI->getSimpleHint(VirtReg); 107 return getPhys(VirtReg) == Hint; 110 bool VirtRegMap::hasKnownPreference(Register VirtReg) { argument 111 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(VirtReg); 314 Register VirtReg = Register::index2VirtReg(Idx); local 315 if (MRI->reg_nodbg_empty(VirtReg)) 317 LiveInterval &LI = LIS->getInterval(VirtReg); 322 Register PhysReg = VRM->getPhys(VirtReg); 517 Register VirtReg local [all...] |
H A D | RegAllocBase.h | 94 /// enqueue - Add VirtReg to the priority queue of unassigned registers. 104 virtual Register selectOrSplit(LiveInterval &VirtReg,
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H A D | TargetRegisterInfo.cpp | 68 const MachineFunction &MF, const LiveInterval &VirtReg) const { 71 MachineInstr *MI = MRI.getUniqueVRegDef(VirtReg.reg); 73 VirtReg.size() > HugeSizeForSplit) 403 Register VirtReg, ArrayRef<MCPhysReg> Order, 408 MRI.getRegAllocationHints(VirtReg); 428 // Check that Phys is a valid hint in VirtReg's register class. 434 // from VirtReg's register class if they aren't in the allocation order. The
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H A D | LiveDebugVariables.cpp | 422 /// Find the EC leader for VirtReg or null. 423 UserValue *lookupVirtReg(Register VirtReg); 473 void mapVirtReg(Register VirtReg, UserValue *EC); 596 void LDVImpl::mapVirtReg(Register VirtReg, UserValue *EC) { argument 597 assert(Register::isVirtualRegister(VirtReg) && "Only map VirtRegs"); 598 UserValue *&Leader = virtRegToEqClass[VirtReg]; 602 UserValue *LDVImpl::lookupVirtReg(Register VirtReg) { argument 603 if (UserValue *UV = virtRegToEqClass.lookup(VirtReg)) 1189 Register VirtReg = Loc.getReg(); local 1190 if (VRM.isAssignedReg(VirtReg) [all...] |
H A D | PHIElimination.cpp | 165 unsigned VirtReg = Register::index2VirtReg(Index); local 166 MachineInstr *DefMI = MRI->getVRegDef(VirtReg); 169 LiveVariables::VarInfo &VI = LV->getVarInfo(VirtReg); 249 /// Return true if all defs of VirtReg are implicit-defs. 251 static bool isImplicitlyDefined(unsigned VirtReg, argument 253 for (MachineInstr &DI : MRI.def_instructions(VirtReg))
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H A D | InlineSpiller.cpp | 556 bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg, MachineInstr &MI) { argument 559 VirtRegInfo RI = AnalyzeVirtRegInBundle(MI, VirtReg.reg, &Ops); 565 VNInfo *ParentVNI = VirtReg.getVNInfoAt(UseIdx.getBaseIndex()); 571 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg) 587 markValueUsed(&VirtReg, ParentVNI); 592 // If the instruction also writes VirtReg.reg, it had better not require the 595 markValueUsed(&VirtReg, ParentVNI); 611 if (!canGuaranteeAssignmentAfterRemat(VirtReg.reg, MI)) { 612 markValueUsed(&VirtReg, ParentVNI); 636 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg [all...] |
H A D | MachineBasicBlock.cpp | 547 Register VirtReg = I->getOperand(0).getReg(); 548 if (!MRI.constrainRegClass(VirtReg, RC)) 550 return VirtReg; 554 Register VirtReg = MRI.createVirtualRegister(RC); 555 BuildMI(*this, I, DebugLoc(), TII.get(TargetOpcode::COPY), VirtReg) 559 return VirtReg;
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/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | LiveRegMatrix.h | 99 /// VirtReg is live across a call, and PhysReg isn't call-preserved. 103 /// Check for interference before assigning VirtReg to PhysReg. 104 /// If this function returns IK_Free, it is legal to assign(VirtReg, PhysReg). 107 InterferenceKind checkInterference(LiveInterval &VirtReg, unsigned PhysReg); 116 /// Assign VirtReg to PhysReg. 117 /// This will mark VirtReg's live range as occupied in the LiveRegMatrix and 119 void assign(LiveInterval &VirtReg, unsigned PhysReg); 121 /// Unassign VirtReg from its PhysReg. 122 /// Assuming that VirtReg was previously assigned to a PhysReg, this undoes 124 void unassign(LiveInterval &VirtReg); [all...] |
H A D | VirtRegMap.h | 125 /// returns true if VirtReg is assigned to its preferred physreg. 126 bool hasPreferredPhys(Register VirtReg); 128 /// returns true if VirtReg has a known preferred register. 129 /// This returns false if VirtReg has a preference that is a virtual 131 bool hasKnownPreference(Register VirtReg); 143 /// getOriginal - Return the original virtual register that VirtReg descends 147 unsigned getOriginal(unsigned VirtReg) const { 148 unsigned Orig = getPreSplitReg(VirtReg); 149 return Orig ? Orig : VirtReg;
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H A D | LiveIntervalUnion.h | 91 void unify(LiveInterval &VirtReg, const LiveRange &Range); 94 void extract(LiveInterval &VirtReg, const LiveRange &Range); 157 bool isSeenInterference(LiveInterval *VirtReg) const;
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H A D | ScheduleDAGInstrs.h | 53 unsigned VirtReg; member in struct:llvm::VReg2SUnit 58 : VirtReg(VReg), LaneMask(LaneMask), SU(SU) {} 61 return Register::virtReg2Index(VirtReg);
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H A D | RegisterPressure.h | 535 bool hasUntiedDef(unsigned VirtReg) const { 536 return UntiedDefs.count(VirtReg);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIPreAllocateWWMRegs.cpp | 128 const Register VirtReg = MO.getReg(); local 129 if (Register::isPhysicalRegister(VirtReg)) 132 if (!VRM->hasPhys(VirtReg)) 135 Register PhysReg = VRM->getPhys(VirtReg);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZRegisterInfo.cpp | 77 Register VirtReg, ArrayRef<MCPhysReg> Order, 85 VirtReg, Order, Hints, MF, VRM, Matrix); 90 for (auto &Use : MRI->reg_nodbg_instructions(VirtReg)) 95 if (VirtReg == Use.getOperand(0).getReg()) { 100 } else if (VirtReg == Use.getOperand(1).getReg()) { 103 } else if (VirtReg == Use.getOperand(2).getReg() && 119 MRI->getRegClass(VirtReg)); 133 if (MRI->getRegClass(VirtReg) == &SystemZ::GRX32BitRegClass) { 136 Worklist.push_back(VirtReg); 145 // VirtReg 76 getRegAllocationHints( Register VirtReg, ArrayRef<MCPhysReg> Order, SmallVectorImpl<MCPhysReg> &Hints, const MachineFunction &MF, const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const argument [all...] |
H A D | SystemZRegisterInfo.h | 61 bool getRegAllocationHints(Register VirtReg, ArrayRef<MCPhysReg> Order,
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMBaseRegisterInfo.h | 154 bool getRegAllocationHints(Register VirtReg, ArrayRef<MCPhysReg> Order,
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