Lines Matching refs:VirtReg
249 LiveRangeStage getStage(const LiveInterval &VirtReg) const {
250 return ExtraRegInfo[VirtReg.reg].Stage;
253 void setStage(const LiveInterval &VirtReg, LiveRangeStage Stage) {
255 ExtraRegInfo[VirtReg.reg].Stage = Stage;
459 Register canReassign(LiveInterval &VirtReg, Register PrevReg);
463 bool canEvictInterferenceInRange(LiveInterval &VirtReg, Register oPhysReg,
467 LiveInterval &VirtReg, SlotIndex Start,
471 bool mayRecolorAllInterferences(unsigned PhysReg, LiveInterval &VirtReg,
484 unsigned calculateRegionSplitCost(LiveInterval &VirtReg,
490 unsigned doRegionSplit(LiveInterval &VirtReg, unsigned BestCand,
495 unsigned tryAssignCSRFirstTime(LiveInterval &VirtReg, AllocationOrder &Order,
629 bool RAGreedy::LRE_CanEraseVirtReg(unsigned VirtReg) {
630 LiveInterval &LI = LIS->getInterval(VirtReg);
631 if (VRM->hasPhys(VirtReg)) {
639 // dump will show the right state for that VirtReg.
644 void RAGreedy::LRE_WillShrinkVirtReg(unsigned VirtReg) {
645 if (!VRM->hasPhys(VirtReg))
649 LiveInterval &LI = LIS->getInterval(VirtReg);
754 /// tryAssign - Try to assign VirtReg to an available register.
755 Register RAGreedy::tryAssign(LiveInterval &VirtReg,
762 if (!Matrix->checkInterference(VirtReg, PhysReg))
771 if (Register Hint = MRI->getSimpleHint(VirtReg.reg))
776 if (canEvictInterference(VirtReg, Hint, true, MaxCost, FixedRegisters)) {
777 evictInterference(VirtReg, Hint, NewVRegs);
782 SetOfBrokenHints.insert(&VirtReg);
794 Register CheapReg = tryEvict(VirtReg, Order, NewVRegs, Cost, FixedRegisters);
802 Register RAGreedy::canReassign(LiveInterval &VirtReg, Register PrevReg) {
803 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo, Matrix);
812 LiveIntervalUnion::Query subQ(VirtReg, Matrix->getLiveUnions()[*Units]);
821 LLVM_DEBUG(dbgs() << "can reassign: " << VirtReg << " from "
856 /// canEvictInterference - Return true if all interferences between VirtReg and
859 /// @param VirtReg Live range that is about to be assigned.
861 /// @param IsHint True when PhysReg is VirtReg's preferred register.
865 bool RAGreedy::canEvictInterference(LiveInterval &VirtReg, Register PhysReg,
869 if (Matrix->checkInterference(VirtReg, PhysReg) > LiveRegMatrix::IK_VirtReg)
872 bool IsLocal = LIS->intervalIsInOneMBB(VirtReg);
874 // Find VirtReg's cascade number. This will be unassigned if VirtReg was never
881 unsigned Cascade = ExtraRegInfo[VirtReg.reg].Cascade;
887 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units);
913 bool Urgent = !VirtReg.isSpillable() &&
915 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(VirtReg.reg)) <
937 if (!shouldEvict(VirtReg, IsHint, *Intf, BreaksHint))
952 /// Return true if all interferences between VirtReg and PhysReg between
955 /// \param VirtReg Live range that is about to be assigned.
962 bool RAGreedy::canEvictInterferenceInRange(LiveInterval &VirtReg,
969 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units);
1009 /// \param VirtReg Live range that is about to be assigned.
1016 LiveInterval &VirtReg,
1021 BestEvictCost.MaxWeight = VirtReg.weight;
1027 if (!canEvictInterferenceInRange(VirtReg, PhysReg, Start, End,
1038 /// evictInterference - Evict any interferring registers that prevent VirtReg
1041 void RAGreedy::evictInterference(LiveInterval &VirtReg, Register PhysReg,
1043 // Make sure that VirtReg has a cascade number, and assign that cascade
1046 unsigned Cascade = ExtraRegInfo[VirtReg.reg].Cascade;
1048 Cascade = ExtraRegInfo[VirtReg.reg].Cascade = NextCascade++;
1056 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units);
1069 // The same VirtReg may be present in multiple RegUnits. Skip duplicates.
1073 LastEvicted.addEviction(PhysReg, VirtReg.reg, Intf->reg);
1077 VirtReg.isSpillable() < Intf->isSpillable()) &&
1096 /// @param VirtReg Currently unassigned virtual register.
1098 /// @return Physreg to assign VirtReg, or 0.
1099 unsigned RAGreedy::tryEvict(LiveInterval &VirtReg,
1117 BestCost.MaxWeight = VirtReg.weight;
1120 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg.reg);
1151 if (!canEvictInterference(VirtReg, PhysReg, false, BestCost,
1166 evictInterference(VirtReg, BestPhys, NewVRegs);
1811 unsigned RAGreedy::tryRegionSplit(LiveInterval &VirtReg, AllocationOrder &Order,
1813 if (!TRI->shouldRegionSplitForVirtReg(*MF, VirtReg))
1835 calculateRegionSplitCost(VirtReg, Order, BestCost, NumCands,
1851 return doRegionSplit(VirtReg, BestCand, HasCompact, NewVRegs);
1854 unsigned RAGreedy::calculateRegionSplitCost(LiveInterval &VirtReg,
1945 << printReg(VirtReg.reg, TRI) << " may ");
1954 unsigned RAGreedy::doRegionSplit(LiveInterval &VirtReg, unsigned BestCand,
1959 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this, &DeadRemats);
2001 unsigned RAGreedy::tryBlockSplit(LiveInterval &VirtReg, AllocationOrder &Order,
2003 assert(&SA->getParent() == &VirtReg && "Live range wasn't analyzed");
2004 Register Reg = VirtReg.reg;
2006 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this, &DeadRemats);
2068 RAGreedy::tryInstructionSplit(LiveInterval &VirtReg, AllocationOrder &Order,
2070 const TargetRegisterClass *CurRC = MRI->getRegClass(VirtReg.reg);
2077 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this, &DeadRemats);
2098 getNumAllocatableRegsForConstraints(MI, VirtReg.reg, SuperRC, TII,
2116 DebugVars->splitRegister(VirtReg.reg, LREdit.regs(), *LIS);
2154 // We know that VirtReg is a continuous interval from FirstInstr to
2208 /// tryLocalSplit - Try to split VirtReg into smaller intervals inside its only
2211 unsigned RAGreedy::tryLocalSplit(LiveInterval &VirtReg, AllocationOrder &Order,
2239 // If VirtReg is live across any register mask operands, compute a list of
2242 if (Matrix->checkRegMaskInterference(VirtReg)) {
2246 // Constrain to VirtReg's live range.
2288 bool ProgressRequired = getStage(VirtReg) >= RS_Split2;
2307 if (Matrix->checkRegMaskInterference(VirtReg, PhysReg))
2403 LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this, &DeadRemats);
2412 DebugVars->splitRegister(VirtReg.reg, LREdit.regs(), *LIS);
2439 /// trySplit - Try to split VirtReg or one of its interferences, making it
2441 /// @return Physreg when VirtReg may be assigned and/or new NewVRegs.
2442 unsigned RAGreedy::trySplit(LiveInterval &VirtReg, AllocationOrder &Order,
2446 if (getStage(VirtReg) >= RS_Spill)
2450 if (LIS->intervalIsInOneMBB(VirtReg)) {
2453 SA->analyze(&VirtReg);
2454 Register PhysReg = tryLocalSplit(VirtReg, Order, NewVRegs);
2457 return tryInstructionSplit(VirtReg, Order, NewVRegs);
2463 SA->analyze(&VirtReg);
2470 // VirtReg has changed, so all cached queries are invalid.
2472 if (Register PhysReg = tryAssign(VirtReg, Order, NewVRegs, FixedRegisters))
2479 if (getStage(VirtReg) < RS_Split2) {
2480 unsigned PhysReg = tryRegionSplit(VirtReg, Order, NewVRegs);
2486 return tryBlockSplit(VirtReg, Order, NewVRegs);
2503 /// interfere with \p VirtReg on \p PhysReg (or one of its aliases) may be
2507 /// for \p VirtReg.
2511 RAGreedy::mayRecolorAllInterferences(unsigned PhysReg, LiveInterval &VirtReg,
2514 const TargetRegisterClass *CurRC = MRI->getRegClass(VirtReg.reg);
2517 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units);
2528 // If Intf is done and sit on the same register class as VirtReg,
2529 // it would not be recolorable as it is in the same state as VirtReg.
2530 // However, if VirtReg has tied defs and Intf doesn't, then
2534 !(hasTiedDef(MRI, VirtReg.reg) && !hasTiedDef(MRI, Intf->reg))) ||
2546 /// tryLastChanceRecoloring - Try to assign a color to \p VirtReg by recoloring
2548 /// Last chance recoloring chooses a color for \p VirtReg and recolors every
2577 /// \p Order defines the preferred allocation order for \p VirtReg.
2583 /// \return a physical register that can be used for VirtReg or ~0u if none
2585 unsigned RAGreedy::tryLastChanceRecoloring(LiveInterval &VirtReg,
2590 LLVM_DEBUG(dbgs() << "Try last chance recoloring for " << VirtReg << '\n');
2592 assert((getStage(VirtReg) >= RS_Done || !VirtReg.isSpillable()) &&
2609 // Mark VirtReg as fixed, i.e., it will not be recolored pass this point in
2611 assert(!FixedRegisters.count(VirtReg.reg));
2612 FixedRegisters.insert(VirtReg.reg);
2617 LLVM_DEBUG(dbgs() << "Try to assign: " << VirtReg << " to "
2624 if (Matrix->checkInterference(VirtReg, PhysReg) >
2634 if (!mayRecolorAllInterferences(PhysReg, VirtReg, RecoloringCandidates,
2641 // with VirtReg on PhysReg (or one of its aliases).
2658 // Do as if VirtReg was assigned to PhysReg so that the underlying
2661 Matrix->assign(VirtReg, PhysReg);
2673 // I.e., VirtReg must be unassigned.
2674 Matrix->unassign(VirtReg);
2678 LLVM_DEBUG(dbgs() << "Fail to assign: " << VirtReg << " to "
2683 Matrix->unassign(VirtReg);
2755 Register RAGreedy::selectOrSplit(LiveInterval &VirtReg,
2760 Register Reg = selectOrSplitImpl(VirtReg, NewVRegs, FixedRegisters);
2785 unsigned RAGreedy::tryAssignCSRFirstTime(LiveInterval &VirtReg,
2790 if (getStage(VirtReg) == RS_Spill && VirtReg.isSpillable()) {
2793 SA->analyze(&VirtReg);
2802 if (getStage(VirtReg) < RS_Split) {
2805 SA->analyze(&VirtReg);
2808 unsigned BestCand = calculateRegionSplitCost(VirtReg, Order, BestCost,
2815 doRegionSplit(VirtReg, BestCand, false/*HasCompact*/, NewVRegs);
2888 /// Using the register assigned to \p VirtReg, try to recolor
2889 /// all the live ranges that are copy-related with \p VirtReg.
2896 void RAGreedy::tryHintRecoloring(LiveInterval &VirtReg) {
2903 unsigned Reg = VirtReg.reg;
3016 Register RAGreedy::selectOrSplitImpl(LiveInterval &VirtReg,
3022 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo, Matrix);
3023 if (unsigned PhysReg = tryAssign(VirtReg, Order, NewVRegs, FixedRegisters)) {
3024 // If VirtReg got an assignment, the eviction info is no longre relevant.
3025 LastEvicted.clearEvicteeInfo(VirtReg.reg);
3031 Register CSRReg = tryAssignCSRFirstTime(VirtReg, Order, PhysReg,
3041 LiveRangeStage Stage = getStage(VirtReg);
3043 << ExtraRegInfo[VirtReg.reg].Cascade << '\n');
3050 tryEvict(VirtReg, Order, NewVRegs, CostPerUseLimit,
3052 Register Hint = MRI->getSimpleHint(VirtReg.reg);
3053 // If VirtReg has a hint and that hint is broken record this
3059 SetOfBrokenHints.insert(&VirtReg);
3060 // If VirtReg eviction someone, the eviction info for it as an evictee is
3062 LastEvicted.clearEvicteeInfo(VirtReg.reg);
3072 setStage(VirtReg, RS_Split);
3074 NewVRegs.push_back(VirtReg.reg);
3079 // Try splitting VirtReg or interferences.
3081 Register PhysReg = trySplit(VirtReg, Order, NewVRegs, FixedRegisters);
3083 // If VirtReg got split, the eviction info is no longer relevant.
3084 LastEvicted.clearEvicteeInfo(VirtReg.reg);
3091 if (Stage >= RS_Done || !VirtReg.isSpillable())
3092 return tryLastChanceRecoloring(VirtReg, Order, NewVRegs, FixedRegisters,
3095 // Finally spill VirtReg itself.
3096 if (EnableDeferredSpilling && getStage(VirtReg) < RS_Memory) {
3101 setStage(VirtReg, RS_Memory);
3103 NewVRegs.push_back(VirtReg.reg);
3107 LiveRangeEdit LRE(&VirtReg, NewVRegs, *MF, *LIS, VRM, this, &DeadRemats);
3114 DebugVars->splitRegister(VirtReg.reg, LRE.regs(), *LIS);