1//===-- llvm/CodeGen/AllocationOrder.cpp - Allocation Order ---------------===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file implements an allocation order for virtual registers. 10// 11// The preferred allocation order for a virtual register depends on allocation 12// hints and target hooks. The AllocationOrder class encapsulates all of that. 13// 14//===----------------------------------------------------------------------===// 15 16#include "AllocationOrder.h" 17#include "llvm/CodeGen/MachineFunction.h" 18#include "llvm/CodeGen/MachineRegisterInfo.h" 19#include "llvm/CodeGen/RegisterClassInfo.h" 20#include "llvm/CodeGen/VirtRegMap.h" 21#include "llvm/Support/Debug.h" 22#include "llvm/Support/raw_ostream.h" 23 24using namespace llvm; 25 26#define DEBUG_TYPE "regalloc" 27 28// Compare VirtRegMap::getRegAllocPref(). 29AllocationOrder::AllocationOrder(unsigned VirtReg, 30 const VirtRegMap &VRM, 31 const RegisterClassInfo &RegClassInfo, 32 const LiveRegMatrix *Matrix) 33 : Pos(0), HardHints(false) { 34 const MachineFunction &MF = VRM.getMachineFunction(); 35 const TargetRegisterInfo *TRI = &VRM.getTargetRegInfo(); 36 Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg)); 37 if (TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM, Matrix)) 38 HardHints = true; 39 rewind(); 40 41 LLVM_DEBUG({ 42 if (!Hints.empty()) { 43 dbgs() << "hints:"; 44 for (unsigned I = 0, E = Hints.size(); I != E; ++I) 45 dbgs() << ' ' << printReg(Hints[I], TRI); 46 dbgs() << '\n'; 47 } 48 }); 49#ifndef NDEBUG 50 for (unsigned I = 0, E = Hints.size(); I != E; ++I) 51 assert(is_contained(Order, Hints[I]) && 52 "Target hint is outside allocation order."); 53#endif 54} 55