Searched refs:SrcOp (Results 1 - 25 of 35) sorted by relevance

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/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DMachineIRBuilder.h118 class SrcOp { class in namespace:llvm
128 SrcOp(Register R) : Reg(R), Ty(SrcType::Ty_Reg) {} function in class:llvm::SrcOp
129 SrcOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(SrcType::Ty_Reg) {} function in class:llvm::SrcOp
130 SrcOp(const MachineInstrBuilder &MIB) : SrcMIB(MIB), Ty(SrcType::Ty_MIB) {} function in class:llvm::SrcOp
131 SrcOp(const CmpInst::Predicate P) : Pred(P), Ty(SrcType::Ty_Predicate) {} function in class:llvm::SrcOp
135 SrcOp(unsigned) = delete;
136 SrcOp(int) = delete;
137 SrcOp(uint64_t V) : Imm(V), Ty(SrcType::Ty_Imm) {} function in class:llvm::SrcOp
138 SrcOp(int64_t V) : Imm(V), Ty(SrcType::Ty_Imm) {} function in class:llvm::SrcOp
167 llvm_unreachable("Unrecognised SrcOp
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H A DCSEMIRBuilder.h63 void profileSrcOp(const SrcOp &Op, GISelInstProfileBuilder &B) const;
65 void profileSrcOps(ArrayRef<SrcOp> Ops, GISelInstProfileBuilder &B) const {
66 for (const SrcOp &Op : Ops)
73 ArrayRef<SrcOp> SrcOps, Optional<unsigned> Flags,
95 ArrayRef<SrcOp> SrcOps,
H A DConstantFoldingMIRBuilder.h29 ArrayRef<SrcOp> SrcOps,
50 const SrcOp &Src0 = SrcOps[0];
51 const SrcOp &Src1 = SrcOps[1];
61 const SrcOp &Src0 = SrcOps[0];
62 const SrcOp &Src1 = SrcOps[1];
H A DLegalizationArtifactCombiner.h523 unsigned SrcOp = SrcDef->getOpcode(); local
524 if (isArtifactCast(SrcOp)) {
525 ConvertOp = SrcOp;
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DMachineIRBuilder.cpp127 const SrcOp &Size,
178 const SrcOp &Op0,
179 const SrcOp &Op1) {
204 const SrcOp &Op0,
234 const SrcOp &Op) {
323 const SrcOp &Addr,
330 const SrcOp &Addr,
343 const DstOp &Dst, const SrcOp &BasePtr,
359 MachineInstrBuilder MachineIRBuilder::buildStore(const SrcOp &Val,
360 const SrcOp
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H A DCSEMIRBuilder.cpp70 void CSEMIRBuilder::profileSrcOp(const SrcOp &Op,
73 case SrcOp::SrcType::Ty_Predicate:
91 ArrayRef<SrcOp> SrcOps,
139 ArrayRef<SrcOp> SrcOps,
169 const SrcOp &Src0 = SrcOps[0];
170 const SrcOp &Src1 = SrcOps[1];
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Linker/
H A DIRMover.cpp1231 MDNode *SrcOp = SrcModFlags->getOperand(I); local
1233 mdconst::extract<ConstantInt>(SrcOp->getOperand(0));
1234 MDString *ID = cast<MDString>(SrcOp->getOperand(1));
1244 if (Requirements.insert(cast<MDNode>(SrcOp->getOperand(2)))) {
1245 DstModFlags->addOperand(SrcOp);
1252 Flags[ID] = std::make_pair(SrcOp, DstModFlags->getNumOperands());
1253 DstModFlags->addOperand(SrcOp);
1263 DstModFlags->setOperand(DstIndex, SrcOp);
1264 Flags[ID].first = SrcOp;
1271 SrcOp
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonRDFOpt.cpp139 const MachineOperand &SrcOp = MI->getOperand(1); local
141 DFG.makeRegRef(SrcOp.getReg(), SrcOp.getSubReg()));
H A DHexagonExpandCondsets.cpp213 MachineInstr *genCondTfrFor(MachineOperand &SrcOp,
619 /// Generate a conditional transfer, copying the value SrcOp to the
623 MachineInstr *HexagonExpandCondsets::genCondTfrFor(MachineOperand &SrcOp, argument
627 MachineInstr *MI = SrcOp.getParent();
637 unsigned Opc = getCondTfrOpcode(SrcOp, PredSense);
642 if (SrcOp.isReg()) {
643 unsigned SrcState = getRegState(SrcOp);
644 if (RegisterRef(SrcOp) == RegisterRef(DstR, DstSR))
649 .addReg(SrcOp.getReg(), SrcState, SrcOp
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H A DHexagonFrameLowering.cpp2454 MachineOperand &SrcOp = SI.getOperand(2); local
2456 HexagonBlockRanges::RegisterRef SrcRR = { SrcOp.getReg(),
2457 SrcOp.getSubReg() };
2479 .add(SrcOp);
2486 if (unsigned SR = SrcOp.getSubReg())
2487 SrcOp.setReg(HRI.getSubReg(FoundR, SR));
2489 SrcOp.setReg(FoundR);
2490 SrcOp.setSubReg(0);
2492 SrcOp.setIsKill(false);
H A DHexagonInstrInfo.cpp1122 const MachineOperand &SrcOp = MI.getOperand(2); local
1123 assert(SrcOp.getSubReg() == 0);
1133 .addReg(SrcOp.getReg(), getRegState(SrcOp))
/freebsd-13-stable/contrib/llvm-project/llvm/utils/TableGen/
H A DCodeGenInstruction.cpp291 std::pair<unsigned,unsigned> SrcOp = (FirstIsDest ? RHSOp : LHSOp); local
299 if (SrcOp.first < Ops.NumDefs)
307 if (!Ops[SrcOp.first].Constraints[SrcOp.second].isNone())
325 Ops[SrcOp.first].Constraints[SrcOp.second] = NewConstraint;
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSILowerControlFlow.cpp540 for (const auto &SrcOp : Def->explicit_operands())
541 if (SrcOp.isReg() && SrcOp.isUse() &&
542 (Register::isVirtualRegister(SrcOp.getReg()) || SrcOp.getReg() == Exec))
543 Src.push_back(SrcOp);
H A DSIPeepholeSDWA.cpp163 const MachineOperand *SrcOp) const;
331 const MachineOperand *SrcOp) const {
333 const auto *MI = SrcOp->getParent();
334 if (TII->getNamedOperand(*MI, AMDGPU::OpName::src0) == SrcOp) {
338 } else if (TII->getNamedOperand(*MI, AMDGPU::OpName::src1) == SrcOp) {
H A DAMDGPULegalizerInfo.cpp3594 MachineOperand &SrcOp = MI.getOperand(I);
3595 if (!SrcOp.isReg())
3598 Register AddrReg = SrcOp.getReg();
3633 MachineOperand &SrcOp = MI.getOperand(DimIdx + I);
3634 if (SrcOp.isReg()) {
3635 AddrRegs.push_back(SrcOp.getReg());
3636 assert(B.getMRI()->getType(SrcOp.getReg()) == S32);
3656 MachineOperand &SrcOp = MI.getOperand(DimIdx + I);
3657 if (SrcOp.isReg())
3838 MachineOperand &SrcOp
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H A DSIInstrInfo.cpp1620 const MachineOperand &SrcOp = MI.getOperand(1); local
1622 assert(!SrcOp.isFPImm());
1623 if (SrcOp.isImm()) {
1624 APInt Imm(64, SrcOp.getImm());
1632 assert(SrcOp.isReg());
1634 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub0))
1637 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub1))
1793 const MachineOperand &SrcOp = MI.getOperand(I); local
1794 assert(!SrcOp.isFPImm());
1795 if (SrcOp
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H A DAMDGPUInstructionSelector.cpp1560 MachineOperand &SrcOp = MI.getOperand(VAddrIdx + i); local
1561 if (SrcOp.isReg()) {
1562 assert(SrcOp.getReg() != 0);
1563 MIB.addReg(SrcOp.getReg());
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerCombiner.cpp39 SmallVector<SrcOp, 2> SrcOps; ///< Source registers.
41 std::initializer_list<SrcOp> SrcOps)
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineVerifier.cpp1255 const MachineOperand &SrcOp = MI->getOperand(1); local
1256 if (!SrcOp.isReg()) {
1268 unsigned SrcSize = MRI->getType(SrcOp.getReg()).getSizeInBits();
1277 const MachineOperand &SrcOp = MI->getOperand(2); local
1278 if (!SrcOp.isReg()) {
1290 unsigned SrcSize = MRI->getType(SrcOp.getReg()).getSizeInBits();
1510 const MachineOperand &SrcOp = MI->getOperand(1); local
1512 LLT SrcTy = MRI->getType(SrcOp.getReg());
1523 unsigned SrcSize = TRI->getRegSizeInBits(SrcOp.getReg(), *MRI);
1528 if (!DstOp.getSubReg() && !SrcOp
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H A DMachineScheduler.cpp1733 const MachineOperand &SrcOp = Copy->getOperand(1); local
1734 Register SrcReg = SrcOp.getReg();
1735 if (!Register::isVirtualRegister(SrcReg) || !SrcOp.readsReg())
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstructionCombining.cpp2301 Value *SrcOp = BCI->getOperand(0); local
2328 ? Builder.CreateInBoundsGEP(SrcEltType, SrcOp, {Ops[1], Ops[2]})
2329 : Builder.CreateGEP(SrcEltType, SrcOp, {Ops[1], Ops[2]});
2346 if (!isa<BitCastInst>(SrcOp) && GEP.accumulateConstantOffset(DL, Offset)) {
2352 if (isa<AllocaInst>(SrcOp) || isAllocationFn(SrcOp, &TLI)) {
2365 return new AddrSpaceCastInst(SrcOp, GEPType);
2366 return new BitCastInst(SrcOp, GEPType);
2376 ? Builder.CreateInBoundsGEP(SrcEltType, SrcOp, NewIndices)
2377 : Builder.CreateGEP(SrcEltType, SrcOp, NewIndice
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H A DInstCombineCasts.cpp1168 if (auto *SrcOp = dyn_cast<Instruction>(Src))
1169 if (SrcOp->hasOneUse())
1170 replaceAllDbgUsesWith(*SrcOp, *Res, CI, DT);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Analysis/
H A DInstructionSimplify.cpp3374 Value *SrcOp = LI->getOperand(0); local
3375 Type *SrcTy = SrcOp->getType();
3384 if (Value *V = SimplifyICmpInst(Pred, SrcOp,
3391 if (Value *V = SimplifyICmpInst(Pred, SrcOp, RI->getOperand(0),
3404 SrcOp, RI->getOperand(0), Q,
3410 if (SrcOp == RI->getOperand(0)) {
3429 SrcOp, Trunc, Q, MaxRecurse-1))
3472 if (Value *V = SimplifyICmpInst(Pred, SrcOp, RI->getOperand(0),
3478 if (SrcOp == RI->getOperand(0)) {
3496 if (Value *V = SimplifyICmpInst(Pred, SrcOp, Trun
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp161 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT,
163 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT,
1750 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
1753 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, EVT SlotVT,
1755 return EmitStackConvert(SrcOp, SlotVT, DestVT, dl, DAG.getEntryNode());
1758 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, EVT SlotVT,
1763 SrcOp.getValueType().getTypeForEVT(*DAG.getContext()));
1771 unsigned SrcSize = SrcOp.getValueSizeInBits();
1782 Store = DAG.getTruncStore(Chain, dl, SrcOp, FIPtr, PtrInfo,
1787 DAG.getStore(Chain, dl, SrcOp, FIPt
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp8167 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp, unsigned NumBits,
8173 SrcOp = DAG.getBitcast(ShVT, SrcOp);
8176 return DAG.getBitcast(VT, DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal));
8179 static SDValue LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, const SDLoc &dl,
8185 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
21424 for (SDValue &SrcOp : SrcOps)
21425 SrcMask->push_back(SrcOpMap[SrcOp]);
24043 SDValue SrcOp, uint64_t ShiftAmt,
24049 if (VT != SrcOp
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