Searched refs:Shr (Results 1 - 12 of 12) sorted by relevance
| /freebsd-13-stable/contrib/llvm-project/clang/include/clang/AST/ |
| H A D | StmtVisitor.h | 129 BINOP_FALLBACK(Shr)
|
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineSimplifyDemanded.cpp | 520 if (Instruction *Shr = dyn_cast<Instruction>(I->getOperand(0)))
521 if (Value *R = simplifyShrShlDemandedBits(Shr, *ShrAmt, I, *SA,
962 InstCombiner::simplifyShrShlDemandedBits(Instruction *Shr, const APInt &ShrOp1, argument
969 Value *VarX = Shr->getOperand(0);
985 bool isLshr = (Shr->getOpcode() == Instruction::LShr);
1001 if (!Shr->hasOneUse())
1015 if (cast<BinaryOperator>(Shr)->isExact())
|
| H A D | InstCombineCompares.cpp | 2187 BinaryOperator *Shr,
2191 Value *X = Shr->getOperand(0);
2193 if (Cmp.isEquality() && Shr->isExact() && Shr->hasOneUse() &&
2198 if (Cmp.isEquality() && match(Shr->getOperand(0), m_APInt(ShiftVal)))
2199 return foldICmpShrConstConst(Cmp, Shr->getOperand(1), C, *ShiftVal);
2202 if (!match(Shr->getOperand(1), m_APInt(ShiftAmt)))
2212 bool IsAShr = Shr->getOpcode() == Instruction::AShr;
2213 bool IsExact = Shr->isExact();
2214 Type *ShrTy = Shr
2186 foldICmpShrConstant(ICmpInst &Cmp, BinaryOperator *Shr, const APInt &C) argument
[all...] |
| H A D | InstCombineInternal.h | 873 Instruction *Shr, const APInt &ShrOp1, Instruction *Shl,
965 Instruction *foldICmpShrConstant(ICmpInst &Cmp, BinaryOperator *Shr,
|
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Transforms/Utils/ |
| H A D | SimplifyIndVar.cpp | 770 /// Annotate the Shr in (X << IVOperand) >> C as exact using the
786 BinaryOperator *Shr = cast<BinaryOperator>(U); local
787 if (!Shr->isExact() && IVRange.getUnsignedMin().uge(*C)) {
788 Shr->setIsExact(true);
|
| /freebsd-13-stable/contrib/llvm-project/clang/lib/AST/Interp/ |
| H A D | Interp.h | 842 // Shr, Shl
896 inline bool Shr(InterpState &S, CodePtr OpPC) {
|
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 1491 auto Shr = MIRBuilder.buildLShr(SrcTy, SrcReg, ShiftAmt); local
1492 MIRBuilder.buildTrunc(MI.getOperand(I), Shr);
5169 auto Shr = MIRBuilder.buildLShr(SrcIntTy, Src, ShiftAmt);
5170 MIRBuilder.buildTrunc(Dst, Shr);
|
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPULegalizerInfo.cpp | 1802 auto Shr = B.buildAShr(S64, FractMask, Exp);
1803 auto Not = B.buildNot(S64, Shr);
|
| H A D | AMDGPUISelLowering.cpp | 2165 SDValue Shr = DAG.getNode(ISD::SRA, SL, MVT::i64, FractMask, Exp); local
2166 SDValue Not = DAG.getNOT(SL, Shr, MVT::i64);
|
| /freebsd-13-stable/contrib/llvm-project/clang/lib/CodeGen/ |
| H A D | CGExprScalar.cpp | 818 HANDLEBINOP(Shr)
4766 COMPOUND_OP(Shr);
|
| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeDAG.cpp | 2447 SDValue Shr = DAG.getNode(ISD::SRL, dl, SrcVT, Op0, ShiftConst);
2450 SDValue Or = DAG.getNode(ISD::OR, dl, SrcVT, And, Shr);
|
| H A D | DAGCombiner.cpp | 21334 SDValue Shr = DAG.getNode(ISD::SRA, SDLoc(N0), VT, Shl, ShrAmt); local
21336 return DAG.getNode(ISD::AND, DL, VT, Shr, N3);
|
Completed in 273 milliseconds