Searched refs:RegOp (Results 1 - 25 of 32) sorted by relevance

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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrFoldTables.h30 // Do not insert the reverse map (MemOp -> RegOp) into the table.
34 // Do not insert the forward map (RegOp -> MemOp) into the table.
44 // Used for RegOp->MemOp conversion. Encoded as Log2(Align) + 1 to allow 0
86 const X86MemoryFoldTableEntry *lookupTwoAddrFoldTable(unsigned RegOp);
90 const X86MemoryFoldTableEntry *lookupFoldTable(unsigned RegOp, unsigned OpNum);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiInstPrinter.cpp214 const MCOperand &RegOp) {
215 assert(RegOp.isReg() && "Register operand expected");
219 OS << "%" << LanaiInstPrinter::getRegisterName(RegOp.getReg());
240 const MCOperand &RegOp = MI->getOperand(OpNo); local
249 printMemoryBaseRegister(OS, AluCode, RegOp);
255 const MCOperand &RegOp = MI->getOperand(OpNo); local
259 assert(OffsetOp.isReg() && RegOp.isReg() && "Registers expected.");
265 OS << "%" << getRegisterName(RegOp.getReg());
276 const MCOperand &RegOp = MI->getOperand(OpNo); local
285 printMemoryBaseRegister(OS, AluCode, RegOp);
213 printMemoryBaseRegister(raw_ostream &OS, const unsigned AluCode, const MCOperand &RegOp) argument
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/BPF/MCTargetDesc/
H A DBPFInstPrinter.cpp67 const MCOperand &RegOp = MI->getOperand(OpNo); local
71 assert(RegOp.isReg() && "Register operand not a register");
72 O << getRegisterName(RegOp.getReg());
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRAsmPrinter.cpp96 const MachineOperand &RegOp = MI->getOperand(OpNum); local
98 assert(RegOp.isReg() && "Operand must be a register when you're"
100 Register Reg = RegOp.getReg();
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineInstrBuilder.h495 /// Get all register state flags from machine operand \p RegOp.
496 inline unsigned getRegState(const MachineOperand &RegOp) { argument
497 assert(RegOp.isReg() && "Not a register operand");
498 return getDefRegState(RegOp.isDef()) | getImplRegState(RegOp.isImplicit()) |
499 getKillRegState(RegOp.isKill()) | getDeadRegState(RegOp.isDead()) |
500 getUndefRegState(RegOp.isUndef()) |
501 getInternalReadRegState(RegOp.isInternalRead()) |
502 getDebugRegState(RegOp
[all...]
H A DMachineInstr.h487 const MachineOperand *RegOp =
491 return RegOp == adl_end(debug_operands()) ? nullptr : RegOp;
494 MachineOperand *RegOp =
498 return RegOp == adl_end(debug_operands()) ? nullptr : RegOp;
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AVR/MCTargetDesc/
H A DAVRMCCodeEmitter.cpp137 auto RegOp = MI.getOperand(OpNo); local
140 assert(RegOp.isReg() && "Expected register operand");
144 switch (RegOp.getReg()) {
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiAsmPrinter.cpp130 unsigned RegOp = OpNo + 1; local
131 if (RegOp >= MI->getNumOperands())
133 const MachineOperand &MO = MI->getOperand(RegOp);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsAsmPrinter.cpp586 unsigned RegOp = OpNum; local
592 RegOp = (Subtarget->isLittle()) ? OpNum + 1 : OpNum;
595 RegOp = (Subtarget->isLittle()) ? OpNum : OpNum + 1;
598 RegOp = OpNum + 1;
600 if (RegOp >= MI->getNumOperands())
602 const MachineOperand &MO = MI->getOperand(RegOp);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIFoldOperands.cpp1419 const MachineOperand *RegOp = nullptr; local
1425 RegOp = Src1;
1428 RegOp = Src0;
1440 return std::make_pair(RegOp, OMod);
1470 const MachineOperand *RegOp; local
1472 std::tie(RegOp, OMod) = isOMod(MI);
1473 if (OMod == SIOutMods::NONE || !RegOp->isReg() ||
1474 RegOp->getSubReg() != AMDGPU::NoSubRegister ||
1475 !hasOneNonDBGUseInst(*MRI, RegOp->getReg()))
1478 MachineInstr *Def = MRI->getVRegDef(RegOp
[all...]
H A DSIInstrInfo.cpp980 MachineOperand RegOp = Cond[1]; local
981 RegOp.setImplicit(false);
984 .add(RegOp);
994 MachineOperand RegOp = Cond[1]; local
995 RegOp.setImplicit(false);
998 .add(RegOp);
1849 MachineOperand &RegOp,
1851 Register Reg = RegOp.getReg();
1852 unsigned SubReg = RegOp.getSubReg();
1853 bool IsKill = RegOp
1848 swapRegAndNonRegOperand(MachineInstr &MI, MachineOperand &RegOp, MachineOperand &NonRegOp) argument
6929 auto &RegOp = MI.getOperand(1 + 2 * I); local
[all...]
H A DGCNHazardRecognizer.cpp126 const MachineOperand *RegOp = TII->getNamedOperand(RegInstr, local
128 return RegOp->getImm() & AMDGPU::Hwreg::ID_MASK_;
H A DAMDGPUMachineCFGStructurizer.cpp1882 MachineOperand RegOp = MachineOperand::CreateReg(Reg, false, false, true);
1883 ArrayRef<MachineOperand> Cond(RegOp);
2341 MachineOperand RegOp =
2343 ArrayRef<MachineOperand> Cond(RegOp);
2400 MachineOperand RegOp = MachineOperand::CreateReg(Reg, false, false, true);
2401 ArrayRef<MachineOperand> Cond(RegOp);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/BPF/AsmParser/
H A DBPFAsmParser.cpp89 struct RegOp { struct in struct:__anon4071::BPFOperand
100 RegOp Reg;
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCCodeEmitter.cpp1626 unsigned RegOp = CurOp++;
1633 emitMemModRMByte(MI, FirstMemOp, getX86RegNum(MI.getOperand(RegOp)),
1639 unsigned RegOp = CurOp++;
1643 emitRegModRMByte(MI.getOperand(RegOp), 0, OS);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/AsmParser/
H A DX86Operand.h44 struct RegOp { struct in struct:llvm::final
74 struct RegOp Reg;
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachinePipeliner.cpp393 MachineOperand &RegOp = PI.getOperand(i); local
394 if (RegOp.getSubReg() == 0)
404 .addReg(RegOp.getReg(), getRegState(RegOp),
405 RegOp.getSubReg());
407 RegOp.setReg(NewReg);
408 RegOp.setSubReg(0);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Lanai/AsmParser/
H A DLanaiAsmParser.cpp122 struct RegOp { struct in struct:__anon4170::LanaiOperand
139 struct RegOp Reg;
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMAsmPrinter.cpp398 unsigned RegOp = FirstHalf ? OpNum : OpNum + 1; local
399 if (RegOp >= MI->getNumOperands())
401 const MachineOperand &MO = MI->getOperand(RegOp);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp709 MachineOperand &RegOp = I.getOperand(1); local
710 RegOp.setReg(SubRegCopy.getReg(0));
835 MachineOperand &RegOp = I.getOperand(1); local
836 RegOp.setReg(PromoteReg);
2071 MachineOperand &RegOp = I.getOperand(0); local
2072 RegOp.setReg(DefGPRReg);
4595 MachineOperand &RegOp = I.getOperand(1); local
4596 RegOp.setReg(Reg);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Sparc/AsmParser/
H A DSparcAsmParser.cpp232 struct RegOp { struct in class:__anon4304::SparcOperand
249 struct RegOp Reg;
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/AsmParser/
H A DSystemZAsmParser.cpp103 struct RegOp { struct in class:__anon4315::SystemZOperand
133 RegOp Reg;
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/VE/AsmParser/
H A DVEAsmParser.cpp169 struct RegOp { struct in class:__anon4344::VEOperand
199 struct RegOp Reg;
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGRRList.cpp1336 if (const auto *RegOp = dyn_cast<RegisterMaskSDNode>(Op.getNode()))
1337 return RegOp->getRegMask();
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonConstExtenders.cpp1779 const MachineOperand &RegOp = MI.getOperand(IsAddi ? 1 : 2); local
1781 assert(Ex.Rs == RegOp && EV == ImmOp && Ex.Neg != IsAddi &&

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