/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARC/ |
H A D | ARCISelLowering.cpp | 37 const SmallVectorImpl<CCValAssign> &RVLocs, 244 SmallVector<CCValAssign, 16> RVLocs; local 246 CCState RetCCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, 365 return lowerCallResult(Chain, Glue, RVLocs, dl, DAG, InVals); 371 const SmallVectorImpl<CCValAssign> &RVLocs, 376 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { 377 const CCValAssign &VA = RVLocs[i]; 597 SmallVector<CCValAssign, 16> RVLocs; local 598 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context); 617 SmallVector<CCValAssign, 16> RVLocs; local 370 lowerCallResult(SDValue Chain, SDValue Glue, const SmallVectorImpl<CCValAssign> &RVLocs, SDLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) argument [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/VE/ |
H A D | VEISelLowering.cpp | 69 SmallVector<CCValAssign, 16> RVLocs; local 70 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context); 81 SmallVector<CCValAssign, 16> RVLocs; local 84 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, 94 for (unsigned i = 0; i != RVLocs.size(); ++i) { 95 CCValAssign &VA = RVLocs[i]; 444 SmallVector<CCValAssign, 16> RVLocs; local 445 CCState RVInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(), RVLocs, 456 for (unsigned i = 0; i != RVLocs.size(); ++i) { 457 CCValAssign &VA = RVLocs[ [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/BPF/ |
H A D | BPFISelLowering.cpp | 449 SmallVector<CCValAssign, 16> RVLocs; local 453 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext()); 467 for (unsigned i = 0; i != RVLocs.size(); ++i) { 468 CCValAssign &VA = RVLocs[i]; 495 SmallVector<CCValAssign, 16> RVLocs; local 496 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext()); 508 for (auto &Val : RVLocs) {
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelLowering.cpp | 562 SmallVectorImpl<CCValAssign> &RVLocs, 729 SmallVector<CCValAssign, 16> RVLocs; local 730 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context); 744 SmallVector<CCValAssign, 16> RVLocs; local 751 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, 755 AnalyzeReturnValues(CCInfo, RVLocs, Outs); 761 for (unsigned i = 0; i != RVLocs.size(); ++i) { 762 CCValAssign &VA = RVLocs[i]; 940 SmallVector<CCValAssign, 16> RVLocs; local 941 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, 561 AnalyzeReturnValues(CCState &State, SmallVectorImpl<CCValAssign> &RVLocs, const SmallVectorImpl<ArgT> &Args) argument [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/XCore/ |
H A D | XCoreISelLowering.cpp | 1063 const SmallVectorImpl<CCValAssign> &RVLocs, 1068 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { 1069 const CCValAssign &VA = RVLocs[i]; 1126 SmallVector<CCValAssign, 16> RVLocs; local 1128 CCState RetCCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, 1230 return LowerCallResult(Chain, InFlag, RVLocs, dl, DAG, InVals); 1428 SmallVector<CCValAssign, 16> RVLocs; local 1429 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context); 1450 SmallVector<CCValAssign, 16> RVLocs; local 1453 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, 1062 LowerCallResult(SDValue Chain, SDValue InFlag, const SmallVectorImpl<CCValAssign> &RVLocs, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) argument [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Lanai/ |
H A D | LanaiISelLowering.cpp | 540 SmallVector<CCValAssign, 16> RVLocs; local 543 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, 553 for (unsigned i = 0; i != RVLocs.size(); ++i) { 554 CCValAssign &VA = RVLocs[i]; 779 SmallVector<CCValAssign, 16> RVLocs; local 780 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, 786 for (unsigned I = 0; I != RVLocs.size(); ++I) { 787 Chain = DAG.getCopyFromReg(Chain, DL, RVLocs[I].getLocReg(), 788 RVLocs[I].getValVT(), InFlag)
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 214 SmallVector<CCValAssign, 16> RVLocs; local 217 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, 230 i != RVLocs.size(); 232 CCValAssign &VA = RVLocs[i]; 252 VA = RVLocs[++i]; // skip ahead to next loc 297 SmallVector<CCValAssign, 16> RVLocs; local 300 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, 314 for (unsigned i = 0; i != RVLocs.size(); ++i) { 315 CCValAssign &VA = RVLocs[i]; 343 if (i+1 < RVLocs 979 SmallVector<CCValAssign, 16> RVLocs; local 1287 SmallVector<CCValAssign, 16> RVLocs; local [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMFastISel.cpp | 2032 SmallVector<CCValAssign, 16> RVLocs; local 2033 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, RVLocs, *Context); 2037 if (RVLocs.size() == 2 && RetVT == MVT::f64) { 2040 MVT DestVT = RVLocs[0].getValVT(); 2045 .addReg(RVLocs[0].getLocReg()) 2046 .addReg(RVLocs[1].getLocReg())); 2048 UsedRegs.push_back(RVLocs[0].getLocReg()); 2049 UsedRegs.push_back(RVLocs[1].getLocReg()); 2054 assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!"); 2055 MVT CopyVT = RVLocs[ 2214 SmallVector<CCValAssign, 16> RVLocs; local 2321 SmallVector<CCValAssign, 16> RVLocs; local [all...] |
H A D | ARMISelLowering.cpp | 2075 SmallVector<CCValAssign, 16> RVLocs; local 2076 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, 2081 for (unsigned i = 0; i != RVLocs.size(); ++i) { 2082 CCValAssign VA = RVLocs[i]; 2101 VA = RVLocs[++i]; // skip ahead to next loc 2115 VA = RVLocs[++i]; // skip ahead to next loc 2119 VA = RVLocs[++i]; // skip ahead to next loc 2888 SmallVector<CCValAssign, 16> RVLocs; local 2889 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context); 2933 SmallVector<CCValAssign, 16> RVLocs; local [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AVR/ |
H A D | AVRISelLowering.cpp | 1296 SmallVector<CCValAssign, 16> RVLocs; local 1297 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, 1308 for (CCValAssign const &RVLoc : RVLocs) { 1327 SmallVector<CCValAssign, 16> RVLocs; local 1328 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context); 1343 SmallVector<CCValAssign, 16> RVLocs; local 1346 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, 1361 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { 1362 CCValAssign &VA = RVLocs[i];
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCFastISel.cpp | 1505 SmallVector<CCValAssign, 16> RVLocs; local 1506 CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context); 1508 CCValAssign &VA = RVLocs[0]; 1509 assert(RVLocs.size() == 1 && "No support for multi-reg return values!"); 1587 SmallVector<CCValAssign, 16> RVLocs; local 1588 CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, RVLocs, *Context); 1590 if (RVLocs.size() > 1)
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H A D | PPCISelLowering.cpp | 5181 SmallVector<CCValAssign, 16> RVLocs; local 5182 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, 5191 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { 5192 CCValAssign &VA = RVLocs[i]; 5202 VA = RVLocs[++i]; // skip ahead to next loc 7762 SmallVector<CCValAssign, 16> RVLocs; local 7763 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context); 7776 SmallVector<CCValAssign, 16> RVLocs; local 7777 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, 7788 for (unsigned i = 0, RealResIdx = 0; i != RVLocs [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.cpp | 186 SmallVector<CCValAssign, 16> RVLocs; local 187 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context); 204 SmallVector<CCValAssign, 16> RVLocs; local 207 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, 220 for (unsigned i = 0; i != RVLocs.size(); ++i) { 221 CCValAssign &VA = RVLocs[i]; 329 SmallVector<CCValAssign, 16> RVLocs; local 331 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, 340 for (unsigned i = 0; i != RVLocs.size(); ++i) { 342 if (RVLocs[ [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsFastISel.cpp | 1282 SmallVector<CCValAssign, 16> RVLocs; local 1283 MipsCCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context); 1290 if (RVLocs.size() != 1) 1293 MVT CopyVT = RVLocs[0].getValVT(); 1303 ResultReg).addReg(RVLocs[0].getLocReg()); 1304 CLI.InRegs.push_back(RVLocs[0].getLocReg());
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H A D | MipsISelLowering.cpp | 3497 SmallVector<CCValAssign, 16> RVLocs; local 3498 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, 3507 for (unsigned i = 0; i != RVLocs.size(); ++i) { 3508 CCValAssign &VA = RVLocs[i]; 3511 SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(), 3512 RVLocs[i].getLocVT(), InFlag); 3777 SmallVector<CCValAssign, 16> RVLocs; local 3778 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context); 3810 SmallVector<CCValAssign, 16> RVLocs; local 3814 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DA [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVISelLowering.cpp | 2425 SmallVector<CCValAssign, 16> RVLocs; local 2426 CCState RetCCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext()); 2430 for (auto &VA : RVLocs) { 2459 SmallVector<CCValAssign, 16> RVLocs; local 2460 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context); 2482 SmallVector<CCValAssign, 16> RVLocs; local 2485 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, 2495 for (unsigned i = 0, e = RVLocs.size(); i < e; ++i) { 2497 CCValAssign &VA = RVLocs[i];
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86FastISel.cpp | 3541 SmallVector<CCValAssign, 16> RVLocs; local 3542 CCState CCRetInfo(CC, IsVarArg, *FuncInfo.MF, RVLocs, 3548 for (unsigned i = 0; i != RVLocs.size(); ++i) { 3549 CCValAssign &VA = RVLocs[i]; 3591 CLI.NumResultRegs = RVLocs.size();
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H A D | X86ISelLowering.cpp | 2552 SmallVector<CCValAssign, 16> RVLocs; local 2553 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context); 2638 SmallVector<CCValAssign, 16> RVLocs; local 2639 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext()); 2643 for (unsigned I = 0, OutsIndex = 0, E = RVLocs.size(); I != E; 2645 CCValAssign &VA = RVLocs[I]; 2719 Passv64i1ArgInRegs(dl, DAG, ValToCopy, RetVals, VA, RVLocs[++I], 2724 MF.getRegInfo().disableCalleeSavedRegister(RVLocs[I].getLocReg()); 2983 SmallVector<CCValAssign, 16> RVLocs; local 2984 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64FastISel.cpp | 3161 SmallVector<CCValAssign, 16> RVLocs; local 3162 CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context); 3166 if (RVLocs.size() != 1) 3170 MVT CopyVT = RVLocs[0].getValVT(); 3179 .addReg(RVLocs[0].getLocReg()); 3180 CLI.InRegs.push_back(RVLocs[0].getLocReg());
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H A D | AArch64ISelLowering.cpp | 4046 SmallVector<CCValAssign, 16> RVLocs; local 4048 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, 4053 for (unsigned i = 0; i != RVLocs.size(); ++i) { 4054 CCValAssign VA = RVLocs[i]; 4761 SmallVector<CCValAssign, 16> RVLocs; local 4762 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context); 4778 SmallVector<CCValAssign, 16> RVLocs; local 4779 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, 4787 for (unsigned i = 0, realRVLocIdx = 0; i != RVLocs.size(); 4789 CCValAssign &VA = RVLocs[ [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIISelLowering.cpp | 2370 SmallVector<CCValAssign, 16> RVLocs; 2371 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context); 2395 SmallVector<CCValAssign, 48> RVLocs; local 2399 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, 2425 for (unsigned I = 0, RealRVLocIdx = 0, E = RVLocs.size(); I != E; 2427 CCValAssign &VA = RVLocs[I]; 2493 SmallVector<CCValAssign, 16> RVLocs; local 2494 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, 2499 for (unsigned i = 0; i != RVLocs.size(); ++i) { 2500 CCValAssign VA = RVLocs[ [all...] |