/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | ReachingDefAnalysis.h | 141 /// PhysReg that reaches MI, relative to the begining of MI's basic block. 142 int getReachingDef(MachineInstr *MI, int PhysReg) const; 144 /// Return whether A and B use the same def of PhysReg. 145 bool hasSameReachingDef(MachineInstr *A, MachineInstr *B, int PhysReg) const; 149 bool isReachingDefLiveOut(MachineInstr *MI, int PhysReg) const; 151 /// Return the local MI that produces the live out value for PhysReg, or 154 int PhysReg) const; 158 MachineInstr *getUniqueReachingMIDef(MachineInstr *MI, int PhysReg) const; 170 bool hasLocalDefBefore(MachineInstr *MI, int PhysReg) const; 174 bool isRegUsedAfter(MachineInstr *MI, int PhysReg) cons [all...] |
H A D | LiveRegMatrix.h | 88 /// assigned to PhysReg or its aliases. This interference could be resolved 98 /// regmask operand that doesn't preserve PhysReg. This typically means 99 /// VirtReg is live across a call, and PhysReg isn't call-preserved. 103 /// Check for interference before assigning VirtReg to PhysReg. 104 /// If this function returns IK_Free, it is legal to assign(VirtReg, PhysReg). 107 InterferenceKind checkInterference(LiveInterval &VirtReg, unsigned PhysReg); 110 /// assignment to PhysReg. If this function returns true, there is 112 /// assigned to PhysReg. If this function returns false, PhysReg is free at 114 bool checkInterference(SlotIndex Start, SlotIndex End, unsigned PhysReg); [all...] |
H A D | LiveIntervalCalc.h | 54 void extendToUses(LiveRange &LR, MCRegister PhysReg) { argument 55 extendToUses(LR, PhysReg, LaneBitmask::getAll());
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H A D | MachineLoopUtils.h | 40 /// Return true if PhysReg is live outside the loop, i.e. determine if it 42 bool isRegLiveInExitBlocks(MachineLoop *Loop, int PhysReg);
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H A D | RegisterClassInfo.h | 111 /// overlaps PhysReg, or 0 if Reg doesn't overlap a CalleeSavedAliases. 112 unsigned getLastCalleeSavedAlias(unsigned PhysReg) const { 113 assert(Register::isPhysicalRegister(PhysReg)); 114 if (PhysReg < CalleeSavedAliases.size()) 115 return CalleeSavedAliases[PhysReg];
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | ReachingDefAnalysis.cpp | 32 static bool isValidRegUseOf(const MachineOperand &MO, int PhysReg) { argument 33 return isValidRegUse(MO) && MO.getReg() == PhysReg; 40 static bool isValidRegDefOf(const MachineOperand &MO, int PhysReg) { argument 41 return isValidRegDef(MO) && MO.getReg() == PhysReg; 61 for (MCRegUnitIterator Unit(LI.PhysReg, TRI); Unit.isValid(); ++Unit) { 257 int ReachingDefAnalysis::getReachingDef(MachineInstr *MI, int PhysReg) const { 265 for (MCRegUnitIterator Unit(PhysReg, TRI); Unit.isValid(); ++Unit) { 277 int PhysReg) const { 278 return getInstFromId(MI->getParent(), getReachingDef(MI, PhysReg)); 282 int PhysReg) cons [all...] |
H A D | LiveRegMatrix.cpp | 81 LiveInterval &VRegInterval, unsigned PhysReg, 84 for (MCRegUnitMaskIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { 96 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { 104 void LiveRegMatrix::assign(LiveInterval &VirtReg, unsigned PhysReg) { argument 106 << printReg(PhysReg, TRI) << ':'); 108 VRM->assignVirt2Phys(VirtReg.reg, PhysReg); 111 TRI, VirtReg, PhysReg, [&](unsigned Unit, const LiveRange &Range) { 122 Register PhysReg = VRM->getPhys(VirtReg.reg); local 124 << printReg(PhysReg, TRI) << ':'); 127 foreachUnit(TRI, VirtReg, PhysReg, 80 foreachUnit(const TargetRegisterInfo *TRI, LiveInterval &VRegInterval, unsigned PhysReg, Callable Func) argument 146 checkRegMaskInterference(LiveInterval &VirtReg, unsigned PhysReg) argument 164 checkRegUnitInterference(LiveInterval &VirtReg, unsigned PhysReg) argument 186 checkInterference(LiveInterval &VirtReg, unsigned PhysReg) argument 209 checkInterference(SlotIndex Start, SlotIndex End, unsigned PhysReg) argument [all...] |
H A D | RegAllocFast.cpp | 87 MCPhysReg PhysReg = 0; ///< Currently held here. member in struct:__anon3551::RegAllocFast::LiveReg 140 void setPhysRegState(MCPhysReg PhysReg, unsigned NewState); 143 void markRegUsedInInstr(MCPhysReg PhysReg) { argument 144 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) 149 bool isRegUsedInInstr(MCPhysReg PhysReg) const { 150 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) 198 void definePhysReg(MachineBasicBlock::iterator MI, MCPhysReg PhysReg, 200 unsigned calcSpillCost(MCPhysReg PhysReg) const; 201 void assignVirtToPhysReg(LiveReg &, MCPhysReg PhysReg); 218 bool setPhysReg(MachineInstr &MI, MachineOperand &MO, MCPhysReg PhysReg); 242 setPhysRegState(MCPhysReg PhysReg, unsigned NewState) argument 343 reload(MachineBasicBlock::iterator Before, Register VirtReg, MCPhysReg PhysReg) argument 521 definePhysReg(MachineBasicBlock::iterator MI, MCPhysReg PhysReg, RegState NewState) argument 611 assignVirtToPhysReg(LiveReg &LR, MCPhysReg PhysReg) argument 758 MCPhysReg PhysReg; local 856 setPhysReg(MachineInstr &MI, MachineOperand &MO, MCPhysReg PhysReg) argument 932 MCPhysReg PhysReg = LR.PhysReg; local 955 MCPhysReg PhysReg = defineVirtReg(MI, I, Reg, 0); local 1113 MCPhysReg PhysReg = LR.PhysReg; local 1188 MCPhysReg PhysReg = defineVirtReg(MI, I, Reg, CopySrcReg); local [all...] |
H A D | RegisterClassInfo.cpp | 111 unsigned PhysReg = RawOrder[i]; local 113 if (Reserved.test(PhysReg)) 115 unsigned Cost = TRI->getCostPerUse(PhysReg); 118 if (CalleeSavedAliases[PhysReg] && 119 !STI.ignoreCSRForAllocationOrder(*MF, PhysReg)) 120 // PhysReg aliases a CSR, save it for later. 121 CSRAlias.push_back(PhysReg); 125 RCI.Order[N++] = PhysReg; 134 unsigned PhysReg = CSRAlias[i]; local 135 unsigned Cost = TRI->getCostPerUse(PhysReg); [all...] |
H A D | RegisterCoalescer.h | 62 CoalescerPair(unsigned VirtReg, unsigned PhysReg, argument 64 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg) {}
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H A D | AllocationOrder.h | 90 /// Return true if PhysReg is a preferred register. 91 bool isHint(unsigned PhysReg) const { return is_contained(Hints, PhysReg); }
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H A D | RegAllocGreedy.cpp | 298 /// be mapped to the evictor Vreg and the PhysReg it was evicted from. 314 /// \param PhysReg The physical register Evictee was evicted from. 317 void addEviction(unsigned PhysReg, unsigned Evictor, unsigned Evictee) { argument 319 Evictees[Evictee].second = PhysReg; 322 /// Return the Evictor Vreg which evicted Evictee Vreg from PhysReg. 324 /// \return The Evictor vreg which evicted Evictee vreg from PhysReg. 0 if 325 /// nobody has evicted Evictee from PhysReg. 351 unsigned PhysReg; member in struct:__anon3553::RAGreedy::GlobalSplitCandidate 356 // Interference for PhysReg. 364 PhysReg 524 MCRegister PhysReg; member in struct:__anon3553::RAGreedy::HintInfo 526 HintInfo(BlockFrequency Freq, Register Reg, MCRegister PhysReg) argument 760 Register PhysReg; local 804 Register PhysReg; local 865 canEvictInterference(LiveInterval &VirtReg, Register PhysReg, bool IsHint, EvictionCost &MaxCost, const SmallVirtRegSet &FixedRegisters) argument 962 canEvictInterferenceInRange(LiveInterval &VirtReg, Register PhysReg, SlotIndex Start, SlotIndex End, EvictionCost &MaxCost) argument 1041 evictInterference(LiveInterval &VirtReg, Register PhysReg, SmallVectorImpl<Register> &NewVRegs) argument 1482 unsigned PhysReg = VregEvictorInfo.second; local 2133 calcGapWeights(unsigned PhysReg, SmallVectorImpl<float> &GapWeight) argument [all...] |
H A D | InterferenceCache.h | 44 /// of PhysReg in all basic blocks. 46 /// PhysReg - The register currently represented. 47 unsigned PhysReg = 0; member in class:llvm::InterferenceCache::Entry 68 /// RegUnitInfo - Information tracked about each RegUnit in PhysReg. 90 /// Info for each RegUnit in PhysReg. It is very rare ofr a PHysReg to have 105 PhysReg = 0; 111 unsigned getPhysReg() const { return PhysReg; } 156 // get - Get a valid entry for PhysReg. 157 Entry *get(unsigned PhysReg); 209 /// setPhysReg - Point this cursor to PhysReg' 210 setPhysReg(InterferenceCache &Cache, unsigned PhysReg) argument [all...] |
H A D | InterferenceCache.cpp | 67 InterferenceCache::Entry *InterferenceCache::get(unsigned PhysReg) { argument 68 unsigned E = PhysRegEntries[PhysReg]; 69 if (E < CacheEntries && Entries[E].getPhysReg() == PhysReg) { 85 Entries[E].reset(PhysReg, LIUArray, TRI, MF); 86 PhysRegEntries[PhysReg] = E; 100 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units, ++i) 111 PhysReg = physReg; 117 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { 126 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units, ++i) { 198 if (MachineOperand::clobbersPhysReg(RegMaskBits[i], PhysReg)) { [all...] |
H A D | RegAllocBasic.cpp | 117 bool spillInterferences(LiveInterval &VirtReg, Register PhysReg, 201 // Spill or split all live virtual registers currently unified under PhysReg 204 bool RABasic::spillInterferences(LiveInterval &VirtReg, Register PhysReg, argument 211 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { 221 LLVM_DEBUG(dbgs() << "spilling " << printReg(PhysReg, TRI) 225 // Spill each interfering vreg allocated to PhysReg or an alias. 263 while (Register PhysReg = Order.next()) { 264 // Check for interference in PhysReg 265 switch (Matrix->checkInterference(VirtReg, PhysReg)) { 267 // PhysReg i [all...] |
H A D | VirtRegMap.cpp | 187 void addLiveInsForSubRanges(const LiveInterval &LI, Register PhysReg) const; 267 Register PhysReg) const { 306 MBB->addLiveIn(PhysReg, LaneMask); 321 // assigned PhysReg must be marked as live-in to those blocks. 322 Register PhysReg = VRM->getPhys(VirtReg); local 323 assert(PhysReg != VirtRegMap::NO_PHYS_REG && "Unmapped virtual register."); 326 addLiveInsForSubRanges(LI, PhysReg); 336 MBB->addLiveIn(PhysReg); 342 // Sort and unique MBB LiveIns as we've not checked if SubReg/PhysReg were in 518 Register PhysReg local [all...] |
H A D | MachineRegisterInfo.cpp | 519 bool MachineRegisterInfo::isConstantPhysReg(MCRegister PhysReg) const { 520 assert(Register::isPhysicalRegister(PhysReg)); 523 if (TRI->isConstantPhysReg(PhysReg)) 528 for (MCRegAliasIterator AI(PhysReg, TRI, true); 536 MachineRegisterInfo::isCallerPreservedOrConstPhysReg(MCRegister PhysReg) const { 538 return isConstantPhysReg(PhysReg) || 539 TRI->isCallerPreservedPhysReg(PhysReg, *MF); 586 bool MachineRegisterInfo::isPhysRegModified(MCRegister PhysReg, argument 588 if (UsedPhysRegMask.test(PhysReg)) 591 for (MCRegAliasIterator AI(PhysReg, TR [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIPreAllocateWWMRegs.cpp | 107 for (unsigned PhysReg : RegClassInfo.getOrder(MRI->getRegClass(Reg))) { 108 if (!MRI->isPhysRegUsed(PhysReg) && 109 Matrix->checkInterference(LI, PhysReg) == LiveRegMatrix::IK_Free) { 110 Matrix->assign(LI, PhysReg); 111 assert(PhysReg != 0); 135 Register PhysReg = VRM->getPhys(VirtReg); local 138 PhysReg = TRI->getSubReg(PhysReg, SubReg); 142 MO.setReg(PhysReg); 153 const Register PhysReg local [all...] |
H A D | GCNNSAReassign.cpp | 181 Register PhysReg = VRM->getPhys(Reg); 184 if (!PhysReg) 200 if (Def && Def->isCopy() && Def->getOperand(1).getReg() == PhysReg) 207 if (UseInst->isCopy() && UseInst->getOperand(0).getReg() == PhysReg) 216 VgprBase = PhysReg; 217 else if (VgprBase + I != PhysReg)
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVRegisterInfo.h | 34 MCRegister PhysReg) const override; 36 bool isConstantPhysReg(MCRegister PhysReg) const override;
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsCallLowering.cpp | 108 virtual void markPhysRegUsed(unsigned PhysReg) { argument 109 MIRBuilder.getMRI()->addLiveIn(PhysReg); 110 MIRBuilder.getMBB().addLiveIn(PhysReg); 127 void markPhysRegUsed(unsigned PhysReg) override { 128 MIB.addDef(PhysReg, RegState::Implicit); 139 Register PhysReg = VA.getLocReg(); local 140 if (VT == MVT::f64 && PhysReg >= Mips::A0 && PhysReg <= Mips::A3) { 145 auto Lo = MIRBuilder.buildCopy(s32, Register(PhysReg + (IsEL ? 0 : 1))); 146 auto Hi = MIRBuilder.buildCopy(s32, Register(PhysReg 240 Register PhysReg = VA.getLocReg(); local [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZRegisterInfo.cpp | 44 Register PhysReg = VRM->getPhys(MO.getReg()); local 45 if (SystemZ::GR32BitRegClass.contains(PhysReg)) 47 assert (SystemZ::GRH32BitRegClass.contains(PhysReg) && 112 Register PhysReg = 114 if (PhysReg) { 116 PhysReg = getSubReg(PhysReg, MO->getSubReg()); 118 PhysReg = getMatchingSuperReg(PhysReg, VRRegMO->getSubReg(), 120 if (!MRI->isReserved(PhysReg) [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/VE/ |
H A D | VERegisterInfo.h | 33 bool isConstantPhysReg(MCRegister PhysReg) const override;
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86CallLowering.cpp | 122 void assignValueToReg(Register ValVReg, Register PhysReg, 124 MIB.addUse(PhysReg, RegState::Implicit); 134 MRI.getTargetRegisterInfo()->getRegSizeInBits(PhysReg, MRI); 144 MIRBuilder.buildCopy(PhysReg, ExtReg); 257 void assignValueToReg(Register ValVReg, Register PhysReg, 259 markPhysRegUsed(PhysReg); variable 270 MRI.getTargetRegisterInfo()->getRegSizeInBits(PhysReg, MRI); 274 auto Copy = MIRBuilder.buildCopy(LLT::scalar(PhysRegSize), PhysReg); 279 MIRBuilder.buildCopy(ValVReg, PhysReg); 285 auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg); 307 MIRBuilder.getMRI()->addLiveIn(PhysReg); variable 308 MIRBuilder.getMBB().addLiveIn(PhysReg); variable [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMCallLowering.cpp | 112 void assignValueToReg(Register ValVReg, Register PhysReg, 115 assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?"); 121 MIRBuilder.buildCopy(PhysReg, ExtReg); 122 MIB.addUse(PhysReg, RegState::Implicit); 335 void assignValueToReg(Register ValVReg, Register PhysReg, 338 assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?"); 346 markPhysRegUsed(PhysReg); variable 348 MIRBuilder.buildCopy(ValVReg, PhysReg); 355 auto PhysRegToVReg = MIRBuilder.buildCopy(LLT::scalar(LocSize), PhysReg); 399 virtual void markPhysRegUsed(unsigned PhysReg) 409 MIRBuilder.getMBB().addLiveIn(PhysReg); variable [all...] |