Lines Matching refs:PhysReg
298 /// be mapped to the evictor Vreg and the PhysReg it was evicted from.
314 /// \param PhysReg The physical register Evictee was evicted from.
317 void addEviction(unsigned PhysReg, unsigned Evictor, unsigned Evictee) {
319 Evictees[Evictee].second = PhysReg;
322 /// Return the Evictor Vreg which evicted Evictee Vreg from PhysReg.
324 /// \return The Evictor vreg which evicted Evictee vreg from PhysReg. 0 if
325 /// nobody has evicted Evictee from PhysReg.
351 unsigned PhysReg;
356 // Interference for PhysReg.
364 PhysReg = Reg;
383 /// Candidate info for each PhysReg in AllocationOrder.
471 bool mayRecolorAllInterferences(unsigned PhysReg, LiveInterval &VirtReg,
496 Register PhysReg, unsigned &CostPerUseLimit,
523 /// In case of a physical register Reg == PhysReg.
524 MCRegister PhysReg;
526 HintInfo(BlockFrequency Freq, Register Reg, MCRegister PhysReg)
527 : Freq(Freq), Reg(Reg), PhysReg(PhysReg) {}
534 bool isUnusedCalleeSavedReg(MCRegister PhysReg) const;
760 Register PhysReg;
761 while ((PhysReg = Order.next()))
762 if (!Matrix->checkInterference(VirtReg, PhysReg))
764 if (!PhysReg || Order.isHint())
765 return PhysReg;
767 // PhysReg is available, but there may be a better choice.
786 unsigned Cost = TRI->getCostPerUse(PhysReg);
790 return PhysReg;
792 LLVM_DEBUG(dbgs() << printReg(PhysReg, TRI) << " is available at cost "
795 return CheapReg ? CheapReg : PhysReg;
804 Register PhysReg;
805 while ((PhysReg = Order.next())) {
806 if (PhysReg == PrevReg)
809 MCRegUnitIterator Units(PhysReg, TRI);
816 // If no units have interference, break out with the current PhysReg.
820 if (PhysReg)
823 << printReg(PhysReg, TRI) << '\n');
824 return PhysReg;
857 /// PhysReg can be evicted.
860 /// @param PhysReg Desired register for assignment.
861 /// @param IsHint True when PhysReg is VirtReg's preferred register.
865 bool RAGreedy::canEvictInterference(LiveInterval &VirtReg, Register PhysReg,
869 if (Matrix->checkInterference(VirtReg, PhysReg) > LiveRegMatrix::IK_VirtReg)
886 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
943 (!EnableLocalReassign || !canReassign(*Intf, PhysReg))) {
952 /// Return true if all interferences between VirtReg and PhysReg between
956 /// \param PhysReg Desired register for assignment.
963 Register PhysReg, SlotIndex Start,
968 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
1013 /// \return The PhysReg which is the best candidate for eviction and the
1025 for (auto PhysReg : Order.getOrder()) {
1027 if (!canEvictInterferenceInRange(VirtReg, PhysReg, Start, End,
1032 BestEvicteePhys = PhysReg;
1041 void RAGreedy::evictInterference(LiveInterval &VirtReg, Register PhysReg,
1050 LLVM_DEBUG(dbgs() << "evicting " << printReg(PhysReg, TRI)
1055 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
1073 LastEvicted.addEviction(PhysReg, VirtReg.reg, Intf->reg);
1085 /// Returns true if the given \p PhysReg is a callee saved register and has not
1087 bool RAGreedy::isUnusedCalleeSavedReg(MCRegister PhysReg) const {
1088 MCRegister CSR = RegClassInfo.getLastCalleeSavedAlias(PhysReg);
1092 return !Matrix->isPhysRegUsed(PhysReg);
1138 while (MCRegister PhysReg = Order.next(OrderLimit)) {
1139 if (TRI->getCostPerUse(PhysReg) >= CostPerUseLimit)
1143 if (CostPerUseLimit == 1 && isUnusedCalleeSavedReg(PhysReg)) {
1145 dbgs() << printReg(PhysReg, TRI) << " would clobber CSR "
1146 << printReg(RegClassInfo.getLastCalleeSavedAlias(PhysReg), TRI)
1151 if (!canEvictInterference(VirtReg, PhysReg, false, BestCost,
1156 BestPhys = PhysReg;
1341 if (Cand.PhysReg) {
1375 // that all the through blocks have interference when PhysReg is unset.
1482 unsigned PhysReg = VregEvictorInfo.second;
1485 if (!Evictor || !PhysReg)
1495 if ((PhysReg != Cand.PhysReg) && (PhysReg != FutureEvictedPhysReg))
1502 // PhysReg. This suggest that we will create a local interval during the
1543 for (auto PhysReg : Order.getOrder()) {
1545 Cand.Intf.last(), PhysReg))
1774 // - Candidate intervals can be assigned to Cand.PhysReg.
1861 while (unsigned PhysReg = Order.next()) {
1862 if (IgnoreCSR && isUnusedCalleeSavedReg(PhysReg))
1871 if (i == BestCand || !GlobalCand[i].PhysReg)
1888 Cand.reset(IntfCache, PhysReg);
1893 LLVM_DEBUG(dbgs() << printReg(PhysReg, TRI) << "\tno positive bundles\n");
1896 LLVM_DEBUG(dbgs() << printReg(PhysReg, TRI) << "\tstatic = ";
1904 << printReg(GlobalCand[BestCand].PhysReg, TRI) << '\n';
1971 LLVM_DEBUG(dbgs() << "Split for " << printReg(Cand.PhysReg, TRI) << " in "
1980 assert(!Cand.PhysReg && "Compact region has no physreg");
2129 /// in order to use PhysReg between two entries in SA->UseSlots.
2133 void RAGreedy::calcGapWeights(unsigned PhysReg,
2149 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
2184 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
2301 while (unsigned PhysReg = Order.next()) {
2303 // order to make use of PhysReg between UseSlots[i] and UseSlots[i+1].
2304 calcGapWeights(PhysReg, GapWeight);
2307 if (Matrix->checkRegMaskInterference(VirtReg, PhysReg))
2326 LLVM_DEBUG(dbgs() << printReg(PhysReg, TRI) << ' ' << Uses[SplitBefore]
2454 Register PhysReg = tryLocalSplit(VirtReg, Order, NewVRegs);
2455 if (PhysReg || !NewVRegs.empty())
2456 return PhysReg;
2472 if (Register PhysReg = tryAssign(VirtReg, Order, NewVRegs, FixedRegisters))
2473 return PhysReg;
2480 unsigned PhysReg = tryRegionSplit(VirtReg, Order, NewVRegs);
2481 if (PhysReg || !NewVRegs.empty())
2482 return PhysReg;
2503 /// interfere with \p VirtReg on \p PhysReg (or one of its aliases) may be
2504 /// recolored to free \p PhysReg.
2506 /// the live intervals that need to be recolored in order to free \p PhysReg
2511 RAGreedy::mayRecolorAllInterferences(unsigned PhysReg, LiveInterval &VirtReg,
2516 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
2616 while (Register PhysReg = Order.next()) {
2618 << printReg(PhysReg, TRI) << '\n');
2624 if (Matrix->checkInterference(VirtReg, PhysReg) >
2632 // Early give up on this PhysReg if it is obvious we cannot recolor all
2634 if (!mayRecolorAllInterferences(PhysReg, VirtReg, RecoloringCandidates,
2641 // with VirtReg on PhysReg (or one of its aliases).
2658 // Do as if VirtReg was assigned to PhysReg so that the underlying
2661 Matrix->assign(VirtReg, PhysReg);
2675 return PhysReg;
2679 << printReg(PhysReg, TRI) << '\n');
2727 Register PhysReg = selectOrSplitImpl(*LI, NewVRegs, FixedRegisters,
2733 if (PhysReg == ~0u || (!PhysReg && !LI->empty()))
2736 if (!PhysReg) {
2743 << " succeeded with: " << printReg(PhysReg, TRI) << '\n');
2745 Matrix->assign(*LI, PhysReg);
2787 Register PhysReg,
2795 return PhysReg;
2812 return PhysReg;
2818 return PhysReg;
2876 /// \p PhysReg was used.
2877 /// \return The cost of \p List for \p PhysReg.
2879 unsigned PhysReg) {
2882 if (Info.PhysReg != PhysReg)
2898 // reusing PhysReg for the copy-related live-ranges. Indeed, we evicted
2899 // some register and PhysReg may be available for the other live-ranges.
2904 Register PhysReg = VRM->getPhys(Reg);
2911 << '(' << printReg(PhysReg, TRI) << ")\n");
2928 if (CurrPhys != PhysReg && (!MRI->getRegClass(Reg)->contains(PhysReg) ||
2929 Matrix->checkInterference(LI, PhysReg)))
2940 if (CurrPhys != PhysReg) {
2943 BlockFrequency NewCopiesCost = getBrokenHintFreq(Info, PhysReg);
2957 Matrix->assign(LI, PhysReg);
3023 if (unsigned PhysReg = tryAssign(VirtReg, Order, NewVRegs, FixedRegisters)) {
3029 if (CSRCost.getFrequency() && isUnusedCalleeSavedReg(PhysReg) &&
3031 Register CSRReg = tryAssignCSRFirstTime(VirtReg, Order, PhysReg,
3038 return PhysReg;
3049 if (Register PhysReg =
3058 if (Hint && Hint != PhysReg)
3063 return PhysReg;
3081 Register PhysReg = trySplit(VirtReg, Order, NewVRegs, FixedRegisters);
3082 if (PhysReg || (NewVRegs.size() - NewVRegSizeBefore)) {
3085 return PhysReg;